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| FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM44-10107-1E F2MC-16LX 16-BIT MICROCONTROLLER MB90560 Series HARDWARE MANUAL PREFACE s Objectives and Intended Reader Thank you for purchasing Fujitsu semiconductor products. The MB90560 series was developed as a group of general-purpose models in the FMC-16 LX series, which is a family of original 16-bit single-chip microcontrollers that can be used for application specific ICs (ASICs). This manual is intended for engineers who design products using the MB90560 series of microcontrollers. The manual describes the functions and operation of the MB90560 series. s Trademarks FMC is a registered trademark of Fujitsu Limited and stands for FUJITSU Flexible Microcontroller. i 1. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. 2. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 3. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. 4. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 5. Any semiconductor devices have an inherent chance of failure.You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. 6. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. (c) 1998 FUJITSU LIMITED Printed in Japan ii CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 OVERVIEW ....................................................................................................1 Features .................................................................................................................................................2 Product Lineup .......................................................................................................................................4 Block Diagram ........................................................................................................................................5 Pin Assignments .....................................................................................................................................6 Package Dimensions ............................................................................................................................10 Pin Functions ........................................................................................................................................14 I/O Circuit Types ...................................................................................................................................18 Notes on Handling Devices ..................................................................................................................20 CHAPTER 2 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.7.6 2.7.7 2.7.8 2.7.9 2.8 2.9 2.9.1 2.9.2 2.9.3 2.9.4 CPU ..............................................................................................................23 CPU ......................................................................................................................................................24 Memory Space ......................................................................................................................................26 Memory Maps .......................................................................................................................................28 Addressing ............................................................................................................................................29 Linear addressing ...........................................................................................................................30 Bank addressing ..............................................................................................................................32 Memory Location of Multibyte Data ......................................................................................................34 Registers ...............................................................................................................................................36 Dedicated Registers .............................................................................................................................38 Accumulator (A) ...............................................................................................................................40 Stack Pointers (USP, SSP) .............................................................................................................44 Processor Status (PS) .....................................................................................................................46 Condition code register (PS: CCR) ..................................................................................................48 Register bank pointer (PS: RP) .......................................................................................................50 Interrupt level mask register (PS: ILM) ............................................................................................51 Program Counter (PC) .....................................................................................................................52 Direct Page Register (DPR) ............................................................................................................53 Bank Registers (PCB, DTB, USB, SSB, ADB) ................................................................................54 General-Purpose Registers ..................................................................................................................56 Prefix Codes .........................................................................................................................................58 Bank select prefix (PCB, DTB, ADB, SPB) ......................................................................................60 Common register bank prefix (CMR) ...............................................................................................62 Flag change suppression prefix (NCC) ...........................................................................................63 Restrictions on Prefix Codes ...........................................................................................................64 CHAPTER 3 3.1 3.2 3.3 3.4 3.5 3.6 RESETS .......................................................................................................67 Resets ..................................................................................................................................................68 Reset Causes and Oscillation Stabilization Wait Intervals ...................................................................70 External Reset Pin ................................................................................................................................72 Reset Operation ....................................................................................................................................74 Reset Cause Bits ..................................................................................................................................76 Status of Pins in a Reset ......................................................................................................................78 iii MB90560 series CHAPTER 4 4.1 4.2 4.3 4.4 4.5 4.6 CLOCKS ...................................................................................................... 81 Clocks .................................................................................................................................................. 82 Block Diagram of the Clock Generator ................................................................................................ 84 Clock Selection Register (CKSCR) ...................................................................................................... 86 Clock Mode .......................................................................................................................................... 88 Oscillation Stabilization Wait Interval ................................................................................................... 90 Connection of an Oscillator or an External Clock ................................................................................ 91 CHAPTER 5 5.1 5.2 5.3 5.4 5.5 5.5.1 5.5.2 5.5.3 5.6 5.7 5.8 LOW POWER CONSUMPTION MODE ...................................................... 93 Low Power Consumption Mode ........................................................................................................... 94 Block Diagram of the Low Power Consumption Control Circuit ........................................................... 96 Low Power Mode Control Register (LPMCR) ...................................................................................... 98 CPU Intermittent Operation Mode ...................................................................................................... 102 Standby Mode .................................................................................................................................... 103 Sleep mode ................................................................................................................................... 104 Timebase timer mode ................................................................................................................... 108 Stop mode .................................................................................................................................... 110 Status Change Diagram ..................................................................................................................... 112 Status of Pins in Standby Mode and Reset ....................................................................................... 115 Notes on Using Low Power Consumption Mode ............................................................................... 116 CHAPTER 6 6.1 6.2 6.3 6.3.1 6.3.2 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.5 6.6 6.6.1 6.6.2 6.7 6.7.1 6.7.2 6.8 6.9 6.10 INTERRUPTS ............................................................................................ 119 Interrupts ............................................................................................................................................ 120 Interrupt Causes and Interrupt Vectors .............................................................................................. 122 Interrupt Control Registers and Peripheral Functions ........................................................................ 124 Interrupt control registers (ICR00 to ICR15) ................................................................................ 126 Interrupt control register functions ................................................................................................ 128 Hardware Interrupts ........................................................................................................................... 132 Operation of hardware interrupts .................................................................................................. 136 Processing for interrupt operation ................................................................................................. 138 Procedure for using hardware interrupts ...................................................................................... 139 Multiple interrupts ......................................................................................................................... 140 Hardware interrupt processing time .............................................................................................. 142 Software Interrupts ............................................................................................................................. 144 Interrupt of Extended Intelligent I/O Service (EIOS) ......................................................................... 146 Extended intelligent I/O service (EIOS) descriptor (ISD) ............................................................. 148 Registers of the extended intelligent I/O service (EIOS) descriptor (ISD) ................................... 150 Operation of the extended intelligent I/O service (EIOS) .................................................................. 154 Procedure for using the extended intelligent I/O service (EIOS) ................................................. 155 Processing time of the extended intelligent I/O service (EIOS) ................................................... 156 Exception Processing Interrupt .......................................................................................................... 158 Stack Operations for Interrupt Processing ......................................................................................... 160 Sample Programs for Interrupt Processing ........................................................................................ 162 CHAPTER 7 7.1 7.2 iv SETTING A MODE .................................................................................... 167 Setting a Mode ................................................................................................................................... 168 Mode Pins (MD2 to MD0) .................................................................................................................. 169 MB90560 series 7.3 Mode Data ..........................................................................................................................................170 CHAPTER 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.5 8.5.1 8.5.2 8.6 8.6.1 8.6.2 8.7 8.7.1 8.7.2 8.8 8.8.1 8.8.2 8.9 8.9.1 8.9.2 8.10 I/O PORTS ..................................................................................................173 Overview of I/O Ports ..........................................................................................................................174 Port Register .......................................................................................................................................175 Port 0 .................................................................................................................................................176 Port 0 Registers (PDR0, DDR0, and RDR0) .................................................................................178 Operation of Port 0 ........................................................................................................................180 Port 1 ..................................................................................................................................................182 Port 1 Registers (PDR1, DDR1, and RDR1) .................................................................................184 Operation of Port 1 ........................................................................................................................186 Port 2 ..................................................................................................................................................188 Port 2 Registers (PDR2 and DDR2) ..............................................................................................190 Operation of Port 2 ........................................................................................................................192 Port 3 ..................................................................................................................................................194 Port 3 Registers (PDR3 and DDR3) ..............................................................................................196 Operation of Port 3 ........................................................................................................................198 Port 4 ..................................................................................................................................................200 Port 4 Registers (PDR4 and DDR4) ..............................................................................................202 Operation of Port 4 ........................................................................................................................204 Port 5 ..................................................................................................................................................206 Port 5 Registers (PDR5, DDR5, and ADER) .................................................................................208 Operation of Port 5 ........................................................................................................................210 Port 6 ..................................................................................................................................................212 Port 6 Registers (PDR6 and DDR6) ..............................................................................................214 Operation of Port 6 ........................................................................................................................216 Sample I/O Port Program ...................................................................................................................218 CHAPTER 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 TIMEBASE TIMER ....................................................................................221 Overview of the Timebase Timer ........................................................................................................222 Configuration of the Timebase Timer .................................................................................................224 Timebase Timer Control Register (TBTC) ..........................................................................................226 Timebase Timer Interrupts ..................................................................................................................228 Operation of the Timebase Timer .......................................................................................................230 Usage Notes on the Timebase Timer .................................................................................................232 Sample Program for the Timebase Timer Program ............................................................................234 CHAPTER 10 WATCHDOG TIMER ..................................................................................237 10.1 10.2 10.3 10.4 10.5 10.6 Overview of the Watchdog Timer .......................................................................................................238 Configuration of the Watchdog Timer .................................................................................................239 Watchdog Timer Control Register (WDTC) ........................................................................................240 Operation of the Watchdog Timer .......................................................................................................242 Usage Notes on the Watchdog Timer .................................................................................................244 Sample Program for the Watchdog Timer ..........................................................................................245 CHAPTER 11 16-BIT RELOAD TIMER ............................................................................247 11.1 Overview of the 16-Bit Reload Timer ..................................................................................................248 v MB90560 series 11.2 Configuration of the 16-Bit Reload Timer ........................................................................................... 252 11.3 16-Bit Reload Timer Pins ................................................................................................................... 254 11.4 16-Bit Reload Timer Registers ........................................................................................................... 255 11.4.1 Timer control status register, upper part (TMCSR0, TMCSR1: H) ............................................... 256 11.4.2 Timer control status register, lower part (TMCSR0, TMCSR1: L) ............................................... 258 11.4.3 16-bit timer register (TMR0, TMR1) .............................................................................................. 260 11.4.4 16-bit reload register (TMRLR0, TMRLR1) ................................................................................... 261 11.5 16-Bit Reload Timer Interrupts ........................................................................................................... 262 11.6 Operation of the 16-Bit Reload Timer ................................................................................................ 264 11.6.1 Reload Mode (Internal Clock Mode) ............................................................................................. 266 11.6.2 Single-shot Mode (Internal Clock Mode) ...................................................................................... 268 11.6.3 Event count mode ......................................................................................................................... 270 11.7 Usage Notes on the 16-Bit Reload Timer .......................................................................................... 272 11.8 Sample Programs for the 16-Bit Reload Timer .................................................................................. 273 CHAPTER 12 MULTI-FUNCTION TIMER ........................................................................ 277 12.1 Overview of Multi-function Timer ....................................................................................................... 278 12.2 Block Diagram of Multi-function Timer ............................................................................................... 280 12.3 Register of Multi-Function Timer ........................................................................................................ 284 12.3.1 Registers of 16-bit Free-Run Timer .............................................................................................. 290 12.3.1.1 Compare Clear Register (CPCLR) ......................................................................................... 291 12.3.1.2 Timer Data Register (TCDT) ................................................................................................... 292 12.3.1.3 Timer Control Status Register (TCCS) ................................................................................... 294 12.3.2 Registers of 16-bit Output Compare ............................................................................................. 298 12.3.2.1 Compare Registers (OCCP0~5) ............................................................................................. 299 12.3.2.2 Compare Control Registers (OSC0/1/2/3/4/5) ........................................................................ 300 12.3.3 Registers of 16-bit Input Capture .................................................................................................. 304 12.3.3.1 Input Capture Register (IPCP0~3) .......................................................................................... 305 12.3.3.2 Capture Control Registers (ICS23, ICS01) ............................................................................. 306 12.3.4 Register of 8/16-bit PPG Timer ..................................................................................................... 310 12.3.4.1 PPG Reload Register (PRLH0~5, PRLL0~5) ......................................................................... 311 12.3.4.2 PPG Control Register (PPGC0~5) ......................................................................................... 312 12.3.4.3 PPG Clock Control Register (PCS01/23/45) .......................................................................... 316 12.3.5 Registers of Waveform Generator ................................................................................................ 318 12.3.5.1 8-bit Reload Register (TMRR0/1/2) ........................................................................................ 319 12.3.5.2 8-bit Timer Control Register (DTCR0/1/2) .............................................................................. 320 12.3.5.3 Waveform Control Register (SIGCR) ...................................................................................... 322 12.4 Operation of Multi-Function Timer ..................................................................................................... 324 12.4.1 Operation of 16-bit Free-run Timer ............................................................................................... 326 12.4.2 Operation of 16-bit Output Compare ............................................................................................ 328 12.4.3 Operation of 16-bit Input Capture ................................................................................................. 332 12.4.4 Operation of 8/16-bit PPG Timers ................................................................................................ 334 12.4.5 Operation of Waveform Generator ............................................................................................... 340 12.4.5.1 Operation of Dead-timer Control Circuit ................................................................................. 342 12.4.5.2 Operation of PPG Output and GATE Signal Control Circuit ................................................... 346 12.4.5.3 Operation of DTTI Pin Control ................................................................................................ 348 CHAPTER 13 UART ......................................................................................................... 351 13.1 13.2 vi Overview of UART ............................................................................................................................. 352 Configuration of UART ....................................................................................................................... 354 MB90560 series 13.3 UART Pins ..........................................................................................................................................358 13.4 UART Registers ..................................................................................................................................360 13.4.1 Serial Control Register 1 (SCR0/1) ...............................................................................................362 13.4.2 Serial Mode Control Register (SMR0/1) .......................................................................................364 13.4.3 Serial Status Register (SSR0/1) ..................................................................................................366 13.4.4 Serial Input Data Register (SIDR0/1) and Serial Output Data Register (SOR0/1) ........................368 13.4.5 Communication Prescaler Control Register (CDCR0/1) ................................................................370 13.5 UART Interrupts ..................................................................................................................................372 13.5.1 Reception Interrupt Generation and Flag Set Timing ....................................................................374 13.5.2 Transmission Interrupt Generation and Flag Set Timing ...............................................................375 13.6 UART Baud Rates ..............................................................................................................................376 13.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator ............................................378 13.6.2 Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0) ...................................382 13.6.3 Baud Rates Determined Using the External Clock ........................................................................384 13.7 Operation of UART .............................................................................................................................386 13.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) .....................................................388 13.7.2 Operation in Synchronous Mode (Operation Mode 2) ...................................................................390 13.7.3 Bidirectional Communication Function (Normal Mode) .................................................................392 13.7.4 Master-slave Communication Function (Multiprocessor Mode) ....................................................394 13.8 Notes on Using UART ........................................................................................................................396 13.9 Sample Program for UART .................................................................................................................398 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT ...................................................401 14.1 Overview of the DTP/External Interrupt Circuit ...................................................................................402 14.2 Configuration of the DTP/External Interrupt Circuit ............................................................................404 14.3 DTP/External Interrupt Circuit Pins .....................................................................................................406 14.4 DTP/External Interrupt Circuit Registers .............................................................................................408 14.4.1 DTP/interrupt cause register (EIRR) ..............................................................................................409 14.4.2 DTP/interrupt enable register (ENIR) ..........................................................................................410 14.4.3 Request level setting register (ELVR) .........................................................................................412 14.5 Operation of the DTP/External Interrupt Circuit ..................................................................................414 14.5.1 External interrupt function ............................................................................................................417 14.5.2 DTP function ................................................................................................................................418 14.6 Usage Notes on the DTP/External Interrupt Circuit ............................................................................420 14.7 Sample Programs for the DTP/External Interrupt Circuit ....................................................................422 CHAPTER 15 Delayed Interrupt Generator Module ......................................................427 15.1 15.2 Overview of the Delayed Interrupt Generator Module ........................................................................428 Operation of the Delayed Interrupt Generator Module .......................................................................429 CHAPTER 16 8/10-BIT A/D CONVERTER .......................................................................431 16.1 Overview of the 8/10-Bit A/D Converter ..............................................................................................432 16.2 Configuration of the 8/10-Bit A/D Converter .......................................................................................434 16.3 8/10-Bit A/D Converter Pins ................................................................................................................436 16.4 8/10-Bit A/D Converter Registers .......................................................................................................438 16.4.1 A/D control status register 1 (ADCS1) .........................................................................................439 16.4.2 A/D control status register 0 (ADCS0) .........................................................................................442 MB90560 series vii 16.4.3 A/D data register (ADCR0, 1) ...................................................................................................... 444 16.5 8/10-Bit A/D Converter Interrupts ....................................................................................................... 446 16.6 Operation of the 8/10-Bit A/D Converter ............................................................................................ 447 16.6.1 Conversion using EIOS ............................................................................................................. 450 16.6.2 A/D conversion data protection function ..................................................................................... 452 16.7 Usage Notes on the 8/10-Bit A/D Converter ...................................................................................... 454 16.8 Sample Program 1 for Single Conversion Mode Using EIOS ........................................................... 456 16.9 Sample Program 2 for Continuous Conversion Mode Using EIOS .................................................. 458 16.10 Sample Program 3 for Stop Conversion Mode Using EIOS ............................................................. 461 CHAPTER 17 ADDRESS MATCH DETECTION FUNCTION .......................................... 465 17.1 17.2 Overview of the Address Match Detection Function .......................................................................... 466 Example of Using the Address Match Detection Function ................................................................. 469 CHAPTER 18 ROM MIRRORING FUNCTION SELECTION MODULE ........................... 473 18.1 Overview of the ROM Mirroring Function Selection Module .............................................................. 474 APPENDIX ................................................................................................................... 477 APPENDIX A I/O MAP ..................................................................................................... 479 APPENDIX B INSTRUCTIONS ........................................................................................ 485 B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 Instructions ......................................................................................................................................... 486 Addressing ......................................................................................................................................... 488 Direct Addressing ............................................................................................................................... 490 Indirect Addressing ............................................................................................................................ 496 Number of Execution Cycles .............................................................................................................. 503 Effective-address field ........................................................................................................................ 506 Reading the Instruction List ............................................................................................................... 507 List of F2MC-16LX Instructions .......................................................................................................... 510 Instruction Maps ................................................................................................................................. 523 APPENDIX C 512K-BIT FLASH MEMORY ..................................................................... 545 APPENDIX D EXAMPLE OF FMC-16LX MB90F562 CONNECTION FOR SERIAL WRITING ............................................................................. 551 viii MB90560 series FIGURES Figure 1.3-2 Figure 1.4-1 Figure 1.4-2 Figure 1.4-3 Figure 1.5-1 Figure 1.5-2 Figure 1.5-3 Figure 1.8-1 Figure 2.2-1 Figure 2.3-1 Figure 2.4-1 Figure 2.4-2 Figure 2.4-3 Figure 2.4-4 Figure 2.5-1 Figure 2.5-2 Figure 2.5-3 Figure 2.5-4 Figure 2.6-1 Figure 2.7-1 Figure 2.7-2 Figure 2.7-3 Figure 2.7-4 Figure 2.7-5 Figure 2.7-6 Figure 2.7-7 Figure 2.7-8 Figure 2.7-9 Figure 2.7-10 Figure 2.7-11 Figure 2.7-12 Figure 2.7-13 Figure 2.7-14 Figure 2.7-15 MB90560 series Block diagram ..........................................................................................................................5 Pin assignment of FPT-64P-M09 ............................................................................................6 Pin assignment of FPT-64P-M09 ............................................................................................7 Pin assignment of DIP-64P-M01 .............................................................................................8 Dimensions of FPT-64P-M06 package .................................................................................10 Dimensions of FPT-64P-M09 package .................................................................................11 Dimensions of DIP-64P-M01 package ..................................................................................12 Sample connection of external clock .....................................................................................21 Sample relationship between the F2MC-16LX system and the memory map ......................26 Memory maps ........................................................................................................................28 Linear addressing and bank addressing memory management ...........................................29 Example of direct specified 24-bit physical address in linear addressing .............................30 Example of indirect specified address with a 32-bit general-purpose register in linear addressing ...............................................................................................................30 Sample bank addressing .......................................................................................................33 Storage of multibyte data in RAM ..........................................................................................34 Storage of a multibyte operand .............................................................................................34 Storage of multibyte data in a stack ......................................................................................35 Multibyte data access on a bank boundary ...........................................................................35 Dedicated registers and general-purpose registers .............................................................36 Configuration of dedicated registers ......................................................................................39 Data transfer to the accumulator ...........................................................................................40 Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, zero extension) 41 Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, sign extension) .41 Example of 32-bit data transfer to the accumulator (A) (register indirect) .............................41 Example of AL-AH transfer in the accumulator (A) (16 bits, register indirect) .......................42 Stack operation instruction and stack pointer ........................................................................45 Processor status (PS) configuration ......................................................................................46 Condition code register (CCR) configuration .........................................................................48 Configuration of the register bank pointer (RP) .....................................................................50 Conversion rules for physical address of general-purpose register area ..............................50 Configuration of the interrupt level mask register (ILM) ........................................................51 Program counter (PC) ...........................................................................................................52 Physical address generation by the direct page register (DPR) ............................................53 Example of direct page register (DPR) setting and data access ...........................................53 ix Figure 2.8-1 Figure 2.9-1 Figure 2.9-2 Figure 2.9-3 Figure 3.3-1 Figure 3.3-2 Figure 3.4-1 Figure 3.4-2 Figure 3.5-1 Figure 3.5-2 Figure 4.1-1 Figure 4.2-1 Figure 4.3-1 Figure 4.4-1 Figure 4.5-1 Figure 4.6-1 Figure 4.6-2 Figure 5.1-1 Figure 5.2-1 Figure 5.3-1 Figure 5.4-1 Figure 5.5-1 Figure 5.5-2 Figure 5.5-3 Figure 5.5-4 Figure 5.6-1 Figure 6.1-1 Figure 6.3-1 Figure 6.3-2 Figure 6.3-3 Figure 6.4-1 Figure 6.4-2 Figure 6.4-3 Figure 6.4-4 Figure 6.4-5 Figure 6.4-6 Figure 6.5-1 x Location and configuration of the general-purpose register banks in the memory space .... 56 Interrupt/hold suppression .................................................................................................... 64 Interrupt/hold suppression instructions and prefix codes ..................................................... 65 Consecutive prefix codes ..................................................................................................... 65 Block diagram of internal reset ............................................................................................. 72 Block diagram of internal reset for external pin .................................................................... 73 Reset operation flow ............................................................................................................. 74 Transfer of reset vector and mode data ............................................................................... 75 Block diagram of reset cause bits ......................................................................................... 76 Configuration of reset cause bits (watchdog timer control register) ..................................... 77 Clock supply map ................................................................................................................. 83 Block diagram of the clock generator ................................................................................... 84 Configuration of the clock selection register (CKSCR) ......................................................... 86 Status change diagram for machine clock selection ............................................................ 89 Operation when oscillation starts .......................................................................................... 90 Example of connecting a crystal or ceramic oscillator to the microcontroller ....................... 91 Example of connecting an external clock to the microcontroller ........................................... 91 CPU operating modes and current consumption .................................................................. 94 Block diagram of the low power consumption control circuit ................................................ 96 Configuration of the low power consumption mode control register (LPMCR) ..................... 98 Clock pulses during CPU intermittent operation ................................................................. 102 Release of sleep mode for an interrupt .............................................................................. 105 Release of PLL sleep mode (by external reset) ................................................................. 106 Release of timebase timer mode (by an external reset) ..................................................... 109 Release of stop mode (by external reset) ........................................................................... 111 Status change diagram ....................................................................................................... 112 Overall flow of interrupt operation ....................................................................................... 121 Interrupt control registers (ICR00 to ICR15) during writing ................................................ 126 Interrupt control registers (ICR00 to ICR15) during reading ............................................... 127 Configuration of interrupt control registers (ICR) ................................................................ 128 Hardware interrupt request while writing to the peripheral function control register area ............................................................................................................ 134 Hardware interrupt operation .............................................................................................. 137 Flow of interrupt processing ............................................................................................... 138 Procedure for using hardware interrupts ............................................................................ 139 Example of multiple interrupts ............................................................................................ 141 Interrupt processing time .................................................................................................... 142 Software interrupt operation ............................................................................................... 145 MB90560 series Figure 6.6-1 Figure 6.6-2 Figure 6.6-3 Figure 6.6-4 Figure 6.6-5 Figure 6.6-6 Figure 6.7-1 Figure 6.7-1 Figure 6.9-1 Figure 6.9-2 Figure 7.1-1 Figure 7.3-1 Figure 7.3-2 Figure 8.3-1 Figure 8.4-1 Figure 8.5-1 Figure 8.6-1 Figure 8.7-1 Figure 8.8-1 Figure 8.9-1 Figure 8.10-1 Figure 9.2-1 Figure 9.3-1 Figure 9.5-1 Figure 9.6-1 Figure 9.6-2 Figure 10.2-1 Figure 10.3-1 Figure 10.4-1 Figure 10.4-2 Figure 11.2-1 Figure 11.3-1 Figure 11.4-1 Figure 11.4-2 Figure 11.4-3 Figure 11.4-4 Figure 11.4-5 Figure 11.6-1 MB90560 series Extended intelligent I/O service (EI2OS) operation .............................................................147 Configuration of EI2OS descriptor (ISD) .............................................................................148 Configuration of DCT ...........................................................................................................150 Configuration of I/O register address pointer (IOA) .............................................................150 Configuration of EI2OS status register (ISCS) ....................................................................151 Configuration of buffer address pointer (BAP) ....................................................................152 Flow of extended intelligent I/O service (EI2OS) operation .................................................154 Procedure for using the extended intelligent I/O service (EI2OS) .......................................155 Stack operations at the start of interrupt processing ...........................................................160 Stack area ...........................................................................................................................161 Mode classification ..............................................................................................................168 Mode data configuration ......................................................................................................170 Correspondence between access areas and physical addresses in single-chip mode ......171 Block diagram of port 0 pins ................................................................................................177 Block diagram of port 1 pins ................................................................................................183 Block diagram of port 2 pins ................................................................................................189 Block diagram of port 3 pins ................................................................................................195 Block diagram of port 4 pins ................................................................................................201 Block diagram of port 5 pins ................................................................................................207 Block diagram of port 6 pins ................................................................................................213 Example of eight-segment LED connection ........................................................................218 Block diagram of the timebase timer ...................................................................................224 Timebase timer control register (TBTC) ..............................................................................226 Setting of the timebase timer ...............................................................................................230 Effect on PPG when clearing timebase timer ......................................................................232 Timebase timer operations ..................................................................................................233 Block diagram of the watchdog timer ..................................................................................239 Watchdog timer control register (WDTC) ............................................................................240 Setting of the watchdog timer ..............................................................................................242 Clear timing and watchdog timer intervals ..........................................................................243 Block diagram of the 16-bit reload timer ..............................................................................252 Block diagram of the 16-bit reload timer pins ......................................................................254 16-bit reload timer registers .................................................................................................255 Timer control status register, upper part (TMCSR0, TMCSR1: H) .....................................256 Timer control status register, low part (TMCSR0, TMCSR1: L) .........................................258 16-bit timer register (TMR0, TMR1) ....................................................................................260 16-bit reload register (TMRLR0, TMRLR1) .........................................................................261 Internal clock mode setting ..................................................................................................264 xi Figure 11.6-2 Figure 11.6-3 Figure 11.6-4 Figure 11.6-5 Figure 11.6-6 Figure 11.6-7 Figure 11.6-8 Figure 11.6-9 Figure 11.6-10 Figure 11.6-11 Figure 12.2-1 Figure 12.2-2 Figure 12.2-3 Figure 12.3-1 Figure 12.3-2 Figure 12.3-3 Figure 12.3-4 Figure 12.3-5 Event counter mode setting ................................................................................................ 264 Counter status transition ..................................................................................................... 265 Count operation in reload mode (software trigger operation) ............................................. 266 Counting in reload mode (external trigger operation) ......................................................... 267 Count operation in reload mode (software trigger and gate input operation) ..................... 267 Count operation in single-shot mode (software trigger operation) ...................................... 268 Count operation in single-shot mode (external trigger operation) ...................................... 269 Count operation in single-shot mode (software trigger and gate input operation) .............. 269 Count operation in reload mode (event count mode) ......................................................... 270 Counter operation in single-shot mode (event count mode) ............................................... 271 BLock Diagram of Realtime I/O .......................................................................................... 280 Block Diagram of 8/16-bit PPG Timer ................................................................................ 281 Block Diagram of Waveform Generator .............................................................................. 282 Registers of 16-bit Free-Run Timer .................................................................................... 284 Registers of Output Compare ............................................................................................. 285 Registers of 16-bit Input Capture ........................................................................................ 286 Registers of 8/16-bit PPG Timers ....................................................................................... 287 Registers of Waveform Generator ...................................................................................... 288 Figure 12.3.1-1 Registers of 16-bit Free-Run Timer .................................................................................... 290 Figure 12.3.1.1-1Compare Clear Register (CPCR) ....................................................................................... 291 Figure 12.3.1.2-1Timer Data Register ........................................................................................................... 292 Figure 12.3.1.3-1Timer Control Status Register (Upper) ............................................................................... 294 Figure 12.3.1.3-2Timer Control Status Register (Lower) ............................................................................... 296 Figure 12.3.2-1 Registers of Output Compare ............................................................................................. 298 Figure 12.3.2.1-1Compare Registers (OCCP0~5) ......................................................................................... 299 Figure 12.3.2.2-1Compare Control Register (Upper, OSC1/3/5) ................................................................... 300 Figure 12.3.2.2-2Compare Control Register (Lower, OSC0/2/4) ................................................................... 302 Figure 12.3.3-1 Registers of 16-bit Input Capture ........................................................................................ 304 Figure 12.3.3.1-1Input Capture Registers (IPCP0~3) .................................................................................... 305 Figure 12.3.3.2-1Capture Control Register (ICS23) ...................................................................................... 306 Figure 12.3.3.2-2Capture Control Register (ICS01) ...................................................................................... 308 Figure 12.3.4-1 Registers of 8/16-bit PPG Timers ....................................................................................... 310 Figure 12.3.4.1-1PPG Reload Register (PRLH0~5, PRLL0~5) ..................................................................... 311 Figure 12.3.4.2-1PPG1/3/5 Control Register (PPGC1/3/5) ........................................................................... 312 Figure 12.3.4.2-2PPG0/2/4 Control Register (PPGC0/2/4) ........................................................................... 314 Figure 12.3.4.3-1PPG0/1/2/3/4/5 Clock Control Register (PCD01/23/45) ..................................................... 316 Figure 12.3.5-1 Registers of Waveform Generator ...................................................................................... 318 Figure 12.3.5.1-18-bit Reload Registers (TMRR0/1/2) .................................................................................. 319 xii MB90560 series Figure 12.3.5.2-18-bit Timer Control Register (DTCR0/1/2) ...........................................................................320 Figure 12.3.5.3-1Waveform Control Register (SIGCR) ..................................................................................322 Figure 12.4.1-1 Clearing the counter by an overflow ....................................................................................326 Figure 12.4.1-2 Clearing the counter upon a match with compare clear register .........................................326 Figure 12.4.1-3 16-bit Free-run timer count timing .......................................................................................327 Figure 12.4.1-4 16-bit Free-run timer clear timing ........................................................................................327 Figure 12.4.2-1 Sample output waveform when compare registers 0 and 1 are used individually when the initial output value is "0". ...............................................................................................................328 Figure 12.4.2-2 Sample output waveform when compare registers 0 and 1 are used in a pair when the initial output value is "0". ...............................................................................................................329 Figure 12.4.2-3 Compare operation upon update of compare registers .......................................................330 Figure 12.4.2-4 Compare interrupt timing .....................................................................................................330 Figure 12.4.2-5 Output pin change timing ....................................................................................................330 Figure 12.4.3-1 Sample input capture timing ................................................................................................332 Figure 12.4.3-2 16-bit input capture timing for input signals .........................................................................333 Figure 12.4.4-1 PPG output operation, output waveform .............................................................................335 Figure 12.4.4-2 8+8 PPG output operation waveform ..................................................................................337 Figure 12.4.4-3 Write timing chart ................................................................................................................338 Figure 12.4.4-4 PRL write operation block diagram .....................................................................................338 Figure 12.4.5-1 Waveform Generator ...........................................................................................................340 Figure 12.4.5.1-1Positive Polarity Non-overlap Signal Generation by RT1/3/5 ..............................................342 Figure 12.4.5.1-2Negative Polarity Non-overlap Signal Generation by RT1/3/5 ............................................343 Figure 12.4.5.1-3Positive Polarity Non-overlap Signal Generation by PPG timer ..........................................344 Figure 12.4.5.1-4Negative Polarity Non-overlap Signal Generation by PPG timer ........................................345 Figure 12.4.5.2-1Generating PPG output/GATE signal during each RT is at "H" level ..................................346 Figure 12.4.5.2-2Generating PPG output/GATE signal until the value 8-bit timer and 8-bit reload register is matched. ..........................................................................................................................347 Figure 12.4.5.3-1Operation when DTTI input is enabled ................................................................................348 Figure 13.1-1 Figure 13.2-1 Figure 13.3-1 Figure 13.4-1 Figure 13.4-2 Figure 13.4-3 Figure 13.4-4 Figure 13.4-5 Figure 13.4-6 Figure 13.5-1 Figure 13.5-2 MB90560 series UART operation mode .........................................................................................................353 Block diagram of UART .......................................................................................................354 Block Diagram of UART Pins ..............................................................................................359 UART registers ....................................................................................................................360 Serial Control register (SCR0/1) ..........................................................................................362 Serial Mode control register (SMR0/1) ................................................................................364 Status register (SSR0/1) .....................................................................................................366 Serial input data register (SIDR0/1) ....................................................................................368 Output data register (SODR0/1) ..........................................................................................368 Reception operation and flag set timing ..............................................................................374 Transmission operation and flag set timing .........................................................................375 xiii Figure 13.6-1 Figure 13.6-2 Figure 13.6-3 Figure 13.7-1 Figure 13.7-2 Figure 13.7-3 Figure 13.7-4 Figure 13.7-5 Figure 13.7-6 Figure 13.7-7 Figure 13.7-8 Figure 13.7-9 Figure 14.2-1 Figure 14.3-1 Figure 14.3.2 Figure 14.4-2 Figure 14.4-2 Figure 14.4-3 Figure 14.4-4 Figure 14.5-1 Figure 14.5-2 Figure 14.5-3 Figure 14.6-1 Figure 14.6-2 Figure 15.1-1 Figure 15.2-1 Figure 16.2-1 Figure 16.3-1 Figure 16.4-1 Figure 16.4-2 Figure 16.4-3 Figure 16.4-4 Figure 16.6-1 Figure 16.6-2 Figure 16.6-3 Figure 16.6-4 Figure 16.6-5 xiv baud rate selection circuit ................................................................................................... 377 Baud rate selection circuit for the internal timer (16-bit reload timer 0) .............................. 382 Baud rate selection circuit for the external clock ................................................................ 384 Transfer data format (operation modes 0 and 1) ................................................................ 388 Transmission data when parity is enabled ......................................................................... 389 Transfer data format (operation mode 2) ............................................................................ 390 Settings for UART1 operation mode 0 ................................................................................ 392 Connection example of UART1 bidirectional communication ............................................. 392 Example of bidirectional communication flowchart ............................................................. 393 Settings for UART operation mode 1 .................................................................................. 394 Connection example of UART master-slave communication ............................................. 394 Master-slave communication flowchart .............................................................................. 395 Block diagram of the DTP/external interrupt circuit ............................................................ 404 Block diagram of the DTP/external interrupt circuit pins (For P10/INT0 ~ P16/INT6 only) . 407 Block diagram of the DTP/external interrupt circuit pins (For P63/ INT7 only) ................... 407 DTP/external interrupt circuit registers ............................................................................... 408 DTP/interrupt cause register (EIRR) ................................................................................... 409 DTP/interrupt enable register (ENIR) ................................................................................. 410 Request level setting register (ELVR) ................................................................................ 412 DTP/external interrupt circuit .............................................................................................. 414 Operation of the DTP/external interrupt circuit ................................................................... 416 Example of interfacing to the external peripheral ............................................................... 418 Clearing the cause retention circuit when a level is specified ............................................ 420 DTP/external interrupt cause and interrupt request when the output of interrupt requests is enabled .......................................................................................... 420 Block diagram of the delayed interrupt generator module .................................................. 428 Operation of the delayed interrupt generator module ......................................................... 429 Block diagram of the 8/10-bit A/D converter ....................................................................... 434 Block diagram of the P50/AN0 to P57/AN7 pins ................................................................ 437 8/10-bit A/D converter registers .......................................................................................... 438 A/D control status register 1 (ADCS1) ................................................................................ 439 A/D control status register 0 (ADCS0) ................................................................................ 442 A/D data register (ADCR0, 1) ............................................................................................. 444 Settings for single conversion mode ................................................................................... 447 Settings for continuous conversion mode ........................................................................... 448 Settings for stop conversion mode ..................................................................................... 449 Sample operation flowchart when EIOS is used ............................................................... 450 Operation flowchart of the data protection function when EIOS is used ........................... 453 MB90560 series Figure 16.8-1 Figure 16.9-1 Figure 16.10-1 Figure 17.1-1 Figure 17.2-1 Figure 17.2-2 Figure 17.2-3 Figure 18.1-1 Figure 18.1-2 Figure B.3-1 Figure B.3-2 Figure B.3-3 Figure B.3-4 Figure B.3-5 Figure B.3-6 Figure B.3-7 Figure B.3-8 Figure B.3-9 Figure B.3-10 Figure B.3-11 Figure B.4-1 Figure B.4-3 Figure B.4-4 Figure B.4-5 Figure B.4-6 Figure B.4-7 Figure B.4-8 Figure B.4-9 Figure B.4-10 Figure B.4-11 Figure B.4-12 Figure B.4-13 Figure B.9-1 Figure B.9-2 Figure C-1 Figure D-1 MB90560 series Flowchart of program using EIOS (single conversion mode) .............................................456 Flowchart of program using EIOS (continuous conversion mode) .....................................458 Flowchart of program using EIOS (stop conversion mode) ...............................................461 Block diagram ......................................................................................................................466 System configuration example ............................................................................................469 System configuration example ............................................................................................470 Flowchart of program patch processing ..............................................................................471 Block diagram ......................................................................................................................474 Memory space .....................................................................................................................475 Example of immediate addressing (#imm) ..........................................................................490 Example of register direct addressing .................................................................................491 Example of direct branch addressing (addr16) ...................................................................491 Example of physical direct branch addressing (addr24) .....................................................492 Example of I/O direct addressing (io) ..................................................................................492 Example of condensed direct addressing (dir) ....................................................................492 Example of direct addressing (addr16) ...............................................................................493 Example of I/O direct bit addressing (io:bp) ........................................................................493 Example of condensed direct bit addressing (dir:bp) ..........................................................494 Example of direct bit addressing (addr16:bp) ......................................................................494 Example of vector addressing (#vct) ...................................................................................494 Example of register indirect addressing (@RWj j = 0 to 3) ................................................496 Example of register indirect addressing with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3) ....................................................................................................497 Example of long-word register indirect addressing with displacement (@RLi+disp8 i = 0 to 3) ......................................................................................................497 Example of program counter indirect addressing with displacement (@PC+disp16) .........498 Example of register indirect addressing with base index (@RW0+RW7, @RW1+RW7) ....499 Example of program counter relative branch addressing (rel) ............................................499 Register list configuration ....................................................................................................500 Example of register list (rlst) ................................................................................................500 Example of accumulator indirect addressing (@A) .............................................................500 Example of accumulator indirect branch addressing (@A) .................................................501 Example of indirect designation branch addressing (@ear) ................................................501 Example of indirect designation branch addressing (@eam) ..............................................502 Configuration of instruction maps ........................................................................................523 Relationship between actual instruction codes and instruction maps .................................524 Sector configuration of 512K-bit flash memory ...................................................................545 Standard configuration for Fujitsu standard serial on-board writing ....................................551 xv Figure D.2 Connection example for MB90F562 serial writing .............................................................. 553 xvi MB90560 series TABLES Table 1.2-1 Table 1.6-1 Table 1.6-2 Table 1.6-3 Table 1.7-1 Table 1.7-2 Table 2.4-1 Table 2.4-2 Table 2.7-1 Table 2.7-2 Table 2.7-3 Table 2.8-1 Table 2.9-1 Table 2.9-2 Table 2.9-3 Table 2.9-4 Table 2.9-5 Table 2.9-6 Table 3.1-1 Table 3.2-1 Table 3.2-2 Table 3.5-1 Table 4.3-1 Table 5.3-1 Table 5.3-2 Table 5.5-1 Table 5.6-1 Table 5.6-2 Table 5.6-3 Table 5.7-1 Table 6.2-1 Table 6.2-2 Table 6.3-1 Table 6.3-2 MB90560 series Product lineup of the MB90560 series ....................................................................................4 Pin functions ..........................................................................................................................14 Pin functions (Continued) ......................................................................................................15 Pin functions (Continued) ......................................................................................................16 I/O circuit types ......................................................................................................................18 I/O circuit types (Continued) ..................................................................................................19 Access space and main function of each bank register ........................................................32 Addressing and default spaces .............................................................................................33 Initial values of the dedicated registers .................................................................................39 Stack address specification ...................................................................................................44 Interrupt level mask register (ILM) and interrupt level priority ...............................................51 Typical functions of general-purpose registers ......................................................................57 Bank select prefix codes and selected memory spaces ........................................................60 Instructions not affected by bank select prefix codes ............................................................60 Instructions which use requires caution when bank select prefix codes are used ................61 Instructions whose use requires caution when the common register bank prefix (CMR) is used ...................................................................................................................................62 Instructions requiring caution when the flag change suppression prefix (NCC) is used .......63 Prefix codes and interrupt/hold suppression instructions .....................................................64 Reset causes .........................................................................................................................68 Reset causes and oscillation stabilization wait intervals .......................................................70 Oscillation stabilization wait intervals set by the clock selection register (CKSCR) .............70 Correspondence between reset cause bits and reset causes ...............................................77 Function description of each bit of the clock selection register (CKSCR) .............................87 Function description of each bit of the low power consumption mode control register (LPMCR) ...............................................................................................................................99 Instructions to be used for switching to low power consumption mode ...............................100 Operation statuses during standby mode ............................................................................103 Low power consumption mode operating states .................................................................113 Clock mode switching and release ......................................................................................113 Switching to and release of standby mode ..........................................................................114 State of pins in single-chip mode ........................................................................................115 Interrupt vectors ..................................................................................................................122 Interrupt causes, interrupt vectors, and interrupt control registers ......................................123 Interrupt control registers ....................................................................................................124 Correspondence between the interrupt level setting bits and interrupt levels .....................129 xvii Table 6.3-3 Table 6.3-4 Table 6.4-1 Table 6.4-2 Table 6.4-3 Table 6.6-1 Table 6.7-1 Table 6.7-2 Table 6.7-3 Table 7.2-1 Table 7.3-1 Table 7.3-2 Table 8.1-1 Table 8.2-1 Table 8.3-1 Table 8.3-2 Table 8.3-3 Table 8.3-4 Table 8.4-1 Table 8.4-2 Table 8.4-3 Table 8.4-4 Table 8.5-1 Table 8.5-2 Table 8.5-3 Table 8.5-4 Table 8.6-1 Table 8.6-2 Table 8.6-3 Table 8.6-4 Table 8.7-1 Table 8.7-2 Table 8.7-3 Table 8.7-4 Table 8.8-1 Table 8.8-2 Table 8.8-3 xviii Correspondence between the EI2OS channel selection bits and descriptor addresses .......................................................................................................... 129 Relationship between EI2OS status bits and the EI2OS status ......................................... 130 Mechanisms used for hardware interrupts ........................................................................ 133 Hardware interrupt suppression instruction ........................................................................ 134 Compensation values (Z) for the interrupt handling time .................................................... 143 Correspondence between channel numbers and descriptor addresses ............................ 148 Extended intelligent I/O service execution time ................................................................. 156 Data transfer compensation value for EI2OS execution time ............................................. 156 Interpolation value (Z) for the interrupt handling time ......................................................... 157 Mode pin settings ............................................................................................................... 169 Bus mode setting bits and functions ................................................................................... 170 Relationship between mode pins and mode data ............................................................... 171 Functions of individual ports ............................................................................................... 174 Registers and corresponding ports ..................................................................................... 175 Port 0 pins .......................................................................................................................... 176 Port 0 pins and their corresponding register bits ................................................................ 177 Port 0 register functions ...................................................................................................... 178 States of port 0 pins ............................................................................................................ 181 Port 1 pins .......................................................................................................................... 182 Port 1 pins and their corresponding register bits ................................................................ 183 Port 1 register functions ...................................................................................................... 184 States of port 1 pins ............................................................................................................ 187 Port 2 pins .......................................................................................................................... 188 Port 2 pins and their corresponding register bits ................................................................ 189 Port 2 register functions ...................................................................................................... 190 States of port 2 pins ............................................................................................................ 193 Port 3 pins .......................................................................................................................... 194 Port 3 pins and their corresponding register bits ................................................................ 195 Port 3 register functions ...................................................................................................... 196 States of port 3 pins ............................................................................................................ 199 Port 4 pins .......................................................................................................................... 200 Port 4 pins and their corresponding register bits ................................................................ 201 Port 4 register functions ...................................................................................................... 202 States of port 4 pins ............................................................................................................ 205 Port 5 pins .......................................................................................................................... 206 Port 5 pins and their corresponding register bits ................................................................ 207 Port 5 register functions ...................................................................................................... 208 MB90560 series Table 8.8-4 Table 8.9-1 Table 8.9-2 Table 8.9-3 Table 8.9-4 Table 9.1-1 Table 9.1-2 Table 9.3-1 Table 9.4-1 Table 9.5-1 Table 10.1-1 Table 10.3-1 Table 11.1-1 Table 11.1-2 Table 11.1-3 Table 11.3-1 Table 11.4-1 Table 11.4-2 Table 11.5-1 Table 11.5-2 States of port 5 pins ............................................................................................................211 Port 6 pins ...........................................................................................................................212 Port 6 pins and their corresponding register bits .................................................................213 Port 6 register functions ......................................................................................................214 States of port 6 pins ............................................................................................................217 Intervals for the timebase timer ...........................................................................................222 Clock cycle time supplied from the timebase timer .............................................................223 Function description of each bit in the timebase timer control register (TBTC) ...................227 Timebase interrupts and EI2OS ..........................................................................................228 Timebase timer counter clearing and oscillation stabilization wait intervals ........................231 Intervals for the watchdog timer .........................................................................................238 Function description of each bit of the watchdog timer control register (WDTC) ................241 16-bit reload timer operating modes ....................................................................................248 Intervals for the 16-bit reload timer ......................................................................................249 16-bit reload timer interrupts and EI2OS .............................................................................250 16-bit reload timer pins ........................................................................................................254 Function description of each bit of the upper part of the timer control status register (TMCSR0, TMCSR1: H) .......................................................................................................................257 Function description of each bit of the low part of the timer control status register (TMCSR0, TMCSR1: L) ........................................................................................259 Interrupt control bits and interrupt causes of the 16-bit reload timer ...................................262 16-bit reload timer interrupts and EI2OS .............................................................................262 Table 12.3.1.3-1 Timer Control Status Register (Upper) Bit ...........................................................................295 Table 12.3.1.3-2 Timer Control Status Register (Lower) ................................................................................297 Table 12.3.2.2-1 Compare Control Register (Upper, OSC1/3/5) Bit ..............................................................301 Table 12.3.2.2-2 Compare Control Register (Lower, OSC0/2/4) ....................................................................303 Table 12.3.3.2-1 Capture Control Register (ICS23) Bit ..................................................................................307 Table 12.3.3.2-2 Capture Control Register (ICS01) .......................................................................................309 Table 12.3.4.1-1 Function of PPG Reload registers .......................................................................................311 Table 12.3.4.2-1 PPG1/3/5 Control Register (PPGC1/3/5) Bit .......................................................................313 Table 12.3.4.2-2 PPG0/2/4 Control Register (PPG0/2/4) ...............................................................................315 Table 12.3.4.3-1 PPG0/1/2/3/4/5 Clock Control Register (PPG0/2/4) ............................................................317 Table 12.3.5.2-1 8-bit Timer Control Registers (DTCR0/1/2) Bit ....................................................................321 Table 12.3.5.3-1 Waveform Control Register (SIGCR) ..................................................................................323 Table 12.4.4-1 Table 13.1-1 Table 13.1-2 Table 13.3-1 Table 13.4-1 MB90560 series Reload operation and pulse output .....................................................................................334 UART functions ...................................................................................................................352 UART interrupt and EIOS ..................................................................................................353 UART pins ...........................................................................................................................358 Functions of each bit of serial control register (SCR0/1) .....................................................363 xix Table 13.4-2 Table 13.4-3 Table 13.4-4 Table 13.5-1 Table 13.5.2 Table 13.6-1 Table 13.6-2 Table 13.6-3 Table 13.6-4 Table 13.7-1 Table 13.7-2 Table 14.1-1 Table 14.1-2 Table 14.3-1 Table 14.4-1 Table 14.4-2 Table 14.4-3 Table 14.4-4 Table 14.4-5 Table 14.5-1 Table 16.1-1 Table 16.1-2 Table 16.3-1 Table 16.4-1 Table 16.4-2 Table 16.4-3 Table 16.5-1 Table 16.5-2 Table A Table A Table A Table A Table A Table A Table B.2-1 Table B.3-1 Table B.5-1 xx Functions of each bit of serial mode control register (SMR0/1) .......................................... 365 Functions of each bit of serial status register (SSR0/1) ..................................................... 367 Communication prescaler ................................................................................................... 370 Interrupt control bits and interrupt causes of UART ........................................................... 372 UART interrupts and EIOS ................................................................................................ 373 Selection of each division ratio for the machine clock prescaler ........................................ 378 Selection of synchronous baud rate division ratios ............................................................ 379 Selection of synchronous baud rate division ratios ............................................................ 379 Baud rates and reload values ............................................................................................. 383 UART operation mode ........................................................................................................ 386 Selection of the master-slave communication function ...................................................... 395 Overview of the DTP/external interrupt circuit .................................................................... 402 Interrupt of the DTP/external interrupt circuit and EI2OS .................................................. 403 DTP/external interrupt circuit pins ...................................................................................... 406 Function description of each bit of the DTP/interrupt cause register (EIRR) ..................... 409 Function description of each bit of the DTP/interrupt enable register (ENIR) .................... 410 Correspondence between the DTP/interrupt control registers (EIRR and ENIR) and each channel .................................................................................. 411 Function description of each bit of the request level setting register (ELVR) .................... 412 Correspondence between request level setting register (ELVR) and each channel ......... 413 Control bit and interrupt cause of the DTP/external interrupt circuit .................................. 415 8/10-bit A/D converter conversion modes .......................................................................... 432 8/10-bit A/D converter interrupts and EIOS ....................................................................... 433 8/10-bit A/D converter pins ................................................................................................. 436 Function description of each bit of A/D control status register 1 (ADCS1) ......................... 440 Function description of each bit of A/D control status register 0 (ADCS0) ......................... 443 Function description of each bit of A/D control status register 0 (ADCS0) ......................... 445 Interrupt control bits of the 8/10-bit A/D converter and the interrupt cause ........................ 446 8/10-bit A/D converter interrupts and EIOS ....................................................................... 446 I/O map .............................................................................................................................. 479 I/O map (continued) ............................................................................................................ 480 I/O map (continued) ............................................................................................................ 481 I/O map (continued) ............................................................................................................ 482 I/O map (continued) ........................................................................................................... 483 I/O map (continued) ............................................................................................................ 484 Effective-address field ........................................................................................................ 489 CALLV vectors .................................................................................................................... 495 Number of execution cycles for each type of addressing .................................................. 503 MB90560 series Table B.5-1 Table B.5-2 Table B.5-3 Table B.6-1 Table B.7-1 Table B.7-1 Table B.7-1 Table B.8-1 Table B.8-2 Table B.8-3 Table B.8-4 Table B.8-5 Table B.8-6 Table B.8-7 Table A.2-1 Table B.8-9 Table B.8-10 Table B.8-11 Table B.8-12 Table B.8-13 Table B.8-14 Table B.8-15 Table B.8-16 Table B.8-17 Table B.9-1 Table B.9-2 Table B.9-3 Table B.9-4 Table B.9-5 Table B.9-6 Table B.9-7 Table B.9-8 Table B.9-9 Table B.9-10 Table B.9-11 Table B.9-12 Table B.9-13 Table B.9-14 MB90560 series Number of execution cycles for each type of addressing (continued) ................................504 Compensation values for calculating the number of execution cycles ................................504 Compensation values for calculating number of cycles for program fetch ..........................505 Effective-address field .........................................................................................................506 Items covered in instruction list ..........................................................................................507 Symbols used in the instruction list (continued) ..................................................................508 Symbols used in the instruction list (continued) ..................................................................509 Transfer instructions (byte): 41 instructions .......................................................................510 Transfer instructions (word, long-word): 38 instructions .....................................................511 Addition/subtraction (byte, word, long-word): 42 instructions .............................................512 Increment/decrement (byte, word, long-word): 12 instructions ..........................................513 Comparison (byte, word, long-word): 11 instructions .........................................................513 Unsigned multiplication/division (word, long-word): 11 instructions ...................................514 Logical 1 (byte, word): 39 instructions ................................................................................515 Logical 2 (long-word): 6 instructions ...................................................................................516 Sign inversion (byte, word): 6 instructions ..........................................................................516 Normalization (long-word): 1 instruction .............................................................................516 Shift instructions (byte, word, long-word): 18 instructions ..................................................517 Branching instructions (1): 31 instructions .........................................................................518 Branch instructions (2): 19 instructions ..............................................................................519 Other control instructions (byte, word, long-word): 28 instructions ....................................520 Bit operation instructions: 21 instructions ...........................................................................521 Accumulator operation instructions (byte, word): 6 instructions .........................................521 String instructions: 10 instructions ......................................................................................522 Example instruction codes ..................................................................................................524 Basic page map ...................................................................................................................525 Bit operation instruction map (1st byte = 6CH) ....................................................................526 Character string operation instruction map (1st byte = 6EH) ..............................................527 2-byte instruction map (1st byte = 6FH) ..............................................................................528 ea instruction map (1) (1st byte = 70H) ...............................................................................529 ea instruction map (2) (1st byte = 71H) ...............................................................................530 ea instruction map (3) (1st byte = 72H) ...............................................................................531 ea instruction map (4) (1st byte = 73H) ...............................................................................532 ea instruction map (5) (1st byte = 74H) ...............................................................................533 ea instruction map (6) (1st byte = 75H) ...............................................................................534 ea instruction map (7) (1st byte = 76H) ...............................................................................535 ea instruction map (8) (1st byte = 77H) ...............................................................................536 ea instruction map (9) (1st byte = 78H) ...............................................................................537 xxi Table B.9-15 Table B.9-16 Table B.9-17 Table B.9-18 Table B.9-19 Table B.9-20 Table B.9-21 Table C-1 Table C-2 MOVEA RWi,ea instruction map (1st byte = 79H) .............................................................. 538 MOV Ri,ea instruction map (1st byte = 7AH) ...................................................................... 539 MOVW RWi,ea instruction map (1st byte = 7BH) .............................................................. 540 MOV ea,Ri instruction map (1st byte = 7CH) ..................................................................... 541 MOVW ea,Rwi instruction map (1st byte = 7DH) ............................................................... 542 XCH Ri,ea instruction map (1st byte = 7EH) ...................................................................... 543 XCHW RWi,ea instruction map (1st byte = 7FH) ................................................................ 544 Correspondence between external control pins and flash memory control signals ............ 546 Pin settings for read/write access in flash memory mode .................................................. 548 xxii MB90560 series CHAPTER 1 OVERVIEW This chapter describes the features of the MB90560 series. 1.1 Features ............................................................................................. 2 1.2 Product Lineup ................................................................................... 4 1.3 Block Diagram .................................................................................... 5 1.4 Pin Assignments................................................................................. 6 1.5 Package Dimensions........................................................................ 10 1.6 Pin Functions.................................................................................... 14 1.7 I/O Circuit Types............................................................................... 18 1.8 Notes on Handling Devices .............................................................. 20 1.1 Features The MB90560 series of general-purpose 16-bit microcontrollers was developed for applications that require high-speed real-time processing in a variety of industrial systems, OA equipment, and process control systems. A specific feature of the series is a built-in multifunctional timer that can easily output desired waveforms. The instruction set inherits the AT architecture of the original Fujitsu FMC-8L and FMC-16L, and has additional instructions supporting high-level languages. In addition, it has an extended addressing mode, enhanced multiply/divide instructions (signed), and reinforced bit manipulation instructions. The chip also has a 32-bit accumulator that enables long-word data to be processed. s Features of the MB90560 Series q Clock * * * Built-in PLL clock multiplying circuit Selectable operating clock (PLL clock): The source oscillation can be divided by two or multiplied by 1 to 4 (4 to 16 MHz when the source oscillation is 4 MHz). Minimum instruction execution time: 62.5 ns (when the source oscillation is 4 MHz, PLL clock is multiplied by 4, and Vcc is 5 V) q Maximum memory address space: 16M bytes Internal 24-bit addressing q Optimum instruction set for controller applications * * * * * Many data types (bit, byte, word, and long word) As many as 23 addressing modes High code efficiency Enhanced high-precision arithmetic operation by a 32-bit accumulator Enhanced signed multiply/divide instructions and RETI instruction function q Instruction set supporting high-level language (C) and multitasking * * System stack pointer Instruction set symmetry and barrel shift instructions q Sleep mode (The operating clock of the CPU stops.) q Program patch function (Two-address pointer) q Increased execution speed 4-byte instruction queue q Enhanced interrupt function (Eight programmable priority levels) Powerful interrupt function of 32 factors q Data transfer function (Extended intelligent I/O service function using up to 16 channels) q Lower-power consumption (standby mode) 2 CHAPTER 1 OVERVIEW MB90560 series * * * * Sleep mode (in which the CPU operating clock stops) Time-base timer mode (in which only the source oscillation and time-base timer are active) Stop mode (in which the source oscillation stops) CPU intermittent operation mode q Packages * * QFP-64 (FPT-64P-M09: 0.65 mm pin pitch, FPT-64P-M06: 1.00 mm pin pitch) SH-DIP (DIP-64-M01: 1.778 pin pitch) q Process : CMOS technology s Internal peripheral functions (resources) q I/O ports: Up to 50 posts q 18-bit time-base timer: 1 channel q Watchdog timer: 1 channel q 16-bit reload timer: 2 channels q Advanced timer: 1 channel * * 16-bit free running timer: 1 channel 16-bit output compare: 6 channels When the count of the 16-bit free running timer matches the count set for comparison, the output compare unit inverts the output and generates an interrupt request. * 16-bit input capture: 4 channels When the edge of the pin input is detected, the input capture unit latches the count of the 16-bit free running timer and generates an interrupt request. * 8-/16-bit PPG timer: 8 bits x 6 channels or 16 bits x 3 channels Capable of changing the period or duty cycle of the output pulses as desired. * Waveform generation circuit (8-bit timer: 3 channels) Capable of generating optimum waveforms for inverter control. q UART: 2 channels * * With full duplex double buffer (8-bit length) Capable of asynchronous or synchronous transfer (I/O extended serial) q DTP/external interrupt (8 channels) Module for activating the extended intelligent I/O service by external input and for generating an external interrupt q Delayed interrupt generator module Generates an interrupt request for task switching. q 8/10-bit A/D converter (8 channels) * * MB90560 series Selectable resolution of 8 or 10 bits Capable of activation by external trigger CHAPTER 1 OVERVIEW 3 1.2 Product Lineup Table 1.2-1 shows the product lineup of the MB90560 series. The specifications excluding the ROM and RAM capacities are common for the series. s Product Lineup Table 1.2-1 Product lineup of the MB90560 series Device Type ROM size RAM size CPU function MB90V560 Evaluation device -- MB90F562 Flash Type ROM MB90561 MB90562 Mass-production product (mask ROM) 32K Byte 1K Byte 64K Byte 2K Byte 4K Byte Number of basic instructions : 351 Minimum instruction execution time : 62.5 ns/4 MHz (when PLL clock is multiplied by 4) Number of addressing modes : 23 Program patch function : 2-address pointer Maximum memory address space : 16M bytes I/O ports (CMS): 50 With a full duplex double buffer. Capable of synchronous or asynchronous clock transfer. Usable also for serial I/O. Dedicated built-in baud rate generator. Two channels built-in 16-bit reload timer operation (toggle output or one-shot selectable) Choice of the event count function. Two channels built-in. 16-bit free running timer x 1 channel, 16-bit output compare x 6 channels, 16-bit input capture x 4 channels 8-/16-bit PPG timer (8-bit mode x 6 channels, 16-bit mode x 3 channels) Waveform generation circuit: 8-bit timer x 3 channels Three-phase waveform output, dead time output 10-bit resolution x 8 channels (input multiplex) Conversion time:6.13 or less (operation at internal 16 MHz clock) Independent 8 channels Interrupt cause: L-to-H edge, H-to-L edge, L-level, or H-level selectable Sleep mode, stop mode, and CPU intermittent mode CMOS PGA256 5V10% @16MHz QFP-64 (0.65 or 1.00 mm pitch), SHDIP-64 Port UART 16-bit reload timer Advanced timer 10-bit A/D converter External interrupt Low-power consumption mode Process Package Operating voltage 4 CHAPTER 1 OVERVIEW MB90560 series 1.3 Block Diagram Figure 1.3-1 shows the block diagram of the MB90560 series. s Block Diagram X0 X1 Clock control circuit F2MC-16LX series core Multi-function timer CPU RSTX Reset Circuit (Watch-dog timer) 8/16-bit PPG (Ch0/1/2) Interrupt controller 6 6 P41/PPG0 to P46/PPG6 16-bit input capture (Ch0/1/2/3) 4 4 P24/IN0 to P27/IN3 Timebase timer 16-bit free-run timer P17/FRCK Delayed Interrupt generator 8 P00-07 CMOS I/O PORT 0 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS F2MC-16LX BUS 16-bit output compare (Ch0~5) P30/RTO0 (U) P31/RTO1 (X) P32/RTO2 (V) P33/RTO3 (Y) P34/RTO4 (W) P35/RTO5 (Z) P63/INT7/DTT CMOS I/O PORT 5 Waveform Generator 8 A/D converter (8/10 bits) UART (Ch 0) P36/SIN0 P37/SOUT0 P40/SCK0 P60/SIN1 P61/SOUT1 P62/SCK1 P20/TIN0 P21/TO0 UART (Ch 1) RAM ROM Address Match Detect ROM Mirroring DTP/External interrupt 8 7 16-bit timer (Ch 0) 16-bit timer (Ch 1) P22/TIN1 P23/TO1 Other pins Vss x2, Vcc x 1, MD0-2 and C P10/INT0 to P16/INT6 CMOS I/O PORT 1, 2, 3, 4 ,6 Note: P00 to P07 (8 channels): With registers that can be used as input pull-up resistors P10 to P17 (8 channels): With registers that can be used as input pull-up resistors Figure 1.3-2 Block diagram MB90560 series CHAPTER 1 OVERVIEW 5 1.4 Pin Assignments This section provides the pin assignments for the following three MB90560 series packages: * FPT-64P-M06 * FPT-64P-M09 * DIP-64P-M01 s Pin Assignment of FPT-64P-M06 Figure 1.4-1 shows the pin assignment of the FPT-64P-M06. P41/PPG0 P40/SCK0 P37/SOT0 P43/PPG2 P42/PPG1 P35/RTO5 P34/RTO4 P33/RTO3 P32/RTO2 64 63 62 61 60 59 58 57 56 55 54 53 52 P45/PPG3 1 P31/RTO1 P36/SIN0 C Vcc 51 50 49 48 47 46 45 44 P45/PPG4 2 P46/PPG5 3 P50/AN0 4 P51/AN1 5 P52/AN2 6 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 Avcc AVR Avss P60/SIN1 P61/SOT1 P62/SCK1 7 8 9 10 11 12 13 14 15 16 17 P30/RTO0 Vss P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/TO1 P22/TIN1 P21/TO0 P20/TIN0 P17/FRCK P16/INT6 P15/INT5 P14/INT4 P13/INT3 P12/INT2 P11/INT1 P10/INT0 P07 < TOP VIEW > 43 42 41 40 39 38 37 36 35 34 33 P63/INT7/DTTI 18 MD0 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 1.4-1 Pin assignment of FPT-64P-M09 MD2 MD1 RSTX P01 P00 Vss P02 P05 P04 P03 P06 X0 X1 6 CHAPTER 1 OVERVIEW MB90560 series s Pin Assignment of FPT-64P-M09 Figure 1.4-2 shows the pin assignment of the FPT-64P-M09. P41/PPG0 P40/SCK0 P37/SOT0 P44/PPG3 P43/PPG2 P42/PPG1 P35/RTO5 P34/RTO4 P33/RTO3 P32/RTO2 P31/RTO1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P45/PPG4 1 P46/PPG5 P50/AN0 P51/AN1 P52/AN2 2 3 4 5 P30/RTO0 Vss P36/SIN0 C Vcc 48 47 46 45 44 43 42 P53/AN3 6 P54/AN4 7 P55/AN5 8 P56/AN6 9 P57/AN7 10 Avcc 11 AVR 12 Avss 13 P60/SIN1 14 P61/SOT1 15 P62/SCK1 16 < TOP VIEW > 41 40 39 38 37 36 35 34 33 P27/IN3 P26/IN2 P25/IN1 P24/IN0 P23/TO1 P22/TIN P21/TO0 P20/TIN0 P17/FRCK P16/INT6 P15/INT5 P14/INT4 P13/INT3 P12/INT2 P11/INT1 P10/INT0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P04 P03 P07 P06 P05 P02 P01 P00 Vss X1 RSTX MD0 X0 Figure 1.4-2 Pin assignment of FPT-64P-M09 P63/IN7/DTTI MD2 MD1 MB90560 series CHAPTER 1 OVERVIEW 7 s Pin Assignment of DIP-64P-M01 Figure 1.4-3 shows the pin assignment of the DIP-64P-M01. C P3 6/SIN 0 P37/S O T 0 P40 /SC K 0 P41/PPG 0 P42 /PPG 1 P43 /PPG 2 P44 /PPG 3 P45 /PPG 4 P46 /PPG 5 P50/A N 0 P51/A N 1 P52/A N 2 P53/A N 3 P54/A N 4 P55/A N 5 P56/A N 6 P57/A N 7 A V cc AVR A V ss P60/SIN 1 P61/SO T1 P62/SC K1 P63/IN T7 /D TTI M D0 R STX M D1 M D2 X0 X1 V ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 V cc P35/R TO 5 P34/R TO 4 P33/R TO 3 P32/R TO 2 P31/R TO 1 P30/R TO 0 V ss P27/IN 3 P26/IN 2 P25/IN 1 P24/IN 0 P23/TO 1 P22/TIN 1 P21/TO 0 P20/TIN 0 P17/FR C K P16/IN T6 P15/IN T5 P14/IN T4 P13/IN T3 P12/IN T2 P11/IN T1 P10/IN T0 P07 P06 P05 P04 P03 P02 P01 P00 < TO P V IE W > 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Figure 1.4-3 Pin assignment of DIP-64P-M01 8 CHAPTER 1 OVERVIEW MB90560 series Memo MB90560 series CHAPTER 1 OVERVIEW 9 1.5 Package Dimensions This section provides the dimensions of the following three MB90560 series packages: * FPT-64P-M06 * FPT-64P-M09 * DIP-64P-M01 s FPT-64P-M06 Figure 1.5-1 shows the dimensions of the FPT-64P-M06 package. 24.700.40(.972.016) 51 20.000.20(.787.008) 33 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 52 32 14.000.20 (.551.008) INDEX 64 20 18.700.40 (.736.016) 12.00(.472) REF 16.300.40 (.642.016) "A" LEAD No. 1 19 1.00(.0394) TYP 0.400.10 (.016.004) 0.150.05(.006.002) 0.20(.008) M Details of "A" part 0.25(.010) "B" 0.10(.004) 18.00(.709)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX Details of "B" part 0 10 1.200.20 (.047.008) C 1994 FUJITSU LIMITED F64013S-3C-2 Figure 1.5-1 Dimensions of FPT-64P-M06 package 10 CHAPTER 1 OVERVIEW MB90560 series s FPT-64P-M09 Figure 1.5-1 shows the dimensions of the FPT-64P-M09 package. 14.000.20(.551.008)SQ 48 12.000.10(.472.004)SQ 33 1.50 -0.10 .059 -.004 +0.20 +.008 (Mounting height) 49 32 9.75 (.384) REF 1 PIN INDEX 13.00 (.512) NOM 64 17 LEAD No. 1 16 Details of "A" part "A" M 0.65(.0256)TYP 0.300.10 (.012.004) 0.13(.005) 0.127 -0.02 .005 -.001 +0.05 +.002 0.100.10 (STAND OFF) (.004.004) 0.10(.004) 0 10 0.500.20 (.020.008) C 1994 FUJITSU LIMITED F64018S-1C-2 Figure 1.5-2 Dimensions of FPT-64P-M09 package MB90560 series CHAPTER 1 OVERVIEW 11 s DIP-64P-M01 Figure 1.5-3 shows the dimensions of the DIP-64P-M01 package. 58.00 -0.55 2.283 -.022 +0.22 +.008 INDEX-1 17.000.25 (.669.010) INDEX-2 5.65(.222)MAX 3.00(.118)MIN 1.00 -0 .039 -0 +0.50 +.020 0.250.05 (.010.002) 0.450.10 (.018.004) 0.51(.020)MIN 15MAX 19.05(.750) TYP 1.7780.18 (.070.007) 1.778(.070) MAX 55.118(2.170)REF C 1994 FUJITSU LIMITED D64001S-3C-4 Figure 1.5-3 Dimensions of DIP-64P-M01 package 12 CHAPTER 1 OVERVIEW MB90560 series Memo MB90560 series CHAPTER 1 OVERVIEW 13 1.6 Pin Functions Tables 1.6-1 to 1.6-3 summarize the pin names, circuit types, states at reset time, and functions. s Pin Functions Table 1.6-1 Pin functions Pin No. Pin name QFPM09*1 QFPM06*2 SDIP*3 Circuit type Pin Status during reset Function 22,23 19 25~32 23,24 20 26~33 30,31 27 33~40 X0*X1 RSTX P00~P07 P10~P16 A B C Oscillating Reset input Oscillation input pins External reset input pin General-purpose I/O ports General-purpose I/O ports 33~39 39~40 41~47 INT0~6 C Can be used as interrupt request input channels 0 to 6. Input is enabled when 1 is set in EN0 to EN6 in standby mode. General-purpose I/O ports P17 40 41 48 FRCK P20 41 42 49 TIN0 P21 T00 P22 43 44 51 TIN1 P23 T01 P24~27 D D C External clock input pin for free running timer Port input General-purpose I/O ports External clock input pin for reload timer 0 General-purpose I/O ports Event output pin for reload timer 0 General-purpose I/O ports External clock input pin for reload timer 1 General-purpose I/O ports Event output pin for reload timer 1 General-purpose I/O ports Trigger input pins for input capture channels 0 to 3. When input capture channels 0 to 3 are used for input operation, these pins are enabled as required and must not be used for any other I/P 42 43 50 D 44 45 52 D 45~48 46~49 53~56 IN0~3 D *1: FPT-64P-M09 *2: FPT-64P-M06 *3: DIP-64P-M01 14 CHAPTER 1 OVERVIEW MB90560 series Table 1.6-2 Pin functions (Continued) Pin No. Pin name QFPM09* 50~55 1 QFPM06* 51~56 2 SDIP* 58~63 3 Circuit type D Pin Status during reset Port input Function P30~P35 RT00~5 General-purpose I/O ports Compare event output pints or waveform generator output pins. These pins output the waveforms specified at the waveform generator. They output compare events when waveforms are not generated. Output is generated when compare event output is enabled. 58 59 2 P36 SIN0 D Port input General-purpose I/O ports Serial data input pin for UART channel 0. While UART channel 0 is operating for input, the input of this pin is used as required and must not be used for any other input. 59 60 3 P37 S0T0 D General-purpose I/O ports Serial data output pin for UART channel 0. This function is enabled when UART channel 0 enables data output. 60 61 4 40 SCK0 D General-purpose I/O ports Serial clock I/O pin for UART channel 0. This function is enabled when UART channel 0 enables clock output. 61~64, 1,2 62~64, 1~3 5~10 P41~P46 PPG0~5 F General-purpose I/O ports Output pins for PPG channels 0 to 5. This function is enabled when PPG channels 0 to 5 enable output. 3~10 4~11 11~18 P50~P57 AN0~7 E Analog input General-purpose I/O ports A/D converter analog input pins. This function is enabled when the analog input specification is enabled. (ADER) 11 12 19 AVCC G Power input Vss power input pin for analog circuits *1: FPT-64P-M09 *2: FPT-64P-M06 *3: DIP-64P-M01 MB90560 series CHAPTER 1 OVERVIEW 15 Table 1.6-3 Pin functions (Continued) Pin No. Pin name QFPM09* 12 1 QFPM06* 13 2 SDIP* 20 3 Circuit type H Pin Status during reset Function AVR Vref+ input pin for the A/D converter. This voltage must not exceed Vcc. Vrefis fixed to AVSS. Power input Power input Vss power input pin for analog circuits General-purpose I/O ports Serial data input pin for UART channel 1. While UART channel 1 is operating for input, the input of this pin is used as required and must not be used for any other input. 13 14 14 15 21 22 AVSS P60 SIN1 G D 15 16 23 P61 S0T1 D General-purpose I/O ports Serial data output pin for UART channel 0. This function is enabled when UART channel 1 enables data output. 16 17 24 P62 SCK1 D Port input General-purpose I/O port Serial clock I/O pin for UART channel 1. This function is enabled when UART channel 1 enables clock output. 17 18 25 P63 DTT1 D General-purpose I/O port RTOn pins for fixed-level input. This function is enabled when the waveform generator enables input. Usable as interrupt request input channel 7. Input is enabled when 1 is set in EN7 in standby mode. INT7 57 58 1 C G Capacitance pin power input Capacitance pin for power stabilization. Connect a ceramic capacitor of about 0.1 F to the outside. Input pin for operation mode specification. Connect this pin directly to Vcc or Vss. Input pin for operation mode specification. Connect this pin directly to Vcc or Vss. Power (5 V) input pin Power (5 V) input pin 18 19 26 MD0 B 20,21 21,22 28,29 MD1,MD2 B 24,49 56 25,50 57 32,57 64 VSS VCC - - *1: FPT-64P-M09 *2: FPT-64P-M06 *3: DIP-64P-M01 16 CHAPTER 1 OVERVIEW MB90560 series Memo MB90560 series CHAPTER 1 OVERVIEW 17 1.7 I/O Circuit Types Table 1.7-1 summarizes the I/O circuit types of the MB90560 series. s I/O Circuit Types Table 1.7-1 I/O circuit types Classification Circuit type Remarks X1 Xout * Oscillation circuit Oscillation feedback resistance: About 1 M A X0 Standby control signal B R * Hysteresis input pin Resistance: About 50K(TYP) R Pull-up control signal Pout * CMOS hysteresis input pin with pull-up control CMOS level output CMOS hysteresis input (with standby control for input rejection) Pull-up resistance: About 50K(TYP) C Nout R Hysteresis input Standby control IOL=4mA * CMOS hysteresis I/O pin CMOS level output Pout CMOS hysteresis input (with standby control for input rejection) D R Nout IOL=4mA Hysteresis input Standby control 18 CHAPTER 1 OVERVIEW MB90560 series Table 1.7-2 I/O circuit types (Continued) Classification Circuit type Remarks Pout E R Nout * Analog/CMOS hysteresis I/O pin CMOS level output CMOS hysteresis input (with standby control for input rejection) Analog input (Analog input is enabled when the bit corresponding to ADER is "1".) IOL=4mA Hysteresis input Standby control Analog input Pout * CMOS hysteresis I/O pin CMOS level output CMOS hysteresis input (with standby control for input rejection) IOL=12mA F R Nout Hysteresis input Standby control * Analog power input protection circuit G IN * A/D converter ref+ (AVR) power input pin with power protection circuit Analog input enable signal H IN Analog input enable signal MB90560 series CHAPTER 1 OVERVIEW 19 1.8 Notes on Handling Devices When handling devices, pay special attention to the following eight items or procedures: * Restriction of maximum rated voltage (latchup prevention) * Stabilization of supply voltage * Power-on * Treatment of unused input pins * Treatment of A/D converter power pin * Notes on external clock * Power supply pin * Analog power-on sequence of A/D converter s Notes on Handling Devices q Be sure that the maximum rated voltage is not exceeded (latchup prevention). A latchup may occur on a CMOS IC if a voltage higher than Vcc or lower than Vss is applied to an input or output pin other than medium-to-high voltage pins. A latchup may also occur if a voltage higher than the rating is applied between Vcc and Vss. A latchup causes a rapid increase in the power supply current, which can result in thermal damage to an element. Take utmost care that the maximum rated voltage is not exceeded. When turning the power on or off to analog circuits, be sure that the analog supply voltages (AVcc, AVR) and analog input voltage do not exceed the digital supply voltage (Vcc). q Try to keep supply voltages stable. Even within the operation guarantee range of the Vcc supply voltage, a malfunction can be caused if the supply voltage undergoes a rapid change. For voltage stabilization guidelines, the Vcc ripple fluctuations (P-P value) at commercial frequencies (50 to 60 Hz) should be suppressed to "10%" or less of the reference Vcc value. During a momentary change such as when switching a supply voltage, voltage fluctuations should also be suppressed so that the "transient fluctuation rate" is 0.1 V/ms or less. q Notes on power-on To prevent a malfunction in the built-in voltage regulator circuit, secure "50S (between 0.2 V and 2.7 V)" or more for the voltage rise time during power-on. q Treatment of unused input pins An unused pin may cause a malfunction if it is left open. Every unused pin should be pulled up or down. q Treatment of A/D converter power pin When the A/D converter is not used, connect the pins as follows: AVcc =Vcc, AVss = AVR = Vss. 20 CHAPTER 1 OVERVIEW MB90560 series q Notes on external clock When an external clock is used, the oscillation stabilization wait time is required at power-on reset or at cancellation of stop mode. As shown in Figure 1.8-1, when an external clock is used, connect only the X0 pin and leave the X1 pin open. X0 OPEN X1 MB90560 Series Figure 1.8-1 Sample connection of external clock q Power supply pins When a device has two or more Vcc or Vss pins, the pins that should have equal potential are connected within the device in order to prevent a latchup or other malfunction. To reduce extraneous emission, to prevent a malfunction of the strobe signal due to an increase in the group level, and to maintain the local output current rating, connect all these power supply pins to an external power supply and ground them. The current source should be connected to the Vcc and Vss pins of the device with minimum impedance. It is recommended that a bypass capacitor of about 0.1F be connected near the terminals between Vcc and Vss. q Analog power-on sequence of A/D converter The power to the A/D converter (AVcc, AVRH, AVRL) and analog inputs (AN0 to AN7) must be turned on after the power to the digital circuits (Vcc) is turned on. When turning off the power, turn off the power to the digital circuits (Vcc) after turning off the power to the A/D converter and analog inputs. When the power is turned on or off, AVR should not exceed AVcc. Also, when a pin that is used for analog input is also used as an input port, the input voltage should not exceed AVcc. (The power to the analog circuits and the power to the digital circuits can be simultaneously turned on or off.) MB90560 series CHAPTER 1 OVERVIEW 21 CHAPTER 2 CPU This chapter describes memory space for the MB90560 series. 2.1 CPU.................................................................................................. 24 2.2 Memory Space ................................................................................. 26 2.3 Memory Maps................................................................................... 28 2.4 Addressing ....................................................................................... 29 2.5 Memory Location of Multibyte Data.................................................. 34 2.6 Registers .......................................................................................... 36 2.7 Dedicated Registers ......................................................................... 38 2.8 General-Purpose Registers.............................................................. 56 2.9 Prefix Codes..................................................................................... 58 2.1 CPU The FMC-16LX CPU core is a 16-bit CPU designed for use in applications, such as consumer and mobile equipment, which require high-speed real-time processing. The instruction set of the FMC-16LX was designed for controllers so that it can perform various types of control at high speeds and efficiencies. The FMC-16LX CPU core process not only 16-bit data but also 32-bit data using a builtin 32-bit accumulator. Memory space, which can be extended up to 16M bytes, can be accessed in either linear or bank access mode. The instruction set inherits the AT architecture of FMC-8L, and has additional instructions supporting high-level languages. In addition, it has an extended addressing mode, enhanced multiply/divide instructions, and reinforced bit manipulation instructions. s CPU q Minimum instruction execution time: 62.5 ns (source oscillation at 4 MHz and PLL clock multiplication by 4) q Maximum memory address space: 16M bytes. Access in linear or bank mode q Instruction set optimum for controller applications Many data types (bit, byte, word, and long word) As many as 23 addressing modes Enhanced high-precision arithmetic operation by a 32-bit accumulator Enhanced signed multiply/divide instructions and RETI instruction function q Enhanced interrupt function Eight programmable priority levels q Automatic transfer function independent of CPU Extended intelligent I/O service using up to 16 channels q Instruction set supporting high-level language (C language) and multitasking System stack pointer, instruction set symmetry, and barrel shift instructions q Increased execution speed: 4-byte instruction queue 24 CHAPTER 2 CPU MB90560 series Memo MB90560 series CHAPTER 2 CPU 25 2.2 Memory Space All I/O, programs, and data are located in the 16-megabyte memory space of the F2MC-16LX. A part of the memory space is used for special purposes, such as extended intelligent I/O service (EIOS) descriptors, general-purpose registers, and vector tables. s Memory space All I/O, programs, and data are located in the 16-megabyte memory space of the F2MC-16LX CPU. The CPU is able to access each resource through an address indicated by the 24-bit address bus. Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and the memory map. F2MC-16L device Vector table area Programs Program area ROM area Internal bus External area (*4) ROM area (FF bank image) External area (*4) Data Data area General-purpose register EIOS descriptor area RAM area Interrupts Peripheral circuits General-purpose ports External area (*4) Interrupt control register area Peripheral function control I/O register area I/O port control register area area *1 *2 *3 *4 The size of internal ROM differs for each model. The area accessible by the image differs for each model. The size of internal RAM differs for each model. There is no access in single-chip mode. control register area Figure 2.2-1 Sample relationship between the F2MC-16LX system and the memory map 26 CHAPTER 2 CPU MB90560 series s ROM area q Vector table area (address: FFFC00H to FFFFFFH) * * This area is used as a vector table for vector call instructions, interrupt vectors, and reset vectors. This area is allocated at the highest addresses of the ROM area. The starting address of the corresponding processing routine is stored as data in each vector table address. q Program area (address: Up to FFFBFFH) * * s RAM area q Data area (address: From 000100H) * * The static RAM is built in as an internal data area. The size of internal RAM differs for each device. ROM is built in as an internal program area. The size of internal ROM differs for each device. q General-purpose register area (address: 000180H to 00037FH) * * * Auxiliary registers used for 8-bit, 16-bit, and 32-bit arithmetic operations and transfer operation are allocated in this area. Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM. When this area is used as a general-purpose register, general-purpose register addressing enables high-speed access with short instructions. q Extended intelligent I/O service (EIOS) descriptor area (address: 000100H to 00017FH) * * s I/O area q Interrupt control register area (address: 0000B0H to 0000BFH) The interrupt control registers (ICR00 to ICR15) correspond to all peripheral functions that have an interrupt function. These registers set interrupt levels and control the extended intelligent I/O service (EIOS). q Peripheral function control register area (address: 000020H to 0000AFH) This register controls the built-in peripheral functions and inputs and outputs data. q I/O port control register area (address: 000000H to 00001FH) This register controls I/O ports, and inputs and outputs data. This area retains the transfer modes, I/O addresses, transfer count, and buffer addresses. Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM. MB90560 series CHAPTER 2 CPU 27 2.3 Memory Maps This section shows the memory map for each MB90560 series device. s Memory maps Figure 2.3-1 shows the memory maps for the MB90560 series. Single chip mode (with mirror ROM function) FFFFFF H ROM area Address #1 FF0000 H 010000 H Address #2 004000 H Address #3 000100 H 0000C0 H Peripheral area 000000 H RAM area Register : Internal access memory : Access not allowed ROM area (FF bank image) Model MB90561 MB90562 MB90F562 MB90V560 Address #1 FF8000H FF0000H FF0000H FF0000H *1 Address #2 008000H 004000H 004000H 004000H *1 Address #3 000500H 000900H 000900H 001100H *1: The MB90V560 does not contain ROM. Assume these areas such that the development tool uses there for its ROM decode areas. Figure 2.3-1 Memory maps Notes: If single chip mode (without mirror ROM function) is selected, see "Mirror ROM Function Selection Module." : ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small model C compiler. Because addresses of the 16 low-order bits in the FF bank are the same, the table in ROM can be referenced without the "far" specification. For example, when 00C000H is accessed, the contents of ROM at FFC000H are actually accessed. The ROM area in the FF bank exceeds 48 kilobytes, and all areas cannot be seen as images in the 00 bank. Because ROM data from FF4000H to FFFFFFH is seen as an image at 004000H to 00FFFFH, the ROM data table should be stored in the area from FF4000H to FFFFFFH. 28 CHAPTER 2 CPU MB90560 series 2.4 Addressing The methods for generating addresses are linear addressing and bank addressing. In linear addressing, the complete 24-bit address is specified directly by an instruction. In bank addressing, the upper 8 bits of the address are specified by a appropriate bank register, and the lower 16 bits of the address are specified by the instruction. The F2MC-16LX series generally uses bank addressing. s Linear addressing and bank addressing In linear addressing, the 16-megabyte space is accessed as consecutive address spaces. In bank addressing, the 16-megabyte space is managed by dividing into 256 64-kilobyte banks. Figure 2.4-1 is an overview of linear addressing and bank addressing memory management. Linear addressing Bank addressing FF bank FE bank FD bank 64 kilobytes 12 bank 04 bank 03 bank 02 bank 01 bank 00 bank Specified entirely by an instruction Specified by an instruction Specified by a bank register for the required purpose Figure 2.4-1 Linear addressing and bank addressing memory management MB90560 series CHAPTER 2 CPU 29 2.4 Addressing 2.4.1 Linear addressing The two types of address in linear addressing are specified by a 24-bit address directly in the operand and specified by the lower 24 bits of a 32-bit general-purpose register. s Linear addressing specified by 24-bit operand Old program counter + program bank New program counter + program bank Next instruction Figure 2.4-2 Example of direct specified 24-bit physical address in linear addressing s Addressing by indirect specification with a 32-bit register Old AL New AL (Upper 8 bits are ignored) RL1: 32-bit (long-word) general-purpose register Figure 2.4-3 Example of indirect specified address with a 32-bit general-purpose register in linear addressing 30 CHAPTER 2 CPU MB90560 series Memo MB90560 series CHAPTER 2 CPU 31 2.4 Addressing 2.4.2 Bank addressing In bank addressing, the 16-megabyte memory space is divided into 256 64-kilobyte banks. A bank address that corresponds to each space is specified in the bank register to determine the upper 8 bits of the address. The lower 16 bits of the address are specified by the instruction. The five types of bank register classified by function are as follows: * Program bank register (PCB) * Data bank register (DTB) * User stack bank register (USB) * System stack bank register (SSB) * Additional bank register (ADB) s Bank registers and access space Table 2.4-1 lists the access space and main function of each bank register. Table 2.4-1 Access space and main function of each bank register Bank register name Program bank register (PCB) Data bank register (DTB) User stack bank register (USB) System stack bank register (SSB) (*1) Additional bank register (ADB) Access space Main function Initial value after a reset FFH 00H 00H 00H 00H Program Instruction codes, vector tables, and immediate-value data (PC) space are stored. Data (DT) space Read/write data is stored. Internal or external peripheral control registers and data registers are accessed. This area is used for stack accesses such as when PUSH/ POP instructions and interrupt registers are saved. The Stack (SP) SSB is used when the stack flag in the condition code regspace ister (CCR:S) is 1. The USB is used when the stack flag in the condition code register (CCR:S) is 0. (*1) Additional (AD) space Data that overflows from the data (DT) space is stored. *1 The SSB is always used as an interrupt stack. Figure 2.4-4 shows the relationship between the memory space divisions and each register. See Section 2.7.9, "Bank registers (PCB, DTB, USB, SSB, ADB)," for details. 32 CHAPTER 2 CPU MB90560 series Program space : Program bank register (PCB) Additional space Physical address : Additional bank register (ADB) User stack space : User stack bank register (USB) Data space : Data bank register (DTB) System stack space : System stack bank register (SSB) Figure 2.4-4 Sample bank addressing s Bank addressing and default space To improve instruction coding efficiency, each instruction has a pre-determined default space for each addressing mode, as shown in Table 2.4-2. To use a space other than the default space, specify a prefix code for a bank before the instruction. This enables the bank space that corresponds to the specified prefix code to be accessed.See Section 2.9, "Prefix Codes," for details about prefix codes. Table 2.4-2 Addressing and default spaces Default space Program space Data space Stack space Addressing PC indirect, program access, branching Addressing using @RW0, @RW1, @RW4, and @RW5, @A, addr16, dir Addressing using PUSHW, POPW, @RW3, and @RW7 Additional space Addressing using @RW2 and @RW6 MB90560 series CHAPTER 2 CPU 33 2.5 Memory Location of Multibyte Data Multibyte data is written to memory sequentially from the lower address. If multibyte data is 32-bit data, the lower 16 bits are transferred before the upper 16 bits. If a reset signal is input immediately after the low-order data is written, the high-order bits may not be written. s Storage of multibyte data in RAM Figure 2.5-1 shows the data configuration of multibyte data in memory. The lower 8 bits of the data is located at address n, and subsequent data is located at address n + 1, address n + 2, address n + 3, and so on, in this sequence. Address n MSB: Most Significant Bit LSB: Least Significant Bit Figure 2.5-1 Storage of multibyte data in RAM s Storage of multibyte operand Figure 2.5-2 shows the configuration of a multibyte operand in memory. Address n Figure 2.5-2 Storage of a multibyte operand 34 CHAPTER 2 CPU MB90560 series s Storage of multibyte data in a stack Figure 2.5-3 shows the configuration of multibyte data in a stack. Address n RW1: 35A4H RW3: 6DF0H *1 Stack status after execution of the PUSHW instruction Figure 2.5-3 Storage of multibyte data in a stack s Multibyte data access Accessing is generally performed within a bank. For an instruction that accesses multibyte data, the address following FFFFH is 0000H in the same bank. Figure 2.5-4 shows an example of executing an instruction that accesses multibyte data on a bank boundary. AL before execution AL after execution Figure 2.5-4 Multibyte data access on a bank boundary MB90560 series CHAPTER 2 CPU 35 2.6 Registers F2MC-16LX registers are classified into internal dedicated registers and built-in RAM general-purpose registers. s Dedicated registers and general-purpose registers Dedicated registers are dedicated hardware inside the CPU and their usage are limited by CPU architecture. General-purpose registers are shared the CPU address space with RAM. Just like dedicated registers, general-purpose registers can be accessed without addressing. Just like ordinary memory, the user can specify how the register is used. Figure 2.6-1 shows the location of the dedicated registers and general-purpose registers in the device. Dedicated register Accumulator User stack pointer System stack pointer Internal bus Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register General-purpose register Figure 2.6-1 Dedicated registers and general-purpose registers 36 CHAPTER 2 CPU MB90560 series Memo MB90560 series CHAPTER 2 CPU 37 2.7 Dedicated Registers The following 11 registers are dedicated registers in the CPU. * Accumulator (A) * System stack pointer (SSP) * Program counter (PC) * Program bank register (PCB) * User stack bank register (USB) * Additional data bank register (ADB) * User stack pointer (USP) * Processor status (PS) * Direct page register (DPR) * Data bank register (DPP) * System stack bank register (SSB) s Configuration of dedicated registers Figure 2.7-1 shows the configuration of dedicated registers; Table 2.7-1 lists the initial values of the dedicated registers. : Accumulator (A) Two 16-bit registers used for the storage of arithmetic operation results. The two registers can be combined as a contiguous 32-bit register. : User stack ointer (USP) 16-bit register that indicates the user stack address : System stack pointer (SSP) 16-bit register that indicates the system stack address : Processor status (PS) 16-bit register that indicates the system status : Program counter (PC) 16-bit register that indicates the current instruction storage location : Direct page register (DPR) 8-bit register that specifies bits 8 to 15 of the operand address in short direct addressing : Program bank register (PCB) 8-bit register that indicates the program space : Data bank register (DTB) 8-bit register that indicates the data space : User stack bank register (USB) 8-bit register that indicates the user stack space : System stack bank register (SSB) 8-bit register that indicates the system stack space : Additional data bank register (ADB) 8 bits 8-bit register that indicates the additional space 16 bits 32 bits 38 CHAPTER 2 CPU MB90560 series Figure 2.7-1 Configuration of dedicated registers Table 2.7-1 Initial values of the dedicated registers Dedicated register Accumulator (A) User stack pointer (USP) System stack pointer (SSP) Processor status (PS) bit15 to bit13 bit12 to bit8 bit7 to bit0 Initial value Undefined Undefined Undefined Program counter (PC) Direct page register (DPR) Program bank register (PCB) Data bank register (DTB) User stack bank register (USB) System stack bank register (SSB) Additional data bank register (ADB) Value in reset vector (contents of FFFFDCH, FFFFDDH) 01H Value in reset vector (contents of FFFFDEH) 00H 00H 00H 00H - :Not used x:Undefined MB90560 series CHAPTER 2 CPU 39 2.7 Dedicated Registers 2.7.1 Accumulator (A) The accumulator (A) consists of two 16-bit arithmetic operation registers (AH and AL). The accumulator is used to temporarily store the results of an arithmetic operation and data. The A register can be used as a 32-bit, 16-bit, or 8-bit register. Various arithmetic operations can be performed between memory and other registers or between the AH register and the AL register. The A register has a data retention function that automatically transfers pre-transfer data from the AL register to the AH register when data of word length or less is transferred to the AL register. (Data is not retained with some instructions.) s Accumulator (A) q Data transfer to the accumulator The accumulator can process 32-bit (long word), 16-bit (word), and 8-bit (byte) data. The 4-bit data transfer instruction (MOVN) is an exception. The explanation of 8-bit data also applies to 4bit data. * * * For 32-bit data processing, the AH register and AL register are combined. For 16-bit data and 8-bit data, only the AL register is used. When data of byte length or less is transferred the AL register, data becomes 16 bits long by sign extension or zero extension, and is stored in the AL register. Data in the AL register can be handled as word-length or byte-length data. Figure 2.7-2 shows data transfer to the accumulator. Figures 2.7-3 to 2.7-6 show specific transfer examples. 32-bit 32-bit data transfer Data transfer Data transfer 16-bit data transfer Data save Data transfer 8-bit data transfer Data save 00H or FFH (*1) Data transfer (Zero extension or sign extension) *1 Becomes 000H or FFFH for a 4-bit transfer instruction. Figure 2.7-2 Data transfer to the accumulator 40 CHAPTER 2 CPU MB90560 series (An instruction that zero-extends the contents at address 3000H and stores the result in the AL register) Memory space Before execution x: MSB: LSB: DTB: After execution Undefined Most Significant Bit Least Significant Bit Data bank register Figure 2.7-3 Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, zero extension) (An instruction that stores the contents at address 3000H in the AL register) Memory space Before execution x: MSB: LSB: DTB: After execution Undefined Most Significant Bit Least Significant Bit Data bank register Figure 2.7-4 Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, sign extension) (Instruction that performs a long-word-length read using the result of the RW1 contents + an 8-bit offset as the address and stores the read value in the A register) Memory space Before execution After execution x: MSB: LSB: DTB: Undefined Most Significant Bit Least Significant Bit Data bank register Figure 2.7-5 Example of 32-bit data transfer to the accumulator (A) (register indirect) MB90560 series CHAPTER 2 CPU 41 (Instruction that performs a word-length read using the result of the RW1 contents + an 8-bit offset as the address and stores the read value in the A register) Memory space Before execution After execution x: MSB: LSB: DTB: Undefined Most Significant Bit Least Significant Bit Data bank register Figure 2.7-6 Example of AL-AH transfer in the accumulator (A) (16 bits, register indirect) q Accumulator byte-processing arithmetic operation When a byte-processing arithmetic operation instruction is executed for the AL register, the upper 8 bits of the AL register before the arithmetic operation is executed are ignored. The upper 8 bits of the arithmetic operation results are all zeros. q Initial value of the accumulator The initial value after a reset is undefined. 42 CHAPTER 2 CPU MB90560 series Memo MB90560 series CHAPTER 2 CPU 43 2.7 Dedicated Registers 2.7.2 Stack Pointers (USP, SSP) There are two types of stack pointers: a user stack pointer (USP) and a system stack pointer (SSP). Each stack pointer is a register that indicates the memory address of the location of the destination for saved data or a return address when PUSH instructions, POP instructions, and subroutines are executed. The upper 8 bits of the stack address are specified by the user stack bank register (USB) or system stack bank register (SSB). When the S flag of the condition code register (CCR) is 0, the USP and USB registers are valid. When the S flag is 1, the SSP and SSB registers are valid. s Stack selection The F2MC-16LX uses two types of stack: a system stack and a user stack. The stack address is determined, as shown in Table 2.7-2, by the S flag in the processor status register (PS:CCR). Table 2.7-2 Stack address specification Stack address S flag Upper 8 bits 0 1 User stack bank register (USB) Lower 16 bits User stack pointer (USP) System stack bank register (SSB) System stack pointer (SSP) : Initial value Because the S flag is initialized to 1 by a reset, the system stack is used as the default. Ordinarily, the system stack is used for interrupt routine stack operations, and the user stack is used for all other types of stack operation. When separation of the stack space is not particularly necessary, only the system stack should be used. 44 CHAPTER 2 CPU MB90560 series PUSHW A with the S flag set to 0 Before execution S flag After execution S flag The user stack is used because the S flag is 0 PUSHW A with the S flag set to 1 Before execution S flag After execution S flag x: Undefined MSB: Most Significant Bit LSB: Least Significant Bit The system stack is used because the S flag is 1 Figure 2.7-7 Stack operation instruction and stack pointer s System stack pointer (SSP) To use the system stack pointer (SSP), set the S flag in the condition code register (CCR) of the processor status (PS) to 1. The upper 8 bits of the address that will be used for the stack operation are indicated by the system stack bank register (SSB). s User stack pointer (USP) To use the user stack pointer (USP), set the S flag in the condition code register (CCR) of the processor status (PS) to 0. The upper 8 bits of the address that will be used for the stack operation are indicated by the user stack bank register (USB). MB90560 series CHAPTER 2 CPU 45 2.7 Dedicated Registers 2.7.3 Processor Status (PS) The processor status (PS) consists of CPU control bits and bits that indicate the CPU status. The PS register consists of the following three registers: * Interrupt level mask register (ILM) * Register bank pointer (RP) * Condition code register (CCR) s Processor status (PS) configuration The processor status (PS) consists of CPU control bits and bits that indicate the CPU status. Figure 2.7-8 shows the configuration of the processor status (PS). Initial value -: Not used x: Undefined Figure 2.7-8 Processor status (PS) configuration q Interrupt level mask register (ILM) This register indicates the level of the interrupt currently accepted by the CPU. The value is compared with the value of the interrupt level setting bits (ICR: IL0 to IL2) in the interrupt control register for the peripheral resource interrupt request. q Register bank pointer (RP) This pointer points to the first address of the memory block (register bank) used as the generalpurpose register in the RAM area. There are 32 banks for general-purpose registers. Values 0 to 31 are set in the RP to specify a bank. q Condition code register (CCR) This register consists of flags that are set to 1 or reset to 0 by instruction execution results and by interrupts. 46 CHAPTER 2 CPU MB90560 series Memo MB90560 series CHAPTER 2 CPU 47 2.7 Dedicated Registers 2.7.4 Condition code register (PS: CCR) The condition code register (CCR) is an 8-bit register that consists of the bits that indicate the results of an arithmetic operation and the contents of transfer data and bits that control interrupt request acceptance. s Condition code register (CCR) configuration Figure 2.7-9 shows the configuration of the CCR register. Refer to the programming manual for details about the status of the condition code register (CCR) during instruction execution. CCR initial value -: Not used x: Undefined Interrupt enable flag Stack flag Sticky bit flag Negative flag Zero flag Overflow flag Carry flag Figure 2.7-9 Condition code register (CCR) configuration q Interrupt enable flag (I) In response to all interrupt requests other than software interrupts, when the I flag is "1", interrupts are enabled. When the I flag is "0", interrupts are disabled. This flag is cleared by a reset. q Stack flag (S) This flag indicates which pointer is used for a stack operation. When the S flag is "0", the user stack pointer (USP) is valid. When the S flag is "1", the system stack pointer (SSP) is valid. Set when an interrupt is accepted or when a reset occurs. q Sticky bit flag (T) "1" is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of a logical/arithmetic right shift instruction. Otherwise, "0" is set in T flag. In addition, "0" is set in T flag when the shift value is zero. q Negative flag (N) Set to "1" when the MSB is "1" as the result of an arithmetic calculation. Cleared to "0" when the MSB is 0. q Zero flag (Z) Set to "1" when the result of an arithmetic calculation is all zeros. Otherwise, set to "0". 48 CHAPTER 2 CPU MB90560 series q Overflow flag (V) Set to "1" if a signed numeric value overflows because of an arithmetic calculation. Cleared to "0" if no overflow occurs. q Carry flag (C) Set to "1" when there is an overflow from the MSB or an underflow from the LSB because of an arithmetic calculation. Cleared to "0" when there is no overflow or underflow because of an arithmetic calculation. MB90560 series CHAPTER 2 CPU 49 2.7 Dedicated Registers 2.7.5 Register bank pointer (PS: RP) The register bank pointer (RP) is a register that indicates the first address of the general-purpose register bank currently being used. The RP is used for real address conversion when general-purpose register addressing is used. s Register bank pointer (RP) Figure 2.7-10 shows the configuration of the register bank pointer (RP) register. RP initial value B4 B3 B2 B1 B0 Figure 2.7-10 Configuration of the register bank pointer (RP) s General-purpose register area and register bank pointer The register bank pointer points to the relationship between the general-purpose register of the F2MC-16LX and the address in internal RAM where the general-purpose register exists. Figure 2.7-11 shows the conversion rules used for the relationship between the contents of the RP and the real address. Conversion formula When RP = 10H Register bank 31 Register bank 16 Register bank 0 Figure 2.7-11 Conversion rules for physical address of general-purpose register area * * * Since the RP takes a value from 00H to 1FH, the first address of the register bank can be set in the range from 000180H to 00037FH. Although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to the RP, in actuality only the lower 5 bits of the data are used. The initial value of the RP register after a reset is 00H. 50 CHAPTER 2 CPU MB90560 series 2.7 Dedicated Registers 2.7.6 Interrupt level mask register (PS: ILM) The interrupt level mask register (ILM) is a 3-bit register that indicates the level of the interrupt currently accepted by the CPU. s Interrupt level mask register (ILM) Figure 2.7-12 shows the configuration of the interrupt level mask register (ILM). See Chapter 6, "Interrupts," for details about interrupts. ILM initial value Figure 2.7-12 Configuration of the interrupt level mask register (ILM) The interrupt level mask register (ILM) indicates the level of the interrupt currently accepted by the CPU. The level is compared with the value of the IL0 to IL2 bits of the interrupt control register (ICR00 to ICR15) set according to the interrupt request from the peripheral function. If the interrupt enable flag has been set to enable (CCR: I = 1), the CPU processes the instruction only when the value (interrupt level) of the interrupt request is smaller than the value indicated by these bits. * * * When an interrupt is accepted, the interrupt level value is set in the interrupt level mask register (ILM). Thereafter, interrupts with the same or lower level are not accepted. The interrupt level is set to the highest level, which is the interrupts disabled status, because the interrupt level mask register (ILM) is initialized to all 0s by a reset. Although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to the interrupt level mask register (ILM), only the lower 3 bits of the data are used. Table 2.7-3 Interrupt level mask register (ILM) and interrupt level priority ILM2 0 0 0 0 1 1 1 1 ILM1 0 0 1 1 0 0 1 1 ILM0 0 1 0 1 0 1 0 1 Interrupt level 0 1 2 3 4 5 6 7 Lowest Interrupt level priority Highest (interrupts disabled) MB90560 series CHAPTER 2 CPU 51 2.7 Dedicated Registers 2.7.7 Program Counter (PC) The program counter (PC) is a 16-bit counter that indicates the lower 16 bits of the memory address of the next instruction code to be executed by the CPU. s Program counter (PC) The program bank register (PCB) specifies the upper 8 bits of the address where the next instruction code to be executed by the CPU is stored. The PC specifies the lower 16 bits. Before being used, the actual address is combined to become 24 bits, as shown in Figure 2.7-13. The contents of the PC are updated by conditional branch instructions, subroutine call instructions, interrupts, and resets. The PC can be used as a base pointer for reading operands. Upper 8 bits Upper 16 bits Next instruction to be executed Figure 2.7-13 Program counter (PC) 52 CHAPTER 2 CPU MB90560 series 2.7 Dedicated Registers 2.7.8 Direct Page Register (DPR) The direct page register (DPR) is an 8-bit register that specifies bits 8 to 15 (addr8 to addr15) of the operand address when a short direct addressing instruction is executed. s Direct page register (DPR) As shown in Figure 2.7-14, the DPR specifies bits 8 to 15 (addr8 to addr15) of the operand address when a short direct addressing instruction is executed. The DPR is 8-bits long. The DPR is initialized to 01H by a reset. The DPR can be read and written using an instruction. DTB register DPR register Direct address during instruction 24 bit Physical address MSB: LSB: Most Significant Bit Least Significant Bit Figure 2.7-14 Physical address generation by the direct page register (DPR) Figure 2.7-15 shows an example of direct page register (DPR) setting and data access Instruction execution results DTB register DPR register MSB: LSB: Most Significant Bit Least Significant Bit Upper 8 bits Lower 8 bits Figure 2.7-15 Example of direct page register (DPR) setting and data access MB90560 series CHAPTER 2 CPU 53 2.7 Dedicated Registers 2.7.9 Bank Registers (PCB, DTB, USB, SSB, ADB) Bank registers specify the highest 8-bit address by bank addressing. The five bank registers are as follows: * Program bank register (PCB) * Data bank register (DTB) * User stack bank register (USB) * System stack bank register (SSB) * Additional bank register (ADB) The PCB, DTB, USB, SSB, and ADB registers indicate the individual memory banks where the program space, data space, user stack space, system stack space, and additional space are located. s Bank registers (PCB, DTB, USB, SSB, ADB) q Program bank register (PCB) The PCB is a bank register that specifies the program (PC) space. The PCB is updated when a software interrupt instruction is executed, when the JMPP, CALLP, RETP, and RETI instructions that branch anywhere within the 16-megabyte space are executed, or when a hardware interrupt or exception occurs. q Data bank register (DTB) The DTB is a bank register that specifies the data (DT) space. q User stack bank register (USB), system stack bank register (SSB) The USB and SSB are bank registers that specify the stack (SP) space. Whether the USB or the SSB is used depends on the S flag value in the processor status (PS: CCR). See Section 2.7.2, "Stack pointers (USP, SSP)," for details. q Additional bank register (ADB) The ADB is a bank register that specifies the additional (AD) space. q Bank setting and data access All bank registers are byte length. The PCB is initialized to FFH by a reset. The other bank registers are initialized to 00H by a reset. The PCB can be read, but cannot be written to. The other bank registers can be read and written to. 54 CHAPTER 2 CPU MB90560 series Memo MB90560 series CHAPTER 2 CPU 55 2.8 General-Purpose Registers The general-purpose registers are a memory block allocated in RAM at 000180H to 00037FH as banks, each of which consists of eight 16-bit segments. The general-purpose registers can be used as general-purpose 8-bit registers (byte registers R0 to R7), 16-bit registers (word registers RW0 to RW7), or 32-bit registers (long-word registers RL0 to RL7). General-purpose registers can access RAM with a short instruction at high speed. Since general-purpose registers are blocked into register banks, protection of register contents and division into function units can readily be performed. When a generalpurpose register is used as a long-word register, it can be used as a linear pointer that directly accesses the entire space. s Configuration of a general-purpose register All general-purpose registers exist in RAM at 000180H to 00037FH and are configured as 32 banks. The register bank pointer (RP) specifies the bank that is to be used for a general-purpose register. The RP points to the bank currently being used. The RP determines the first address of each bank with the following formula: Address of first general-purpose register = 000180H + RP x 10H Figure 2.8-1 shows the location and configuration of the general-purpose register banks in the memory space. Built-in RAM Register bank 31 Register bank 30 Byte address Byte address Register bank 21 Register bank 20 Register bank 19 Register bank 2 Register bank 1 Register bank 0 Conversion formula [000180H + RP x 10H] R0 to R7: RW0 to RW7: RL0 to RL3: MSB: LSB: Byte registers Word registers Long-word registers Most Sifnificant Bit Least Significant Bit Figure 2.8-1 Location and configuration of the general-purpose register banks in the memory space s Register bank A register bank can be used as general-purpose registers (byte registers R0 to R7, word registers RW0 to RW7, long-word registers RL0 to RL3) for various arithmetic operations and pointers. A long-word register can be used as a linear pointer that directly accesses the entire memory space. The contents of the register bank, like ordinary RAM, are not initialized by a reset. The status before a reset is retained. At power-on, however, the contents are undefined. Table 2.8-1 lists the typical functions of general-purpose registers. Table 2.8-1 Typical functions of general-purpose registers Register name Function Used as an operand in various instructions R0 to R7 RW0 to RW7 RL0 to RL3 MB90560 series CHAPTER 2 CPU 57 2.9 Prefix Codes Prefix codes are placed before an instruction to partially change the operation of the instruction. The three types of prefix codes are as follows: * Bank select prefix (PCB, DTB, ADB, SPB) * Common register bank prefix (CMR) * Flag change suppression prefix (NCC) s Prefix codes q Bank select prefix (PCB, DTB, ADB, SPB) A bank select prefix is placed before an instruction to select the memory space to be accessed by the instruction regardless of the addressing method. q Common register bank prefix (CMR) The common register bank prefix is placed before an instruction that accesses a register bank to change the register accessed by the instruction to the common bank (register bank selected when RP = 0) at 000180H to 00018FH regardless of the current register bank pointer (RP) value. q Flag change suppression prefix (NCC) The flag change suppression prefix code is placed before an instruction to suppress a flag change accompanying the execution of the instruction. 58 CHAPTER 2 CPU MB90560 series Memo MB90560 series CHAPTER 2 CPU 59 2.9 Prefix Codes 2.9.1 Bank select prefix (PCB, DTB, ADB, SPB) A bank select prefix is placed before an instruction to select the memory space accessed by the instruction regardless of the addressing method. s Bank select prefixes (PCB, DTB, ADB, SPB) The memory space used for data access is defined for each addressing method. If a bank select prefix is placed before an instruction, the memory space accessed by the instruction can be selected regardless of the addressing method. Table 2.9-1 lists the bank select prefix codes and selected memory spaces. Table 2.9-1 Bank select prefix codes and selected memory spaces Bank select prefix PCB DTB ADB SPB Program space Data space Additional space When the value of the S flag in the condition code register (CCR) is 0 and the user stack space is 1, the system stack space is used. Selected space If a bank select prefix is used, some instructions perform an unexpected operation. Table 2.9-2 lists the instructions that are not affected by bank select prefix codes. Table 2.9-3 lists instructions that require caution when they are used. Table 2.9-2 Instructions not affected by bank select prefix codes Instruction type String instruction MOVS SCEQ FILS Instruction MOVSW SCWEQ FILSW Effect of bank select prefix The bank register specified by the operand is used regardless of whether a prefix is used. When the S flag is "0", the user stack bank (USB) is used regardless of whether there is a prefix. When the S flag is "1", the system stack bank (SSB) is used regardless of whether a prefix is used.] MOVX MOVW MOVW MOVB CLRB BBS WBTS A, io io, A io, #imm16 io : bp, A io : bp io : bp, rel io : bp The I/O space ("000000H" to "0000FFH") is accessed regardless of whether there is a prefix. Stack operaPUSHW tion MOV MOVW MOV MOV MOVB SETB BBC WBTC RETI POPW I/O access instruction A A, io io, A io, #imm8 A, io : bp io : bp io : bp, rel io, bp Interrupt return instruction The system stack bank (SSB) is used regardless of whether a prefix is used. 60 CHAPTER 2 CPU MB90560 series Table 2.9-3 Instructions which use requires caution when bank select prefix codes are used Instruction type Flag change instruction ILM setting instruction PS return instruction AND OR MOV POPW Instruction CCR, #imm8 CCR, #imm8 ILM, #imm8 PS Explanation The effect of the prefix extends to the next instruction. The effect of the prefix extends to the next instruction. Do not place a bank select prefix before the PS return instruction. MB90560 series CHAPTER 2 CPU 61 2.9 Prefix Codes 2.9.2 Common register bank prefix (CMR) The common register bank (CMR) prefix is placed before an instruction that accesses a register bank to change the register accessed by the instruction to the common bank (register bank selected when RP = 0) at 000180H to 00018FH regardless of the current register bank pointer (RP) value. s Common register bank prefix (CMR) To facilitate data exchange between multiple tasks, a relatively simple means of accessing a fixed register bank regardless of the current register bank pointer (RP) value is necessary. This is the reason that the F2MC-16LX provides a common register bank for tasks, which is called the common bank. The common bank is located at address 000180H to 00018FH. If the common register bank prefix (CMR) is placed before an instruction that accesses a register bank, registers accessed by the instruction can be changed to the common bank (register bank selected when RP = 0) at 000180H to 00018FHH regardless of the current register bank pointer (RP) value. Note that caution is required when this prefix is used with the instructions listed in Table 2.9-4. Table 2.9-4 Instructions whose use requires caution when the common register bank prefix (CMR) is used Instruction type String instruction Flag change instruction PS return instruction ILM setting instruction MOVS SCEQ FILS AND CCR, #imm8 Instruction MOVSW SCWEQ FILSW OR CCR, #imm8 Explanation Do not place the CMR prefix before the string instruction. The effect of the prefix extends to the next instruction. The effect of the prefix extends to the next instruction. The effect of the prefix extends to the next instruction. POPW PS MOV ILM, #imm8 62 CHAPTER 2 CPU MB90560 series 2.9 Prefix Codes 2.9.3 Flag change suppression prefix (NCC) The flag change suppression prefix (NCC) code is placed before an instruction to suppress a flag change accompanying the execution of the instruction. s Flag change suppression prefix (NCC) The flag change suppression prefix (NCC) is used to suppress unnecessary flag changes. If a flag change suppression prefix code is placed before an instruction, a flag change accompanying the execution of the instruction is suppressed. Changes of the T, N, Z, V, and C flags are suppressed. Note that caution is required when this prefix is used with the instructions listed in Table 2.9-5. Table 2.9-5 Instructions requiring caution when the flag change suppression prefix (NCC) is used Instruction type String instruction MOVS SCEQ FILS Instruction MOVSW SCWEQ FILSW Explanation Do not place the NCC prefix before the string instruction. The condition code register (CCR) changes as defined in the instruction specification regardless of whether a prefix is used. The effect of prefix extends to the next instruction. The condition code register (CCR) changes as defined in the instruction specification regardless of whether a prefix is used. The effect of prefix extends to the next instruction. The effect of prefix extends to the next instruction. Flag change instruction AND CCR, #imm8 OR CCR, #imm8 PS return instruction ILM setting instruction Interrupt instruction POPW PS MOV INT INT RETI ILM, #imm8 #vct8 adder16 INT9 INTP Interrupt return instruction Context switch instruction addr24 The condition code register (CCR) changes as defined in the instruction specification regardless of whether a prefix is used. The condition code register (CCR) changes as defined in the instruction specification regardless of whether a prefix is used. JCTX @A MB90560 series CHAPTER 2 CPU 63 2.9 Prefix Codes 2.9.4 Restrictions on Prefix Codes The following three restrictions are imposed on the use of prefix codes: * Interrupt/hold requests are not accepted during the execution of prefix codes and interrupt/hold suppression instructions. * If a prefix code is placed before an interrupt/hold instruction, the effect of the prefix code is delayed. * If consecutively placed prefix codes conflict, the last prefix code is valid. s Prefix codes and interrupt/hold suppression instructions Table 2.9-6 lists the interrupt/hold suppression instructions and prefix codes that have restrictions. Table 2.9-6 Prefix codes and interrupt/hold suppression instructions Prefix codes PCB DTB ADB SPB CMR NCC Interrupt/hold suppression instructions (instructions that delay the effect of prefix codes) MOV OR AND POPW Instructions that do not accept interrupt and hold requests ILM, #imm8 CCR, #imm8 CCR, #imm8 PS q Interrupt/hold suppression As shown in Figure 2.9-1, an interrupt or hold request generated during the execution of prefix codes and interrupt/hold instructions is not accepted. The interrupt/hold is not processed until the first instruction that is not governed by a prefix code or that is not an interrupt/hold suppression instruction is executed. Interrupt/hold suppression instruction Interrupt request generated (a) Ordinary instruction Interrupt accepted Figure 2.9-1 Interrupt/hold suppression 64 CHAPTER 2 CPU MB90560 series q Delay of the effect of prefix codes As shown in Figure 2.9-2, if a prefix code is placed before an interrupt/hold suppression instruction, the prefix code takes effect with the first instruction executed after the interrupt/hold suppression instruction. Interrupt/hold suppression instruction NCC does not cause the CCR to change. Figure 2.9-2 Interrupt/hold suppression instructions and prefix codes s Consecutive prefix codes As shown in Figure 2.9-3, when consecutive conflicting prefix codes (PCB, ADB, DTB, and SPB) are specified, the last prefix code is valid. Prefix code Prefix code PCB is valid. Figure 2.9-3 Consecutive prefix codes MB90560 series CHAPTER 2 CPU 65 CHAPTER 3 RESETS This chapter describes resets for the MB90560-series microcontrollers. 3.1 Resets .............................................................................................. 68 3.2 Reset Causes and Oscillation Stabilization Wait Intervals ............... 70 3.3 External Reset Pin............................................................................ 72 3.4 Reset Operation ............................................................................... 74 3.5 Reset Cause Bits.............................................................................. 76 3.6 Status of Pins in a Reset .................................................................. 78 3.1 Resets If a reset cause is generated, the CPU immediately stops the current execution process and waits for the release of the reset. When the reset is released, the CPU begins processing at the address indicated by the reset vector. There are four causes of a reset: * Power-on reset * Watchdog timer overflow * External reset request via the RSTX pin * Software reset request s Reset causes Table 3.1-1 lists the reset causes. Table 3.1-1 Reset causes Type of reset Cause Machine clock Previous state retained Previous state retained MCLK MCLK Watchdog timer Previous state retained Previous state retained Stop Stop Oscillation stabilization wait No No Yes Yes External pin Software Watchdog timer Power-on "L" level input to RST pin A "0" is written to the RST bit of the low power consumption mode control register (LPMCR). Watchdog timer overflow When the power is turned on MCLK: Main clock (oscillation clock divided by 2) q External reset An external reset is generated by the "L" level input to an external reset pin (RSTX pin). The minimum required period of the "L" level input to the RSTX pin is 16 machine cycles (16/). The oscillation stabilization wait interval is not required for external resets. 68 CHAPTER 3 RESETS MB90560 series q Software reset A software reset is an internal reset of three machine cycles (3/) generated by writing "0" to the RST bit of the low power mode control register (LPMCR). The oscillation stabilization wait interval is not required for software resets. q Watchdog timer reset A watchdog timer reset is generated by a watchdog timer overflow that occurs when a "0" is not written to the WTE bit of the watchdog timer control register (WDTC) within a given time after the watchdog timer is activated. The watch-dog reset will wait for oscillation stabilization watch interval. The oscillation stabilization wait interval can be set by the clock selection register (CKSCR). q Power-on reset A power-on reset is generated when the power is turned on. The oscillation stabilization wait interval is fixed at 217 oscillation clock cycles (217/HCLK). After the oscillation stabilization wait interval has elapsed, the reset is executed. See also * Definition of clocks HCLK: Oscillation clock MCLK: Main clock : Machine clock (CPU operating clock) 1/: Machine cycle (CPU operating clock cycle) See Chapter 4, "Clocks," for details. MB90560 series CHAPTER 3 RESETS 69 3.2 Reset Causes and Oscillation Stabilization Wait Intervals The F2MC-16LX has five reset causes. The oscillation stabilization wait interval for a reset depends on the reset cause. s Reset causes and oscillation stabilization wait intervals Tables 3.2-1 and 3.2-2 summarize reset causes and oscillation stabilization wait intervals. Table 3.2-1 Reset causes and oscillation stabilization wait intervals Reset cause Power-on reset Watchdog timer External reset via the RSTX pin Software reset Oscillation stabilization wait interval The corresponding time interval for an oscillation clock frequency of 4 MHz is given in parentheses. 217/HCLK (32.768 ms) 217/HCLK (32.768 ms) None None HCLK:Oscillation clock frequency, source oscillation Table 3.2-2 Oscillation stabilization wait intervals set by the clock selection register (CKSCR) WS1 0 0 1 1 WS0 0 1 0 1 Oscillation stabilization wait interval The corresponding time interval for an oscillation clock frequency of 4 MHz is given in parentheses. No oscillation stabilization time. 213/HCLK (2.048 ms) 215/HCLK (8.192 ms) 217/HCLK (32.768 ms) HCLK: Oscillation clock frequency 70 CHAPTER 3 RESETS MB90560 series Memo MB90560 series CHAPTER 3 RESETS 71 3.3 External Reset Pin The external reset pin (RST pin) is a dedicated pin for inputting, with an L level signal, a reset and generating an internal reset by the L level input. In MB90560 series microcontrollers, there are internal CPU synchronous reset and external synchronous reset. s Block diagrams of the external reset pin q Block diagram of internal reset RSTX Pin Pch Nch CPU operating clock (PLL multiplier circuit with a frequency of HCLK divided by 2) Synchronization curcuit Internal reset signal HCLK: Oscillation clock Input buffer Figure 3.3-1 Block diagram of internal reset 72 CHAPTER 3 RESETS MB90560 series q Block diagram of internal reset for external pin RSTX Pin Pch Nch Internal reset signal HCLK: Oscillation clock Input buffer Figure 3.3-2 Block diagram of internal reset for external pin MB90560 series CHAPTER 3 RESETS 73 3.4 Reset Operation When a reset is released, the memory locations from which the mode data and the reset vector are read are selected according to the setting of the mode pins, and the mode setting data is fetched. Mode setting data determines the CPU operating mode and the execution start address after a reset operation ends. For power-on or recovery from stop mode by a reset, the mode is fetched after the oscillation stabilization wait time has elapsed. s Overview of reset operation Figure 3.4-1 shows the reset operation flow. Power-on reset Stop mode Watchdog timer reset During a reset Oscillation stabilization wait and reset state External reset Software reset Fetching the mode data Mode fetch (Reset operation) Pin state and function change Fetching the reset vector CPU executes an instruction, fetching instruction codes from the address indicated by the reset vector. Normal operation (Run state) Figure 3.4-1 Reset operation flow s Mode pins Setting the mode pins (MD0 to MD2) specifies how to fetch the reset vector and the mode data. Fetching the reset vector and the mode data is performed in the reset sequence. See Chapter 7, "Setting a Mode," for details about mode pins. 74 CHAPTER 3 RESETS MB90560 series s Mode fetch When the reset is cleared, the CPU transfers the reset vector and the mode data stored in the hardware memory to the appropriate registers in the CPU core. The reset vector and mode data are allocated to the four bytes from FFFFDCH to FFFFDFH. The CPU outputs these addresses to the bus immediately after the reset is cleared and fetches the reset vector and mode data. Using mode fetching, the CPU can begin processing at the address indicated by the reset vector. Figure 3.4-2 shows the transfer of the reset vector and mode data. Memory space F2MC-16L CPU core Mode register Mode data Bits 23 to 16 of the reset vector Bits 15 to 8 of the reset vector Bits 7 to 0 of the reset vector Micro-ROM Reset sequence Figure 3.4-2 Transfer of reset vector and mode data q Mode data (address: FFFFDFH) Only s reset operation changes the contents of the mode register. The mode register setting is valid after a reset operation. See Section 7.1, "Setting a Mode," for details about mode data. q Reset vector (address: FFFFDCH to FFFFDEH) The execution start address after the reset operation ends is written as the reset vector. Execution starts at the address contained in the reset vector. MB90560 series CHAPTER 3 RESETS 75 3.5 Reset Cause Bits A reset cause can be identified by checking the watchdog timer control register (WDTC). s Reset cause bits As shown in Figure 3.5-1, a flip-flop is associated with each reset cause. The contents of the flipflops are obtained by reading the watchdog timer control register (WDTC). If it is necessary to identify the cause of a reset after the reset has been released, the value read from the WDTC should be processed by the software and a branch made to the appropriate program. RSTX pin Power-on Power-on detection circuit RSTX=L External reset request detection cirtuit No periodic clear Watchdog timer reset generation detection cirtuit RST bit set LPMCR:RST bit write detection circuit Watchdog timer control register (WDTC) S F/F Q Q R S F/F Q R S F/F Q R S Clear R F/F Delay circuit Reading of watchdog timer control register (WDTC) F2MC-16LX @Internal bus S : Set R : Reset Q : Output F/F : Flip Flop Figure 3.5-1 Block diagram of reset cause bits 76 CHAPTER 3 RESETS MB90560 series s Correspondence between reset cause bits and reset causes Figure 3.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC). Table 3.5-1 maps the correspondence between the reset cause bits and reset causes. Watchdog timer control register (WDTC) bit15 (TBTC) bit8 bit7 PONR R R : Read only W : Write only X : Undefined Address 0000A8H bit6 - bit5 bit4 bit3 bit2 bit1 bit0 Initial value WRST ERST SRST WTE WT1 WT0 1XXXXXXXB R R R W W W Figure 3.5-2 Configuration of reset cause bits (watchdog timer control register) Table 3.5-1 Correspondence between reset cause bits and reset causes Reset cause Power-on reset Watchdog timer overflow External reset request via RST pin Software reset request PONR 1 * * * WRST X 1 * * ERST X * 1 * SRST X * * 1 *:Previous state retained X:Undefined s Notes about reset cause bits q Multiple reset causes generated at the same time When multiple reset causes are generated at the same time, the corresponding reset cause bits of the watchdog timer control register (WDTC) are set to "1". If, for example, an external reset request via the RSTX pin and the watchdog timer overflow occur at the same time, both the ERST bit and the WRST bit are set to "1". q Power-on reset For a power-on reset, the PONR bit is set to "1", but all other reset cause bits are undefined. Consequently, program the software so that it will ignore all reset cause bits except the PONR bit if it is "1". q Clearing the reset cause bits The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Once a reset is occurred, the corresponding reset cause bit remains to "1", even though another reset cause is occurred. MB90560 series CHAPTER 3 RESETS 77 3.6 Status of Pins in a Reset This section describes the status of pins when a reset occurs. s Status of pins during a reset The status of pins during a reset depends on the settings of mode pins (MD2 to MD0 = "011"). q When internal vector mode has been set: All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM. s Status of pins after mode data is read The status of pins after mode data has been read depends on the mode data (M1 and M0 = 00). q When single-chip mode has been selected (M1, M0 = 00B): All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM. 78 CHAPTER 3 RESETS MB90560 series Memo MB90560 series CHAPTER 3 RESETS 79 CHAPTER 4 CLOCKS This chapter describes the clocks used by MB90560 series microcontrollers. 4.1 Clocks............................................................................................... 82 4.2 Block Diagram of the Clock Generator............................................. 84 4.3 Clock Selection Register (CKSCR) .................................................. 86 4.4 Clock Mode ...................................................................................... 88 4.5 Oscillation Stabilization Wait Interval ............................................... 90 4.6 Connection of an Oscillator or an External Clock............................. 91 4.1 Clocks The clock generator controls the operation of the internal clock for the CPU and peripheral functions. This internal clock is called the machine clock. One internal clock cycle is regarded as one machine cycle. Other clocks include a clock generated by source oscillation, called an oscillation clock, and a clock generated by the internal PLL oscillation, called a PLL clock. s Clocks The clock generator block contains the oscillation circuit that generates the oscillation clock. An external oscillator is connected to this circuit. The oscillation clock can also be supplied by inputting an external clock to the clock generator. The clock generator also contains the PLL clock multiplier circuit, which generates four types of clock, that are multiples of the oscillation clock. The clock generator controls the oscillation stabilization wait interval and PLL clock multiplication as well as controls internal clock operation by changing the clock with a clock selector. q Oscillation clock (HCLK) The oscillation clock is generated either from an external oscillator connected to the oscillation circuit or by input of an external clock. q Main clock (MCLK) The main clock, which is the oscillation clock divided by 2, supplies the clock input to the timebase timer and the clock selector. q PLL clock (PCLK) The PLL clock is obtained by multiplying the oscillation clock with the internal PLL clock multiplier circuit (PLL oscillation circuit). Selection can be made from among four different PLL clocks. q Machine clock () The machine clock controls operation of the operation of the CPU and peripheral functions. One clock cycle is regarded as one machine cycle (1/). An operating machine clock can be selected from among the main clock that is generated from the oscillation clock divided by 2 and the four types of clock, that are multiples of the source clock frequency. s Clock supply map Since the machine clock generated by the clock generator is supplied as the operating clock for the CPU and peripheral functions, the operation of the CPU and peripheral functions is affected by switching of the main clock and the PLL clock (clock mode) and a change in the PLL clock multiplier. Since the timebase timer output will supply the operating clock for some peripheral functions, a peripheral function can select the clock best suited for its operation. Figure 4.1-1 shows the clock supply map. Peripheral function 4 Watchdog timer 8/16-bit PPG timer 0/2/4 8/16-bit PPG timer 1/3/5 Timebase timer Clock generator 1234 X0 Pin X1 Pin PLL multipiler circuit System Divide-by-2 clock generation HCLK MCLK circuit PCLK Clock selecter UART1 UART0 SCK0 Pin SCK1 Pin TIN1 Pin CPU 3 16-bit reload timer 1 TO1 Pin 3 16-bit reload timer 0 PPG0/2/4 Pin PPG1/3/5 Pin TIN0 Pin TO0 Pin 3 A/D converter IC interface Output compare unit 16-bit free-run timer Input capture unit 3 Oscillation stabilization wait control HCLK: MCLK: PCLK: : Oscillation clock Main clock PLL clock Machine clock Figure 4.1-1 Clock supply map MB90620 series CHAPTER 4 CLOCKS 83 4.2 Block Diagram of the Clock Generator The clock generator consists of five blocks: * System clock generation circuit * PLL multiplier circuit * Clock selector * Clock selection register (CKSCR) * Oscillation stabilization wait interval selector s Block diagram of the clock generator Figure 4.2-1 shows a block diagram of the clock generator and also includes the standby control circuit and timebase timer circuit. Standby control circuit Low power mode control register (LPMCR) STP SLP SPL RST RESV CG1 CG0 RESV 2 CPU intermittent operation cycles selecter Stop and sleep signals Reset Interrupt SQ R SQ R CPU clock control circuit Stop signal CPU operating clock SQ R Machine clock Peripheral clock control circuit Peripheral function operating clock Clock selector 2 2 Oscillation stabilization wait interval selector PLL multipiller circuit RESV MCM WS1 WS0 RESV MCS CS1 CS0 Clock selection register (CKSCR) Timebase timer X0 X1 Pin Pin Divide- Oscillation by-2 clock System clock generation circuit Divideby-2048 Divideby-4 Divideby-4 Divideby-4 Main clock To watchdog timer S: Set R: Reset Q: Output Figure 4.2-1 Block diagram of the clock generator 84 CHAPTER 4 CLOCKS MB90620 series q System clock generation circuit The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator connected to it. Alternatively, an external clock can be input to this circuit. q PLL multiplier circuit The PLL multiplier circuit multiplies the oscillation clock through PLL oscillation and supplies this multiplied clock to the CPU clock selector. q Clock selector From among the main clock and four different PLL clocks, the clock selector selects the clock that is supplied to the CPU and peripheral clock control circuits. q Clock selection register (CKSCR) The clock selection register is used to set switching between the oscillation clock and a PLL clock to select an oscillation stabilization wait interval, and to select a PLL clock multiplier. q Oscillation stabilization wait interval selector This selector selects an oscillation stabilization wait interval for the oscillation clock when returning from stop mode or after a watchdog timer reset. Selection is made from among three kinds of timebase timer output. In all other cases, an oscillation stabilization wait interval is not selected. MB90620 series CHAPTER 4 CLOCKS 85 4.3 Clock Selection Register (CKSCR) The clock selection register (CKSCR) is used to switch between the main clock and a PLL clock, to select an oscillation stabilization wait interval, and to select a PLL clock multiplier. s Configuration of the clock selection register (CKSCR) Figure 4.3-1 shows the configuration of the clock selection register (CKSCR); Table 4.3-1 describes the function of each bit of the clock selection register (CKSCR). bit15 bit14 bit13 bit12 bit11 bit10 Address 0 0 0 0 A 1 H RESV MCM WS1 WS0 RESV MCS R/W R R/W R/W R/W R/W bit9 CS1 R/W bit8 CS0 R/W bit7 (LPMSR) bit0 Initial value 11111100B CS1 CS0 0 0 1 1 MCS 0 1 0 1 0 1 Multiplier selection bits The resulting clock frequency is shown in parenthness 1 x HCLK (4MHz) 2 x HCLK (8MHz) 3 x HCLK (12MHz) 4 x HCLK (16MHz) Machine clock selection bit PLL clock selected. Main clock selected. Oscillation stabilization wait interval selection bits The corresponding time interval for an oscillation clock frequency of 4 MHz is given in parentheses. WS1 WS0 0 0 1 1 MCM 0 1 RESV HCLK: Oscillation clock frequency R/W: Read/write R: Read only -: Unused : Initial value 0 1 0 1 No oscillation stabilization wait interval 13 2 / HCLK (Aprox. 2.05ms) 15 2 / HCLK (Aprox. 8.19ms) 17 2 / HCLK (Aprox. 32.768ms) Machine clock indication bit A PLL clock is used as the machine clock. The main clock is usedas the machine clock. Reserved bit 1 must always be written to these bits. Figure 4.3-1 Configuration of the clock selection register (CKSCR) Table 4.3-1 Function description of each bit of the clock selection register (CKSCR) Bit name bit 15 bit 11 RESV: Reserved bit MCM: Machine clock indication bit Function * This bit indicates whether the main clock or a PLL clock has been selected bit 14 * When this bit is set to "0", a PLL clock has been selected. When it is set to * If MCS = 0 and MCM = 1, the PLL clock oscillation stabilization wait period is in effect. "1", the main clock has been selected. as the machine clock. * These bits select an oscillation stabilization wait interval of the oscillation WS1, WS0: Oscillation stabilization wait interval selection bits * These bits are initialized to 11B by all reset causes. clock after stop mode has been cancelled. bit 13 bit 12 * This bit specifies whether the main clock or a PLL clock is selected as the * When this bit is "0", a PLL clock is selected. When this bit is "1", the main clock is selected. "0" is written to this bit while it is "1", the oscillation stabilization wait interval for the PLL clock starts. As a result, the timebase timer is automatically cleared, and the TBOF bit of the timebase timer control register (TBTC) is also cleared. * For PLL clocks, the oscillation stabilization period is fixed at 213/HCLK (the oscillation stabilization wait interval is approx. 2 ms for an oscillation clock frequency of 4 MHz). * When the main clock has been selected, the operating clock frequency is the frequency of the oscillation clock divided by 2 (e.g., the operating clock is 2 MHz when the oscillation clock frequency is 4 MHz). * This bit is initialized to 1 by all reset causes. * bit 10 MCS: Machine clock selection bit bit 9 bit 8 CS1, CS0: Multiplier selection bits * These bits select a PLL clock multiplier. * Selection can be made from among four different multipliers. * These bits are initialized to 00B by all reset causes. HCLK: Oscillation clock frequency MB90620 series CHAPTER 4 CLOCKS 87 4.4 Clock Mode Two clock modes are provided: main clock mode and PLL clock mode. s Main clock mode and PLL clock mode q Main clock mode In main clock mode, the main clock, which is the oscillation clock divided by 2 and is used as the operating clock for the CPU and peripheral resources. Meanwhile, the PLL clocks are disabled. q PLL clock mode In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and CS0). s Clock mode transition Switching between main clock mode and PLL clock mode is done by writing to the MCS bit of the clock selection register (CKSCR). q Switching from main clock mode to PLL clock mode When the MCS bit of CKSCR is "1", writing "0" to it will switch the operating clock from the main clock to a PLL clock after the PLL clock oscillation stabilization wait period (213/HCLK). q Switching from PLL clock mode to main clock mode When the MCS bit of CKSCR is "0", writing "1" to it will switch the operating clock from the PLL clock to the main clock when the edges of the PLL clock and the main clock coincide (after 1 to 8 PLL clocks). 88 CHAPTER 4 CLOCKS MB90620 series Figure 4.4-1 shows the status change caused by the machine clock switching. Power-on (1) Main MCS = 1 MCM = 1 CS1, CS0 = xx Main PLLx MCS = 0 MCM = 1 CS1, CS0 = xx (2) (3) (4) (5) (6) (7) PLL1 Main MCS = 1 MCM = 1 CS1, CS0 = 00 PLL1: Multiplied by 1 (6) MCS = 0 MCM = 0 CS1, CS0 = 00 (7) PLL2 Main MCS = 1 MCM = 0 CS1, CS0 = 01 PLL2: Multiplied by 2 MCS = 0 (6) MCM = 0 CS1, CS0 = 01 (7) PLL3 Main MCS = 1 MCM = 0 CS1, CS0 = 11 (6) PLL3: Multiplied by 3 MCS = 0 MCM = 0 CS1, CS0 = 10 (7) PLL4 Main MCS = 1 MCM = 0 CS1, CS0 = 11 (6) PLL4: Multiplied by 4 MCS = 0 MCM = 0 CS1, CS0 = 11 (1) The MCS bit is cleared. (2) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 00. (3) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 01. (4) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 10. (5) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 11. (6) The MCS bit is set (including also watchdog timer resets). (7) PLL clock and main clock synchronization timing MCS: Machine clock selection bit of CKSCR MCM: Machine clock indication bit of CKSCR CS1, CS0: Multiplier selection bits of CKSCR Figure 4.4-1 Status change diagram for machine clock selection MB90620 series CHAPTER 4 CLOCKS 89 4.5 Oscillation Stabilization Wait Interval When the system changes operation from a state in which the main clock is stopped (such as at power-on, in stop mode and at watch-dog reset), a delay (an oscillation stabilization wait interval) is required to stabilize the clock oscillation before operation starts. When the switch from the main clock to a PLL clock occurs, an oscillation stabilization wait interval is also required when PLL oscillation starts. s Oscillation stabilization wait interval Ceramic and crystal oscillators generally take several milliseconds to 20 milliseconds to stabilize at their natural frequency when oscillation starts. For this reason, CPU operation is not allowed as soon as oscillation starts and is allowed only after full stabilization of oscillation. After the oscillation stabilization wait interval has elapsed, the clock is supplied to the CPU. Because the oscillation stabilization time depends on the type of the oscillator (crystal, ceramic, etc.), the proper oscillation stabilization wait interval for the oscillator used must be selected. An oscillation stabilization wait interval is selected by setting the clock selection register (CKSCR). In a switch from the main clock to a PLL clock, the CPU continues to operate on the main clock during the oscillation stabilization wait interval for PLL. After this interval, the operating clock switches to the PLL clock. Figure 4.5-1 shows the operation after oscillation starts. Oscillator-activated Oscillation stabilization Normal operation start wait interval oscillation time or change to PLL clock Start of oscillation Stable oscillation Figure 4.5-1 Operation when oscillation starts 90 CHAPTER 4 CLOCKS MB90620 series 4.6 Connection of an Oscillator or an External Clock The F2MC-16LX microcontroller contains a system clock generation circuit. Connecting an external oscillator to this circuit generates the system clock. Alternatively, an externally generated clock can be input to the microcontroller. s Connection of an oscillator or an external clock to the microcontroller q Example of connecting a crystal or ceramic oscillator to the microcontroller Connect a crystal or ceramic oscillator as shown in the example in Figure 4.6-1. X0 MB90560 X1 Figure 4.6-1 Example of connecting a crystal or ceramic oscillator to the microcontroller q Example of connecting an external clock to the microcontroller As shown in Figure 4.6-2, connect an external clock to pin X0. Pin X1 must be open. X0 MB90560 ~ Open Figure 4.6-2 Example of connecting an external clock to the microcontroller MB90620 series CHAPTER 4 CLOCKS 91 CHAPTER 5 LOW POWER CONSUMPTION MODE This chapter describes the low power consumption mode of MB90560 series microcontrollers. 5.1 Low Power Consumption Mode ....................................................... 94 5.2 Block Diagram of the Low Power Consumption Control Circuit ....... 96 5.3 Low Power Mode Control Register (LPMCR)................................... 98 5.4 CPU Intermittent Operation Mode .................................................. 102 5.5 Standby Mode ................................................................................ 103 5.6 Status Change Diagram ................................................................. 112 5.7 Status of Pins in Standby Mode and Reset.................................... 115 5.8 Notes on Using Low Power Consumption Mode............................ 116 5.1 Low Power Consumption Mode F2MC-16LX microcontrollers have the following CPU operating modes, any of which can be used depending on the operating clock selection and clock operation control: * Clock mode (PLL clock mode and main clock mode) * CPU intermittent operation mode (PLL clock intermittent operation mode and main clock intermittent operation mode) * Standby mode (sleep, timebase timer and stop) All modes other than PLL clock mode are low power consumption modes. s CPU operating modes and current consumption Figure 5.1-1 shows the relation between the CPU operating modes and current consumption Current consumption Several tens of mA CPU operating mode PLL clock mode Multiplied-by-four clock Multiplied-by-three clock Multiplied-by-two clock Multiplied-by-1 clock Multiplied-by-four clock Multiplied-by-three clock Multiplied-by-two clock Multiplied-by-1 clock PLL clock intermittent operation mode Main clock mode (1/2 clock mode) Main clock intermittent operation mode Several mA Standby mode Sleep mode Timebase timer mode Stop mode/hardware standby mode Several A Low power consumption mode Note: This figure is only an indication of power consumption for each mode. Actual current consumption values may not agree with those in the figure. Figure 5.1-1 CPU operating modes and current consumption 94 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series s Clock mode q PLL clock mode A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the CPU and peripheral functions. q Main clock mode The main clock, with a frequency one-half that of the oscillation clock (HCLK), is used to operate the CPU and peripheral functions. In main clock mode, the PLL multiplier circuit is inactive. MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 95 5.2 Block Diagram of the Low Power Consumption Control Circuit The low power consumption control circuit consists of the following seven blocks: * CPU intermittent operation selector * Standby clock control circuit * CPU clock control circuit * Peripheral clock control circuit * Pin high-impedance control circuit * Internal reset generation circuit * Low power mode control register (LPMCR) s Block diagram of the low power consumption control circuit Figure 5.2-1 shows the block diagram of the low power consumption control circuit. Low power mode control register (LPMCR) STP SLP SPL RST RESV CG1 CG0 RESV Pin high impedance control circuit Internal reset generation circuit CPU intermittent operation selecter Pin Hi-z control RST Pin Internal reset Select intermittent cycles CPU clock control circuit CPU clock Release reset 2 RST Standby control circuit Stop and sleep signals Cancel interrupt Stop signal Clock generator Clock selector Machine clock Peripheral clock Oscillation stabiliz- control circuit -ation wait is passed Peripheral clock 2 2 PLL multipiller circuit Oscillation stabilization wait interval selector RESV MCM WS1 WS0 RESV MCS Clock selection register (CKSCR) CS1 CS0 X0 Pin System clock generation circuit Divideby-2 Divideby-2048 Divideby-4 Divideby-4 Divideby-8 Main clock X1 Pin Timebase timer Figure 5.2-1 Block diagram of the low power consumption control circuit 96 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series q CPU intermittent operation selector This selector selects the number of clock pulses the CPU is to be halted during CPU intermittent operation mode. q Standby control circuit The standby control circuit controls the CPU clock control circuit and the peripheral clock control circuit, and turns the low power consumption mode on and off. q CPU clock control circuit This circuit controls the clocks supplied to the CPU. q Peripheral clock control circuit This circuit controls the clocks supplied to peripheral functions. q Pin high-impedance control circuit This circuit makes the external pins high-impedance when the microcontroller enters timebase timer mode and stop mode. For the pins with the pull-up option, this circuit disconnects the pull-up resistor when the microcontroller enters stop mode or hardware standby mode. q Internal reset generation circuit This circuit generates an internal reset signal. q Low power consumption mode control register (LPMCR) This register is used to switch to and return from standby mode and to set the CPU intermittent operation function. MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 97 5.3 Low Power Mode Control Register (LPMCR) The low power mode control register (LPMCR) switches to or releases low power consumption mode. It is also used to set the number of CPU clock pulses the CPU is to be halted during CPU intermittent mode. s Low power consumption mode control register (LPMCR) Figure 5.3-1 shows the configuration of the low power consumption mode control register (LPMCR). bit15 Address 0000A0H (CKSCR) bit8 STP W bit7 SLP W bit6 SPL R/W bit5 RST W bit4 RESV R/W bit2 CG1 R/W bit1 bit0 Initial value 00011001B CG0 RESV R/W R/W RESV Reserved bit 1 must always be written to these bits. CG1 CG0 0 0 1 1 RST 0 1 SPL 0 1 SLP 0 1 0 1 0 1 CPU halt clock pulses selection bits 0 clock pulse (CPU clock = Peripheral clock) 9 clock pulses (CPU clock: Peripheral clock = 1: 3 to 4 approx.) 17 clock pulses (CPU clock: Peripheral clock = 1: 5 to 6 approx.) 33 clock pulses (CPU clock: Peripheral clock = 1: 9 to 10 approx.) Internal reset signal generation bit Generates an internal reset signal of 3 machine cycles. No change, no effect on operation Pin state setting bit (for timebase timer mode and stop mode) Retained High-impedance Sleep bit No change, no effect on operation Switch to sleep mode. Stop bit STP R/W: W: Read/write Write-only : Initial value PLL clock mode (MCS of CKSCR = 0) No change, no effect on operation Switch to timebase timer mode. Main clock mode (MCS of CKSCR = 1) No change, no effect on operation Switch to stop mode. 0 1 Figure 5.3-1 Configuration of the low power consumption mode control register (LPMCR) 98 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series Table 5.3-1 Function description of each bit of the low power consumption mode control register (LPMCR) Bit name Function * This bit indicates switching to timebase timer mode or stop * When "1" is written to this bit, a switch to timebase timer mode is performed if the PLL clock has been selected (MCS of CKSCR = 0) and a switch to stop mode is performed if the oscillation clock has been selected (MCS of CKSCR = 1). Even though 1 is written to the STP bit during the transition of clock selection, the MCS bit status determines whether timebase timer mode or stop mode is used. * Writing "0" to this bit has no effect on operation. * This bit is cleared to "0" by a reset or by release of the timebase timer or of the stop state. * The read value of this bit is always "0". mode. bit 7 STP: Stop bit bit 6 SLP: Sleep bit * * * * This bit indicates switching to sleep mode. When "1" is written to this bit, the mode switches to sleep mode. Writing "0" to this bit has no effect on operation. This bit is cleared to "0" by a reset or by release of sleep or stop mode. * If "1" is written to both the STP bit and SLP bit at the same time, the mode switches to timebase timer mode or stop mode. * The read value of this bit is always "0". * This bit is enabled while either timebase timer mode or stop bit 5 SPL: Pin state setting bit (for timebase timer mode and stop mode) * When this bit is "0", the level of the external pins is retained. * When this bit is "1", the status of the external pins changes to * This bit is initialized to "0" by a reset. * When "0" is written to this bit, an internal reset signal of 3 * Writing "1" to this bit has no effect on operation. * The read value of this bit is always "1". mode is in effect. bit 4 RST: Internal reset signal generation bit RESV: Reserved bit bit 3 * These bits set the number of CPU halt clock pulses for the CPU bit 2 bit 1 CG1, CG0: CPU halt clock pulses selection bits * The clock supplied to the CPU is stopped after the execution of * Selection can be made from among four different clock pulses. * These bits are initialized to "00B" by a power-on or watchdog timer reset. Other resets do not initialize these bits. intermittent operation function. bit 0 RESV: Reserved bit MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 99 s Access to the low power mode control register (LPMCR) Switching to low power consumption mode (including stop mode and sleep mode) is performed by writing to the low power mode control register (LPMCR). Only the instructions listed in Table 5.3-2 should be used for this purpose. If other instructions are used for switching to low power consumption mode, operation cannot be assured. To control functions other than switching to low power consumption mode, any instruction can be used. When word-length is used for writing to the low power consumption mode control register, even addresses must be used. Writing with odd addresses to switch to low power consumption mode may cause a malfunction. Table 5.3-2 Instructions to be used for switching to low power consumption mode MOV io,#imm8 MOV io,A MOV @RLi+disp8,A MOVW io,#imm16 MOVW io,A MOVW @RLi+disp8,A SETB io:bp MOV dir,#imm8 MOV dir,A MOV addr24,A MOVW dir,#imm16 MOVW dir,A MOVPW addr24,A SETB dir:bp MOV eam,#imm8 MOV addr,A MOVW eam,#imm16 MOVW addr16,A SETB addr16:bp MOV eam,Ri MOV eam,A MOVW eam,RWi MOVW eam,AA 100 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series Memo MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 101 5.4 CPU Intermittent Operation Mode CPU intermittent operation mode is used for intermittent operation of the CPU while peripheral functions continue to operate at high speed. Its purpose is to reduce power consumption. s CPU intermittent operation mode CPU intermittent operation mode halts the supply of the clock to the CPU for a certain period. The halt occurs after the execution of every instruction that accesses a register, internal memory (ROM and RAM), I/O, peripheral functions. and the external bus. Internal bus cycle activation is therefore delayed. While a steady rate of peripheral clock pulses are supplied to the peripheral functions, the rate of CPU execution is reduced, enabling processing with low power consumption. * * The CG1 and CG0 bits of the low power mode control register (LPMCR) are used to select the number of clock pulses per halt cycle of the clock supplied to the CPU. Instruction execution time in CPU intermittent mode can be calculated. A correction value should be obtained by multiplying the number of times instructions that access a register, internal memory and internal peripheral functions are executed by the number of clock pulses per halt cycle. Add this correction value to the normal execution time. Figure 5.4-1 shows the operating clock pulses during CPU intermittent operation mode. Peripheral clock CPU clock Halt cycle One instruction execution cycle Internal bus activation Figure 5.4-1 Clock pulses during CPU intermittent operation 102 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series 5.5 Standby Mode Standby mode includes the sleep (PLL sleep and main sleep), timebase timer, and stop modes. s Operating status during standby mode Table 5.5-1 summarizes the operating statuses during standby mode. Table 5.5-1 Operation statuses during standby mode Standby mode Condition for switch MCS = 0 SLP = 1 Active Main sleep mode MCS = 0 SLP = 1 MCS = 0 STP = 1 MCS = 0 STP = 1 MCS = 1 STP = 1 Stop Stop Hi-z MCS = 1 STP = 1 Active Hold Stop Stop (*1) Hi-z Reset Interrupt Active Active Oscillation Clock CPU Peripheral Pin Release event Sleep mode PLL sleep mode Timebase timer mode Timebase timer mode (SPL = 0) Timebase timer mode (SPL = 1) Stop mode (SPL = 0) Stop mode (SPL = 1) Inactive Hold Stop mode *1 Only the timebase timer is active. SPL:Pin state setting bit of low power consumption mode control register (LPMCR) SLP:Sleep bit of LPMCR STP:Timebase timer or stop bit of LPMCR MCS:Machine clock selection bit of clock selection register (CKSCR) Hi-z:High-impedance MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 103 5.5 Standby Mode 5.5.1 Sleep mode Sleep mode causes the CPU operating clock to stop while other peripheral functions continue to operate. When the low power mode control register (LPMCR) indicates a switch to sleep mode, a switch to PLL sleep mode occurs if PLL clock mode has been set. Alternatively, a switch to main sleep mode occurs if main clock mode has been set. s Switching to sleep mode Writing "1" to the SLP bit of LPMCR and "0" to the STP bit of LPMCR triggers a switch to sleep mode. At this time, if the MCS bit of the clock selection register (CKSCR) is "0", the microcontroller enters PLL sleep mode. If the MCS bit of CKSCR is "1", the microcontroller enters main sleep mode. 104 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series q Return to normal mode by an interrupt If an interrupt request of level 7 or higher is issued from a peripheral circuit during sleep mode, sleep mode is released. After release, the CPU handles the interrupt in normal manner. The CPU executes processing according to the settings of the I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If that interrupt is accepted, the CPU executes interrupt processing. If the interrupt is not accepted, the CPU resumes execution with the instruction that follows the instruction in which switching to sleep mode was specified. Figure 5.5-1 shows the release of sleep mode for an interrupt. Interrupt from a peripheral circuit Enable flag is set. Sleep mode is not released. INT occurs (IL smaller than 7) Sleep mode is not released. Execution of the next instruction Sleep mode is released. Execution of the next instruction Interrupt execution Figure 5.5-1 Release of sleep mode for an interrupt MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 105 RST pin Sleep mode Main clock PLL clock CPU clock CPU operation Inactive Oscillating Oscillating PLL clock Reset sequence Reset released. Execution Sleep mode released. Figure 5.5-2 Release of PLL sleep mode (by external reset) 106 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series Memo MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 107 5.5 Standby Mode 5.5.2 Timebase timer mode Timebase timer mode causes the microcontroller operation to stop except the source oscillation and the timebase timer. All functions other than timebase timer are deactivated. s Switching to timebase timer mode When "1" is written to the STP bit of the low power consumption mode control register (LPMCR) in PLL clock mode (MCS of CKSCR = 0), switching to timebase timer mode occurs. Also, in main clock mode (MCS of CKSCR = 1), writing "0" to the MCS bit of the clock selection register (CKSCR) and "1" to the STP bit of LPMCR triggers switching to timebase timer mode. q Data retention function In timebase timer mode, the contents of dedicated registers, such as accumulators and internal RAM, are retained. q Operation during an interrupt Writing "1" to the STP bit of LPMCR during an interrupt request does not trigger switching to timebase timer mode. q Status of pins Before switching to timebase timer mode, the SPL bit of LPMCR controls external I/O pins to either retain the pervious state or go to high-impedance. s Release of timebase timer mode The low power consumption control circuit is used to release timebase timer mode. Release is caused by input of a reset or an interrupt. If timebase timer mode is released by a reset, the microcontroller is placed in the reset state after its release from timebase timer mode. For return to normal mode from timebase timer mode, the low power consumption control circuit releases timebase timer mode. The microcontroller then enters the PLL clock oscillation stabilization wait state. If the PLL clock is not used, change the MCS bit of CKSCR to 1 with the instruction that is executed immediately after the reset or return from the interrupt. q Return to normal mode by a reset If timebase timer mode is released by a reset, the microcontroller is placed in the reset state after release from timebase timer mode. q Return to normal mode by an external reset Since an external reset does not initialize the MCS bit of the clock selection register (CKSCR) to 1, PLL clock mode remains selected (MCS of CKSCR = 0). If the reset period is shorter than the PLL clock oscillation stabilization wait period, the reset sequence proceeds using the main clock. Figure 5.5-3 shows the operation for return to normal mode from timebase timer mode triggered by an external reset. 108 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series RST pin Timebase timer mode Main clock PLL clock CPU clock CPU operation Inactive Oscillating Oscillation stabilization wait Oscillating PLL clock Main clock Reset sequence Execution Reset released. Timebase timer mode released Figure 5.5-3 Release of timebase timer mode (by an external reset) q Return to normal mode by an interrupt If an interrupt request of level 7 or higher is issued from a peripheral circuit in timebase timer mode (when IL2, IL1, and IL0 of the interrupt control register (ICR) are set to a value other than "111B"), the low power consumption control circuit releases timebase timer mode. After the release, the CPU handles the interrupt in a normal manner. The CPU executes processing according to the settings of the I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If the interrupt is accepted, the CPU executes interrupt processing. If the interrupt is not accepted, the CPU resumes execution with the instruction that follows the instruction in which switching to timebase timer mode was specified. MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 109 5.5 Standby Mode 5.5.3 Stop mode Stop mode causes the source oscillation to stop and deactivates all functions. It is therefore the most power saving mode while data is being retained. s Switching to stop mode When "1" is written to the STP bit of the low power consumption mode control register (LPMCR) is written in main clock mode (MCS of CKSCR = 1), switching to stop mode occurs. During PLL clock mode (MCS of CKSCR = 0), writing "1" to the MCS bit of the clock selection register (CKSCR) and writing "1" to the STP bit of LPMCR trigger switching to stop mode. q Data retention function In stop mode, the contents of dedicated registers, such as accumulators and internal RAM, are retained. q Operation during an interrupt Writing "1" to the STP bit of LPMCR during an interrupt request does not trigger switching to stop mode. q Pin state setting Before switching to stop mode, the SPL bit of LPMCR controls the external pins to either retain the pervious state or go to high-impedance. 110 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series s Release of stop mode The low power consumption control circuit is used release stop mode. The release is caused by input of a reset or by an interrupt. Because the oscillation of the operating clock is stopped before return to normal mode from stop mode, the low power consumption control circuit puts the microcontroller into the oscillation stabilization wait state, then releases stop mode. q Return to normal mode by a reset When stop mode is released by a reset cause, the microcontroller is placed in the oscillation stabilization wait and reset state after release from stop mode. The reset sequence proceeds after the oscillation stabilization wait interval has elapsed. q Return to normal mode by a interrupt If an interrupt request of level 7 or higher is issued from a peripheral circuit during stop mode (when IL2, IL1, and IL0 of the interrupt control register (ICR) are set to a value other than "111B"), the low power consumption control circuit releases stop mode. After release, the CPU handles the interrupt in a normal manner. However, the CPU starts after the main clock oscillation stabilization wait interval specified by the WS1 and WS0 bits of the clock selection register (CKSCR) has elapsed. The CPU executes processing according to the settings of the I flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If the interrupt is accepted, the CPU executes interrupt processing. If the interrupt is not accepted, the CPU resumes the execution with the instruction that follows the instruction in which switching to stop mode was specified. RST pin Stop mode Main clock PLL clock CPU clock CPU operation Inactive Oscillation stabilization wait Oscillating Inactive Main clock Reset sequence Execution Reset released. Stop mode released. Figure 5.5-4 Release of stop mode (by external reset) MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 111 5.6 Status Change Diagram Figure 5.6-1 shows the status change diagram of FMC-16LX operation and gives change conditions. s Status change diagram From all states Power-on Main clock mode Hardware standby state Power-on reset Source clock oscillation stabilization wait and reset state Main clock reset state Source clock oscillation stabilization wait state Stop state Main run state Main sleep state PLL cock mode PLL sleep state Timebase timer state PLL run state Main clock reset state PLL clock reset state Figure 5.6-1 Status change diagram 112 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series s Low power consumption mode operating states Table 5.6-1 lists the operating states of low power consumption mode. Table 5.6-1 Low power consumption mode operating states Low power consumption mode Main sleep PLL sleep Timebase timer (SPL = 0) Timebase timer (SPL = 1) Stop (SPL = 0) Stop (SPL = 1) Condition for transition MCS = 1 SLP = 1 MCS = 0 SLP = 1 MCS = 0 STP = 1 MCS = 0 STP = 1 MCS = 1 STP = 1 MCS = 1 STP = 1 Oscillation Release event Reset or interrupt Reset or interrupt Reset or interrupt Reset or interrupt Reset or interrupt Reset or interrupt Clock CPU Peripheral Pin Active Active Active Active Inactive Inactive Active Active Inactive Inactive Inactive Inactive Inactive Inactive Inactive Inactive Inactive Inactive Active Active Inactive Inactive Inactive Inactive Active Active Hold Hi-z Hold Hi-z q Clock mode switching and release (excluding standby mode) Table 5.6-2 lists clock mode switching and release. Table 5.6-2 Clock mode switching and release Transition After power-on, transition to the main run state Reset during main run state Transition from main run state to PLL run state Return to main run state from PLL run state Reset during PLL run state Conditions [1] Source clock oscillation stabilization wait interval ends. (Timebase timer output) [2] Reset input has been cleared. [3] External reset, software reset, or watchdog timer reset [4] [5] MCS = 0 (After PLL clock oscillation stabilization wait, switch to PLL clock) (*1) MCS = 1 (PLL clock deactivated) [6] External reset or software reset ([7] After reset, return to PLL run state) [8] Watch dog reset ([3] After reset, return to main run state) *1The microcontroller operates using the main clock during the PLL clock oscillation stabilization wait state. MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 113 q Switching to and release from standby mode Table 5.6-3 lists switching to and release from standby mode. Table 5.6-3 Switching to and release of standby mode Transition Transition to main sleep mode Release of main sleep mode Transition to stop mode Conditions [1] SLP = 1, MCS = 1 (Transition from main run state) [2] SLP =1, MCS = 1 (Transition from PLL run state) [3] Interrupt input [4] External reset [5] STP =1, MCS = 1 (Transition from main run state) [6] STP =1, MCS = 1 (Transition from PLL run state) [7] Interrupt input ([10] indicates return to main run state after oscillation stabilization wait.) [8] External reset ([9] indicates external reset during oscillation stabilization wait state.) <1>SLP = 1, MCS = 0 (Transition from PLL run state) <2>SLP = 1, MCS = 0 (Transition from main run state, switch to PLL clock after PLL clock oscillation stabilization wait) (*1) <3>Interrupt input <4>External reset <5>STP = 1, MCS = 0 (Transition from PLL run state) <6>STP = 1, MCS = 0 (Transition from main run state, switch to PLL clock after PLL clock oscillation stabilization wait) (*1) <7>Interrupt input(*1) <8>External reset (<9> After reset, return to PLL run state) (*1) Release of stop mode Transition to PLL sleep mode Release of PLL sleep mode Transition to timebase timer mode Release of timebase timer mode *1The microcontroller operates using the main clock during the PLL clock oscillation stabilization wait state. 114 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series 5.7 Status of Pins in Standby Mode and Reset The statues of pins in standby mode and reset are summarized below for each memory access mode. s Software pull-up resistor For pins with a pull-up resistor selected by software, the pull-up resistor is disconnected during "L" level output. s Status of pins in single-chip mode Table 5.7-1 lists the state of pins in single-chip mode. Table 5.7-1 State of pins in single-chip mode Standby mode Pin name Sleep SPL = 0 P00 to P07 P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P62 P10 to P16 P63 SPL = 1 Stop Reset The preceding status is retained. (*2) The preceding status is retained. (*2) Input shut off/output Hi-z (*3) Input disabled/ output Hi-z (*1) Input enabled (*1) *1"Input enabled" means that the input function is enabled. Select either the pull-up or the pulldown option. Alternatively, an external input is required. Pins used as output ports are the same as other ports. *2"The preceding status is retained" means that the status of the pin output existing immediately before switching to this mode is retained. Note that input is disabled if the preceding status was input. * "Status of the pin output is retained" means that the pin retains the value output from an operating internal peripheral unit or the value output from the port if the pin is used as a port. "Input disabled" means that the input to the pin is not accepted because the internal circuit is inactive, although operation of the input gate adjacent to the pin is enabled. * *3"Input shut off" indicates the state in which operation of the input gate adjacent to the pin is disabled. "Output Hi-z" means that the pin state is high-impedance because driving of the pin driving transistor is disabled. MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 115 5.8 Notes on Using Low Power Consumption Mode Note the following six items to use low power consumption mode: * Switching to standby mode and interrupts * Release of standby mode by an interrupt * Setting of standby mode * Release of stop mode * Release of timebase timer mode * Oscillation stabilization wait time s Notes on standby mode q Switching to standby mode and interrupts During an interrupt request to the CPU from a peripheral function, the CPU ignores the STP and SLP bits of the low power consumption mode control register (LPMCR) even though "1" has been written to these bits. Thus, switching to any standby mode is disabled (even after processing the interrupt is completed, there is no switch to standby mode). If the interrupt level is 7 or a higher priority, this action does not depend on whether the interrupt request is accepted by the CPU. However, during execution of interrupt processing by the CPU, if the interrupt request flag for the interrupt is cleared and no other interrupt requests have been issued, switching to standby mode can be done. q Release of standby mode caused by an interrupt If an interrupt request of interrupt level 7 or a higher priority is issued from a peripheral function during the sleep, timebase timer, or stop modes, the standby mode is released. This action does not depend on whether the CPU accepts that interrupt. After the release of standby mode, normal interrupt processing is performed. The CPU branches to the interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt level setting bits (IL2, IL1, and IL0 of ICR) is higher than the interrupt level mask register (ILM); and the interrupt enable flag (I) of the condition code register (CCR) is set to "1" (enabled). If the interrupt is not accepted, the CPU starts the execution with the instruction that follows the instruction in which switching to standby mode was specified. When interrupt processing is executed normally, the CPU first executes the instruction that follows the instruction in which switching to standby mode was specified. The CPU then proceeds to interrupt processing. Depending on the condition when switching to standby mode was performed, however, the CPU may proceed to interrupt processing before executing the next instruction. If the CPU should not branch to the interrupt processing routine immediately on return to normal mode from standby mode, action must be taken to disable interrupts before standby mode is set. q Setting of standby mode When "1" is written to the STP bit and SLP bit of LPMCR at the same time, switching to standby mode is performed. If the MCS bit of the clock selection register (CKSCR) is "0", switching to timebase timer mode is performed; if this bit is 1, switching to stop mode is performed. 116 CHAPTER 5 LOW POWER CONSUMPTION MODE MB90560 series s Release of stop mode If an external interrupt is used to release stop mode, the input request level must be "H". Do not use an "L" level request because it may cause a malfunction. Edge requests do not result in a return from the standby state in a mode in which the clock has stopped. s Release of timebase timer mode When timebase timer mode is released, the microcontroller is placed in the PLL clock oscillation stabilization wait state. If the PLL clock is not used, change the MCS bit of the clock selection register (CKSCR) to "1" with the instruction that is to be executed immediately after a reset or on return from an interrupt. If an external interrupt is used to release timebase timer mode, the input request level must be "H". An "L" level request may cause a malfunction. Edge requests do not result in a return from the standby state in a mode in which the clock has stopped. s Oscillation stabilization wait interval q Source clock oscillation stabilization wait interval Because the oscillator for source oscillation is halted in stop mode, an oscillation stabilization wait interval is required. A time period selected by the WS1 and WS0 bits of CKSCR is used as the oscillation stabilization wait interval. q PLL clock oscillation stabilization wait interval The CPU may be working with the main clock and the PLL clock may be stopped. If the microcontroller will enter a mode in which the CPU and peripheral functions work with the PLL clock, the PLL clock initially enters the oscillation stabilization wait state. In this state, the CPU still operates using the main clock. The PLL clock oscillation stabilization wait interval is fixed at 2 13/HCLK (HCLK: oscillation clock frequency). However, this interval may range from 2 3/HCLK to 3 x 213/HCLK depending on the status of the timebase timer, if the timebase timer is not cleared before the PLL clock oscillation stabilization wait state is entered. (For example, return to the PLL run state from timebase timer mode occurs because of an external reset.) MB90560 series CHAPTER 5 LOW POWER CONSUMPTION MODE 117 CHAPTER 6 INTERRUPTS This chapter explains the interrupts and extended intelligent I/O service (EI2OS) in the MB90560 series. 6.1 Interrupts ........................................................................................ 120 6.2 Interrupt Causes and Interrupt Vectors .......................................... 122 6.3 Interrupt Control Registers and Peripheral Functions .................... 124 6.4 Hardware Interrupts........................................................................ 132 6.5 Software Interrupts ......................................................................... 144 6.6 Interrupt of Extended Intelligent I/O Service (EIOS) ..................... 146 6.7 Operation of the extended intelligent I/O service (EIOS) .............. 154 6.8 Exception Processing Interrupt ...................................................... 158 6.9 Stack Operations for Interrupt Processing ..................................... 160 6.10 Sample Programs for Interrupt Processing .................................... 162 6.1 Interrupts This chapter explains the interrupts and extended intelligent I/O service (EI2OS) in the MB90560 series. * Hardware interrupts * Software interrupts * Interrupts from extended intelligent I/O service (EI2OS) * Exception processing s Interrupt types and functions q Hardware interrupt A hardware interrupt transfers control to a user-defined interrupt processing program in response to an interrupt request from a peripheral function. q Software interrupt A software interrupt transfers control to a user-defined interrupt processing program triggered by the execution of a dedicated software interrupt instruction (such as the INT instruction). q Interrupt from extended intelligent I/O service (EI2OS) The EI2OS function automatically transfers data between a peripheral function and memory. Data transfer, which has ordinarily been executed by an interrupt processing program, can be handled like a direct memory access (DMA). When the specified number of data transfers has been terminated, the interrupt processing program is automatically executed. An instruction from EI2OS is a type of hardware interrupt. q Exception processing Exception processing is basically the same as an interrupt. When an exception event (execution of an undefined instruction) is detected on the instruction boundary, ordinary processing is interrupted and exception processing is performed. This is equivalent to software interrupt instruction INT10. 120 CHAPTER 6 INTERRUPTS MB90560 series s Interrupt operation Figure 6.1-1 shows the activation and return processing for the four types of interrupt functions. Main program Is there a valid hardware interrupt String type (*1) request? instruction being executed Fetch the next instruction and decode Interrupt activation/return processing EI2OS? EI2OS INT instruction? Software interrupt/ exception processing Save the dedicated register on the system stack Disable acceptance of hardware interrupts (I = 0) Hardware EI2OS processing Interrupt Specified count terminated? Alternatively, is there an end request from the peripheral function? Save the dedicated register on the system stack Update the CPU interrupt processing level (ILM) RETI instruction? Return processing Return the dedicated register from the system stack, call the interrupt routine, and return to the previous routine Read the interrupt vector, update PC and PCB, and branch to the interrupt routine Execute ordinary instruction Repetition of string type (*1) instruction completed? Move the pointer to the next instruction by PC update *1 When a string type instruction is being executed, the interrupt is evaluated in each step. Figure 6.1-1 Overall flow of interrupt operation MB90560 series CHAPTER 6 INTERRUPTS 121 6.2 Interrupt Causes and Interrupt Vectors The F2MC-16LX can handle 256 types of interrupt causes. The 256 interrupt vector tables are allocated to the memory at the highest addresses. These interrupt vectors are shared by all interrupts. Software interrupts can use all these interrupt vectors (INT0 to INT256). Software interrupts share some interrupt vectors with the hardware interrupts and exception processing interrupts. Hardware interrupts used a fixed interrupt vector and interrupt control register (ICR) for each peripheral function. s Interrupt vectors Interrupt vector tables referenced during interrupt processing are allocated to the highest addresses in the memory area ("FFFC00H" to "FFFFFFH"). Interrupt vectors share the same area with EI2OS, exception processing, hardware, and software interrupts. Table 6.2-1 shows the assignment of interrupt numbers and interrupt vectors. Table 6.2-1 Interrupt vectors Software interrupt instruction INT0 : INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 : INT254 INT255 Vector address L FFFFFCH : FFFFE0H FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H : FFFC04H FFFC00H Vector address M FFFFFDH : FFFFE1H FFFFDDH FFFFD9H FFFFD5H FFFFD1H FFFFCDH FFFFC9H FFFFC5H : FFFC05H FFFC01H Vector address H FFFFFEH : FFFFE2H FFFFDEH FFFFDAH FFFFD6H FFFFD2H FFFFCEH FFFFCAH FFFFC6H : FFFC06H FFFC02H Mode data Not used : Not used FFFFDFH Not used Not used Not used Not used Not used Not used : Not used Not used Interrupt No. #0 : #7 #8 #9 #10 #11 #12 #13 #14 : #254 #255 Hardware interrupt None : None (RESET vector) None Reference Unused interrupt vectors should be set as the exception processing address. 122 CHAPTER 6 INTERRUPTS MB90560 series s Interrupt causes and interrupt vectors/interrupt control registers Table 6.2-2 shows the relationship between interrupt causes (excluding software interrupts), interrupt vectors, and interrupt control registers. Table 6.2-2 Interrupt causes, interrupt vectors, and interrupt control registers EI2OS support x x x o x o x o x #08 #09 #10 #11 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 Interrupt vector Number Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt cause Interrupt control register ICR ICR00 ICR01 Priority (*2) High Address 0000B0H 0000B1H(*1) Reset INT9 instruction Exception processing A/D converter conversion termination Output compare channel 0 match 8/16-bit PPG timer 0 counter borrow Output compare channel 1 match 8/16-bit PPG timer 1 counter borrow Output compare channel 2 match 8/16-bit PPG timer 2 counter borrow Output compare channel 3 match 8/16-bit PPG timer 3 counter borrow Output compare channel 4 match 8/16-bit PPG timer 4 counter borrow Output compare channel 5 match 8/16-bit PPG timer 5 counter borrow DTP/external interrupt channels 0/1 detection DTP/external interrupt channels 2/3 detection DTP/external interrupt channels 4/5 detection DTP/external interrupt channels 6/7 detection 8-bit timer 0/1/2 counter borrow 16-bit reload timer 0 underflow 16-bit free-running timer overflow 16-bit reload timer 1 underflow Input capture channels 0/1 16-bit free-running timer clear Input capture channels 2/3 Timebase timer UART1 receive UART1 send UART0 receive UART0 send Flash memory status Delayed interrupt generator module 08H 09H 0AH 0BH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH ICR02 0000B2H(*1) ICR03 0000B3H(*1) ICR04 0000B4H(*1) ICR05 0000B5H(*2) ICR06 0000B6H(*1) ICR07 0000B7H(*1) ICR08 0000B8H(*1) ICR09 0000B9H(*1) ICR10 0000BAH(*1) ICR11 0000BBH(*1) x x x ICR12 0000BCH(*1) ICR13 0000BDH(*1) ICR14 0000BEH(*1) ICR15 0000BFH(*1) Low o:Can be used. x:Cannot be used. if used with the EI2OS stop function. :Usable when an interrupt cause that shares the ICR is not used. *1- For peripheral functions that share the ICR register, the interrupt level will be the same. If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register with another peripheral function, the service can be used only for one of the functions. If the extended intelligent I/O service is specified for a peripheral function that shares the ICR register with another peripheral function, interrupts are disabled for the other peripheral function sharing the ICR register.*1 *2 This priority is applied when interrupts of the same level occur simultaneously. :Usable MB90560 series CHAPTER 6 INTERRUPTS 123 6.3 Interrupt Control Registers and Peripheral Functions Interrupt control registers (ICR00 to ICR15) are located inside the interrupt controller. The interrupt control registers correspond to all peripheral functions that have the interrupt function. These registers control interrupts and the extended intelligent I/O service (EI2OS). s Interrupt control registers Table 6.3-1 lists the interrupt control registers and corresponding peripheral functions. Table 6.3-1 Interrupt control registers Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H Register Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Abbreviation ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Corresponding peripheral function A/D converter Output compare 0, 8/16-bit PPG timer 0 Output compare 1, 8/16-bit PPG timer 1 Output compare 2, 8/16-bit PPG timer 2 Output compare 3, 8/16-bit PPG timer 3 Output compare 4, 8/16-bit PPG timer 4 Output compare 5, 8/16-bit PPG timer 5 DTP/external interrupts 0, 1, 2, 3 DTP/external interrupts 4, 5, 6, 7 8-bit timers 0, 1, 2, 16-bit reload timer 0 16-bit free-run timer overflow, 16-bit reload timer 1 Input capture 0, 1, 16-bit free-run timer clear Input capture 2, 3, timebase timer UART1 UART0 Flash memory, delayed interrupt generator module 0000BAH Interrupt control register 10 0000BBH Interrupt control register 11 0000BCH Interrupt control register 12 0000BDH Interrupt control register 13 0000BEH Interrupt control register 14 0000BFH Interrupt control register 15 s Interrupt control register functions All interrupt control registers (ICR) do the following: * * * * Set the interrupt level of the corresponding peripheral function. Select ordinary interrupts or the extended intelligent I/O service as interrupts of the corresponding peripheral function. Select an extended intelligent I/O service (EI2OS) channel Display the status of the extended intelligent I/O service (EI2OS) Some of the functions of the interrupt control registers (ICR) differ during writing and reading, as shown in Figures 6.3-1 and 6.3-2. 124 Memo MB90560 series CHAPTER 6 INTERRUPTS 125 6.3 Interrupt Control Registers and Peripheral Functions 6.3.1 Interrupt control registers (ICR00 to ICR15) Interrupt control registers correspond to all peripheral functions that have the interrupt function. The interrupt control registers control the processing when an interrupt request occurs. The functions of these registers partially differ at writing and reading. s Interrupt control registers (ICR00 to ICR15) During writing ICR bit7 Address 0000B0H to 0000BFH ICS3 W bit6 ICS2 W bit5 ICS1 W bit4 ICS0 W bit3 ISE R/W bit2 IL2 R/W bit1 IL1 R/W bit0 IL0 R/W Initial value 00000111B IL2 0 0 0 0 1 1 1 1 ISE 0 1 IL1 0 0 1 1 0 0 1 1 IL0 0 1 0 1 0 1 0 1 Interrupt level setting bit Interrupt level 0 (highest) Interrupt level 7 (no interrupt) EI2OS enable bit Activates the interrupt sequence when an interrupt occurs Activates EI2OS when an interrupt occurs EI2OS channel selection bit Channel Descriptor address 000100H 000108H 000110H 000118H 000120H 000128H 000130H 000138H 000140H 000148H 000150H 000158H 000160H 000168H 000170H 000178H ICS3 ICS2 ICS1 ICS0 0 0 0 0 0 0 0 0 1 1 1 1 1 R/W: W: Read/write Write-only : Initial value 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 6.3-1 Interrupt control registers (ICR00 to ICR15) during writing 126 CHAPTER 6 INTERRUPTS MB90560 series During reading ICR bit7 Address 0000B0H to 0000BFH bit6 bit5 S1 R bit4 S0 R bit3 ISE R/W bit2 IL2 R/W bit1 IL1 R/W bit0 IL0 R/W Initial value XX000111B IL2 0 0 0 0 1 1 1 1 ISE 0 1 S1 R/W: Read/write R: Write-only - : Not used X: Undefined : Initial value 0 0 1 1 IL1 0 0 1 1 0 0 1 1 IL0 0 1 0 1 0 1 0 1 Interrupt level setting bit Interrupt level 0 (highest) Interrupt level 7 (no interrupt) EI2OS enable bit Activates the interrupt sequence when an interrupt occurs Activates EI2OS when an interrupt occurs S0 0 1 0 1 EI2OS status EI2OS operation in progress or EI2OS not activated Stopped status due to count termination Reserved Stopped status due to a request from the peripheral function Figure 6.3-2 Interrupt control registers (ICR00 to ICR15) during reading MB90560 series CHAPTER 6 INTERRUPTS 127 6.3 Interrupt Control Registers and Peripheral Functions 6.3.2 Interrupt control register functions The interrupt control registers (ICR00 to ICR15) consist of the following four functional bits: * Interrupt level setting bits (IL2 to IL0) * Extended intelligent I/O service (EI2OS) enable bit (ISE) * Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0) * Extended intelligent I/O service (EI2OS) status (S1 to S0) s Configuration of interrupt control registers (ICR) Figure 6.3-3 shows the configuration of the interrupt control register (ICR) bits. Writing to interrupt control register (ICR) Address 0000B0H to 0000BFH Reading of interrupt control register (ICR) Address 0000B0H to 0000BFH R: Read-only W: Write-only - : Not used Initial value Initial value Figure 6.3-3 Configuration of interrupt control registers (ICR) Reference * The ICS3 to ICS0 bits are valid only when the extended intelligent I/O service (EI2OS) has been activated. To activate EI2OS, set the ISE bit to 1. To not activate EI2OS, set the ISE bit to 0. When EI2OS is not activated, setting ICS3 to ICS0 is optional. ICS1 and ICS0 are valid only for writing. S1 and S0 are valid only for reading. * s Interrupt control register functions q Interrupt level setting bits (IL2 to IL0) These bits set the interrupt level of the corresponding peripheral function. These bits are initialized to level 7 (no interrupts) by a reset. Table 6.3-2 shows the correspondence between the interrupt level setting bits and interrupt levels. 128 CHAPTER 6 INTERRUPTS MB90560 series Table 6.3-2 Correspondence between the interrupt level setting bits and interrupt levels IL2 0 0 0 0 1 1 1 1 IL1 0 0 1 1 0 0 1 1 IL0 0 1 0 1 0 1 0 1 Interrupt level 0 (highest priority) 6 (lowest priority) 7 (no interrupts) q Extended intelligent I/O service (EI2OS) enable bit (ISE) If this bit is "1" when an interrupt request is generated, EI 2OS is activated. If this bit is "0" when an interrupt request is generated, the interrupt sequence is activated. When the EI2OS termination condition is met (when the S1 and S0 bits are not 00B), the ISE bit is cleared. If the corresponding peripheral function does not have the EI2OS function, the ISE bit must be set to "0" by software. The ISE bit is initialized to "0" by a reset. q Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0) These write-only bits specify the EI2OS channel. The EI2OS descriptor address is determined based on the value set here. The ICS bit is initialized to "0000B"by a reset. Table 6.3-3 shows the correspondence between the EI2OS channel selection bits and descriptor addresses. Table 6.3-3 Correspondence between the EI2OS channel selection bits and descriptor addresses ICS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ICS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ICS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ICS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selected channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Descriptor address 000100H 000108H 000110H 000118H 000120H 000128H 000130H 000138H 000140H 000148H 000150H 000158H 000160H 000168H 000170H 000178H MB90560 series CHAPTER 6 INTERRUPTS 129 q Extended intelligent I/O service (EI2OS) status bits (S1, S0) These are read-only bits. When this value is checked at EI2OS termination, the operating status and termination status can be distinguished. These bits are initialized to "00B" by a reset. Table 6.3-4 shows the relationship between the S0 and S1 bits and the EI 2OS status Table 6.3-4 Relationship between EI2OS status bits and the EI2OS status S1 0 0 1 1 S0 0 1 0 1 EI2OS status EI2OS operation in progress or EI2OS not activated Stopped status due to count termination Reserved Stopped status due to a request from the peripheral function 130 CHAPTER 6 INTERRUPTS MB90560 series Memo MB90560 series CHAPTER 6 INTERRUPTS 131 6.4 Hardware Interrupts The hardware interrupt function temporarily interrupts the program being executed by the CPU and transfers control to a user-defined interrupt processing program in response to an interrupt signal from a peripheral function. The extended intelligent I/O service (EI2OS) and external interrupts are executed as a type of hardware interrupt. s Hardware interrupts q Hardware interrupt function The hardware interrupt function compares the interrupt level of the interrupt request signal output by a peripheral function with the interrupt level mask register (ILM) in the CPU processor status (PS). The function then references the contents of the I flag in the processor status (PS) through the hardware and decides if the interrupt can be accepted. When the hardware interrupt is accepted, the CPU internal registers are automatically saved on the system stack. The currently requested interrupt level is stored in the interrupt level mask register (ILM), and the function branches to the corresponding interrupt vector. q Multiple interrupts Multiple hardware interrupts can be activated. q Extended intelligent I/O service (EI2OS) EI2OS is an automatic transfer function between memory and I/O. When the specified transfer count has been completed, a hardware interrupt is activated. Multiple EI2OS activation is not possible to occur. During EI2OS processing, all other interrupt requests and EI2OS requests are held. q External interrupt An external interrupt (including wake-up interrupts) is accepted from a peripheral function (interrupt request detection circuit) as a hardware interrupt. q Interrupt vector Interrupt vector tables referenced during interrupt processing are allocated to memory at "FFFC00H" to "FFFFFFH". These tables are shared by software interrupts. See Section 6.2, "Interrupt causes and Interrupt Vectors," for more information about the allocation of interrupt numbers and interrupt vectors. 132 CHAPTER 6 INTERRUPTS MB90560 series s Hardware interrupt structure Table 6.4-1 lists four mechanisms used for hardware interrupts. These four mechanisms must be included in the program before hardware interrupts can be used. Table 6.4-1 Mechanisms used for hardware interrupts Mechanism Peripheral function Interrupt controller Interrupt enable bit, interrupt request bit Interrupt control register (ICR) Interrupt enable flag (I) CPU Interrupt level mask register (ILM) Microcode "FFFC00H" to "FFFFFFH" Interrupt vector table in memory Function Controls interrupt requests from a peripheral function Sets the interrupt level and controls EI2OS Identifies the interrupt enable status Compares the request interrupt level and current interrupt level Executes the interrupt processing routine Stores the branch destination address for interrupt processing MB90560 series CHAPTER 6 INTERRUPTS 133 s Hardware interrupt suppression Acceptance of hardware interrupt requests is suppressed under the following conditions. q Hardware interrupt suppression during writing to the peripheral function control register area When data is being written to the peripheral function control register area, hardware interrupt requests are not accepted. This prevents the CPU from making operational mistakes. The mistakes may be caused if an interrupt request is generated during data is being written to the interrupt control registers for a resource. The peripheral function control register area is not the I/ O addressing area at "000000H" to "0000FFH", but the area allocated to the control register of the peripheral function control register and data register. Figure 6.4-1 shows hardware interrupt operation during writing to the built-in peripheral area Instruction that writes to the peripheral function control register area ..... MOV A, #08 MOV io,A MOV A,2000H Does not branch to the interrupt Interrupt processing An interrupt request is generated here Branches to the interrupt Figure 6.4-1 Hardware interrupt request while writing to the peripheral function control register area q Hardware interrupt suppression by interrupt suppression instruction The ten types of hardware interrupt suppression instructions listed in Table 6.4-2 ignore interrupt requests without detecting whether a hardware interrupt request exists. Table 6.4-2 Hardware interrupt suppression instruction Prefix code PCB DTB ADB SPB CMR NCC Interrupts/hold suppression instructions (instructions that delay the effect of the prefix code) MOV OR AND POPW ILM, #imm8 CCR, #imm8 CCR, #imm8 PS Instructions that do not accept interrupts and hold requests Even if a valid hardware interrupt request is generated during execution of one of these instructions, the interrupt is not processed until the first time an instruction of a different type is executed. q Hardware interrupt suppression during execution of software interrupt When a software interrupt is activated, the I flag is cleared to "0". In this state, other interrupt requests cannot be accepted. 134 CHAPTER 6 INTERRUPTS MB90560 series Memo MB90560 series CHAPTER 6 INTERRUPTS 135 6.4 Hardware Interrupts 6.4.1 Operation of hardware interrupts This section explains hardware interrupt operation from generation of a hardware interrupt request to the completion of interrupt processing. s Hardware interrupt activation q Peripheral function operation (generation of an interrupt request) A peripheral function that has a hardware interrupt request function also has an interrupt request flag that indicates the presence of interrupt requests and an interrupt enable flag that determines whether CPU interrupt requests are enabled or disabled. The interrupt request flag is set when an event specified by the peripheral function occurs. q Interrupt controller operation (interrupt request control) When two or more interrupt requests are received at the same time, the interrupt controller compares their interrupt levels (IL) in their interrupt requests register. The interrupt controller selects the request with the highest level (with the smallest IL value) and posts it to the CPU. When multiple requests have the same level, the request with the smallest interrupt number has the highest priority. q CPU operation (interrupt request acceptance and interrupt processing) The CPU compares the received interrupt level (ICR: IL2 to IL0) and the interrupt level mask register (ILM). If IL < ILM and interrupts are enabled (PS: CCR: I = 1), the CPU activates the interrupt processing microcode after the instruction currently being executed terminates. At the beginning of the interrupt processing microcode, the CPU checks the ISE bit in the interrupt control register (ICR). If ISE = 0, the CPU continues the execution of interrupt processing. (If ISE = 1, EI2OS is activated.) Interrupt processing saves the contents of the dedicated registers (12 bytes including A, DPR, ADB, DTB, PCB, PC, and PS) on the system stack (the system stack space indicated by the SSB and SSP). The CPU then loads data into the interrupt vector program counters (PCB and PC), updates the ILM, and sets the stack flag (S) (sets CCR: S = 1 and activates the system stack). s Returning from a hardware interrupt In an interrupt processing program, when the interrupt request flag of the peripheral function that generated the interrupt cause is cleared and the RETI instruction is executed, 12-byte data saved on the system stack is restored to the dedicated registers and the processing that was being executed before branching for the interrupt is resumed. When the interrupt request flag is cleared, interrupt requests output by the peripheral function to the interrupt controller are automatically canceled. 136 CHAPTER 6 INTERRUPTS MB90560 series s Hardware interrupt operation Figure 6.4-2 shows hardware interrupt operation from generation of a hardware interrupt to the completion of interrupt processing. Internal bus Microcode Check Comparator Other peripheral functions Peripheral function that generated the interrupt request Enable FF Factor FF Level comparator Interrupt level IL Interrupt controller IL: PS: I: ILM: IR: FF: Interrupt level setting bit in the interrupt control register (ICR) Processor status Interrupt enable flag Interrupt level mask register Instruction register Flip-flop Figure 6.4-2 Hardware interrupt operation (1) An interrupt cause is generated by the peripheral function. (2) The interrupt enable bit of the peripheral function is checked. If the interrupt is enabled, the interrupt request is sent from the peripheral function to the interrupt controller. (3) The interrupt controller determines the priority of simultaneous interrupt requests, then transfers the interrupt level (IL) that matches the corresponding interrupt request to the CPU. (4) The CPU compares the interrupt level (IL) requested by the interrupt controller with the interrupt level mask register (ILM). (5) If the comparison indicates a higher priority than the current interrupt processing level, the CPU checks the contents of the I flag in the condition code register (CCR). (6) If in the check in (5) shows that the I flag is interrupt enabled (I = 1), the CPU waits until the execution of the instruction currently being executed terminates. At termination, the CPU sets the requested level (IL) in the ILM. (7) Registers are saved, and processing branches to the interrupt processing routine. (8) The interrupt cause that was generated in (1) is cleared by software in the interrupt processing routine. Execution of the RETI instruction terminates the interrupt processing. MB90560 series CHAPTER 6 INTERRUPTS 137 6.4 Hardware Interrupts 6.4.2 Processing for interrupt operation When an interrupt request is generated by the peripheral function, the interrupt controller transmits the interrupt level to the CPU. If the CPU is able to accept interrupts, the interrupt controller temporarily interrupts the instruction currently being executed. The interrupt controller then executes the interrupt processing routine or activates the extended intelligent I/O service (EI2OS). If a software interrupt is generated by the INT instruction, the interrupt processing routine is executed regardless of the CPU status. In this case, hardware interrupts are not allowed. s Processing for interrupt operation Figure 6.4-3 shows the flow of processing for interrupt operation. START Main program YES I&IF&IF=1 AND LM>IL Interrupt activation/return processing String type (*1) instruction in progress Fetch the next instruction and deode ISE = 1 YES EI2OS EI2OS processing YES INT instruction? Software interrupt/exception processing NO NO Save the dedicated registers to the system stack Hardware instruction YES I <- 0 (Disable hardware interrupts) Save the dedicated registers to the system stack Specified count terminated? Alternatively, is there a termination request from the peripheral function? NO ILM <- IL (Transfer the interrupt level of the accepted interrupt request to the ILM) RETI instruction? YES Return processing Return the dedicated registers from the system stack, call the interrupt routine, and return to the previous routine S <- 1 (Activates the system stack) NO Execute ordinary instruction (including interrupt processing) PCB, PC <- interrupt vector (Branch to the interrupt processing routine) NO Repetition of string type (*1) instruction completed? YES Move the pointer to the next instruction by PC update *1 When a string type instruction is being executed, the interrupt is evaluated in each step. I: Interrupt enable flag of the condition code register (CCR) S: Stack flag of the condition code register (CCR) IF: Interrupt request flag of the peripheral function PCB: Program bank register IE: Interrupt enable flag of the peripheral function PC: Program counter: ILM: Interrupt level mask register (in the PS) ISE: EIOS enbale flag ofthe interruptor control register (ICR) IL: Interrupt level setting bit of the interrupt control register (ICR) 138 Figure 6.4-3 Flow of interrupt processing CHAPTER 6 INTERRUPTS MB90560 series 6.4 Hardware Interrupts 6.4.3 Procedure for using hardware interrupts Before hardware interrupts can be used, the system stack area, peripheral function, and interrupt control register (ICR) must be set. s Procedure for using hardware interrupts Figure 6.4-4 shows an example of the procedure for using hardware interrupts. Start (1) Set the system stack area Initialize the peripheral function Interrupt processing program (2) (3) Set the ICR in the interrupt controller Stack processing branches to the interrupt vector (7) (8) Processing for interrupt to the peripheral function (execute the interrupt processing routine) (4) Set operation start for the peripheral function. Set the interrupt enable bit to enable Hardware processing (9) Clear the interrupt cause (5) Set the ILM and I in the PS (10) Interrupt return instruction (RETI) Main program (6) Interrupt request generated Main program Figure 6.4-4 Procedure for using hardware interrupts (1) Set the system stack area. (2) Initialize a peripheral function that can generate interrupt requests. (3 Set the interrupt control register (ICR) in the interrupt controller. (4) Set the peripheral function to the operation start status, and set the interrupt enable bit to enable. (5) Set the interrupt level mask register (ILM) and interrupt enable flag (I) to interrupt acceptable. (6) An interrupt generated in the peripheral function causes a hardware interrupt request. (7) The interrupt processing hardware saves the registers and branches to the interrupt processing program. (8) The interrupt processing program processes the peripheral function in response to the generated interrupt. (9) Clear the peripheral function interrupt request. (10) Execute the interrupt return instruction, and return to the program location before branching. MB90560 series CHAPTER 6 INTERRUPTS 139 6.4 Hardware Interrupts 6.4.4 Multiple interrupts Multiple hardware interrupts can be implemented by setting different interrupt levels in the interrupt level setting bits (IL0, IL1, IL2) of the interrupt control register (ICR) in response to multiple interrupt requests from peripheral functions. Use of multiple interrupts, however, is not possible with the extended intelligent I/O service. s Multiple interrupts q Operation of multiple interrupts During execution of an interrupt processing routine, if an interrupt request with a higher-priority interrupt level is generated, the current interrupt processing is interrupted and the interrupt request with the higher-priority interrupt level is accepted. When the interrupt request with the higher-priority interrupt level terminates, the CPU returns to the previous interrupt processing. 0 to 7 can be set as the interrupt level. If level 7 is set, the CPU does not accept interrupt requests. During execution of interrupt processing, if an interrupt request with the same or lower-priority interrupt level is generated, the new interrupt request is held until the current interrupt terminates unless the I flag or ILM is changed. Other multiple interrupts to be activated during an interrupt can be temporarily disabled by setting the I flag in the condition code register (CCR) in the interrupt processing routine to interrupts not allowed (CCR: I = 0) or the interrupt level mask register (ILM) to interrupts not allowed (ILM = 000). 140 CHAPTER 6 INTERRUPTS MB90560 series Main program A/D interrupt processing Interrupt level 2 (ILM = 010) Timer interrupt processing Interrupt level 1 (ILM = 001) Peripheral initialization A/D interrupt generated Interrupted Restart Main processing restarts A/D interrupt processing Timer interrupt generated Timer interrupt processing Timer interrupt return A/D interrupt return Figure 6.4-5 Example of multiple interrupts r A/D interrupt generated When the A/D converter interrupt processing starts, the interrupt level mask register (ILM) automatically has the same value (2 in the example) as the A/D converter interrupt level (ICR: IL2 to IL0). If a level-1 or level-0 interrupt request is generated, this interrupt processing has priority. r Interrupt processing terminated When the interrupt processing terminates and the return instruction (RETI) is executed, the values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC, and PS) are returned from the stack, and the interrupt level mask register (ILM) has the value that it had before the interrupt. MB90560 series CHAPTER 6 INTERRUPTS 141 6.4 Hardware Interrupts 6.4.5 Hardware interrupt processing time From the occurrence of a hardware interrupt request to the execution of an interrupt processing routine, the time for the instruction currently being executed to terminate and the time required to handle an interrupt are necessary. s Hardware interrupt processing time From the occurrence of a hardware interrupt request to the acceptance of the interrupt and to the execution of an interrupt processing routine, the time to wait for sampling for an interrupt request and the time required to handle an interrupt (time to prepare for interrupt processing) are necessary. Figure 6.4-6 shows the interrupt processing time. CPU operation Ordinary instruction execution Interrupt request sampling wait time Interrupt handling Interrupt processing routine Interrupt wait time Interrupt handling time ( machine cycle) (*1) Interrupt request generation : The final instruction cycle samples the interrupt request here. : One machine cycle corresponds to one machine clock (). Figure 6.4-6 Interrupt processing time q Interrupt request sampling wait time The interrupt request sampling wait time is the time from the occurrence of and interrupt request to the termination of the instruction currently being executed. Whether an interrupt request has been occurred is determined by sampling the instruction for an interrupt request in the final cycle of the instruction. Consequently, the CPU cannot identify an interrupt request during execution of each instruction creating a delay. 142 CHAPTER 6 INTERRUPTS MB90560 series q Interrupt handling time ( machine cycle) The CPU saves dedicated registers to the system stack and fetches interrupt vectors after it receives an interrupt request. The required handling time for this processing is machine cycles. The interrupt handling time is calculated with the following formula: When an interrupt is activated: = 24 + 6 + Z machine cycles When returning from an interrupt: = 11 + 6 + Z machine cycles (RETI instruction) The interrupt handling time is different depending on each address pointed to by the stack pointer. Table 6.4-3 shows the compensation values (Z) for the interrupt handling time. Table 6.4-3 Compensation values (Z) for the interrupt handling time Address pointed to by the stack pointer External 8-bit External even-numbered address External odd-numbered address Internal even-numbered address Internal odd-numbered address Compensation value (Z) +4 +1 +4 0 +2 MB90560 series CHAPTER 6 INTERRUPTS 143 6.5 Software Interrupts When the software interrupt instruction (INT instruction) is executed, the software interrupt function transfers control from the program being executed by the CPU to the user-defined interrupt processing program. Hardware interrupts are disabled during execution of a software interrupt. s Software interrupt activation q Software interrupt activation The INT instruction is used to activate a software interrupt. There is no interrupt request flag or enable flag for software interrupt requests. When the INT instruction is executed, an interrupt request is always generated. q Hardware interrupt suppression Since the INT instruction does not have interrupt levels, the interrupt level mask register (ILM) is not updated. During the execution of the INT instruction, the I flag of the condition code register (CCR) is set to "0", and hardware interrupts are masked. To enable hardware interrupts during software interrupt processing, set the I flag to "1" in the software interrupt processing routine. q Software interrupt operation When the CPU fetches the INT instruction, the software interrupt processing microcode is activated. This microcode saves the internal CPU registers on the system stack, masks hardware interrupts (CCR: I = 0), and branches to the corresponding interrupt vector. 144 CHAPTER 6 INTERRUPTS MB90560 series s Software interrupt operation Figure 6.5-1 shows software interrupt operation from the occurrence of a software interrupt to the completion of interrupt processing. Internal bus Microcode Queue Fetch PS: I: S: IR: Processor status Interrupt enable flag Stack flag Instruction register Figure 6.5-1 Software interrupt operation (1)A software interrupt instruction is executed. (2)The dedicated registers are saved according to the microcode that corresponds to the software interrupt instruction, and other necessary processing is performed. Branch processing is then executed. (3)The RETI instruction in the user interrupt processing routine terminates the interrupt processing. MB90560 series CHAPTER 6 INTERRUPTS 145 6.6 Interrupt of Extended Intelligent I/O Service (EIOS) The extended intelligent I/O service (EI2OS) automatically transfers data between a peripheral function (I/O) and memory. When the data transfer terminates, a hardware interrupt is generated. s Extended intelligent I/O service (EI2OS) The extended intelligent I/O service is a type of hardware interrupt. It automatically transfers data between a peripheral function (I/O) and a memory. Traditionally, data transfer with a peripheral function (I/O) has been performed by the interrupt processing program. EI2OS performs this data transfer in the same way as direct memory access (DMA). At termination, EI2OS sets the termination condition and automatically branches to the interrupt processing routine. The user creates programs only for EI2OS activation and termination. Data transfer programs in between are not required. q Advantages of extended intelligent I/O service (EI2OS) Compared to data transfer performed by the interrupt processing routine, EI2OS has the following advantages. * * * * Coding a transfer program is not necessary, reducing program size. Because transfer can be stopped depending on the peripheral function (I/O) status, unnecessary data transfer can be eliminated. Incrementing or no updating can be selected for the buffer address. Incrementing or no updating can be selected for the I/O register address. q Extended intelligent I/O service (EI2OS) termination interrupt When data transfer by EI2OS terminates, a termination condition is set in the S1 and S0 bits in the interrupt control register (ICR). Processing then automatically branches to the interrupt processing routine. The EI2OS termination factor can be determined by checking the EI2OS status (ICR: S1, S0) with the interrupt processing program. s Operation of the extended intelligent I/O service (EI2OS) Figure 6.6-1 shows EI2OS operation. Memory space I/O register I/O register Peripheral functon (I/O) Interrupt request Interrupt control register (ICR) Interrupt controller Buffer ISD: IOA: BAP: ICS: DCT: EI2OS descriptor I/O address pointer Buffer address pointer EI2OS channel selection bit in the interrupt control register (ICR) Data counter Figure 6.6-1 Extended intelligent I/O service (EI2OS) operation (1)I/O requests transfer. (2)The interrupt controller selects the descriptor. (3)The transfer source and transfer destination are read from the descriptor. (4)Transfer is performed between I/O and memory. (5)The interrupt cause is automatically cleared. MB90560 series CHAPTER 6 INTERRUPTS 147 6.6 Interrupt of Extended Intelligent I/O Service (EIOS) 6.6.1 Extended intelligent I/O service (EIOS) descriptor (ISD) The extended intelligent I/O service (EI2OS) descriptor (ISD) resides in internal RAM at "000100H" to "00017FH". The ISD consists of 8 bytes x 16 channels. s Configuration of the extended intelligent I/O service (EIOS) descriptor (ISD) The ISD consists of 8 bytes x 16 channels. Each ISD has the structure shown in Figure 6.6-2. Table 6.6-1 shows the correspondence between channel numbers and ISD addresses. Data counter upper 8 bits (DCTH) Data counter lower 8 bits (DCTL) I/O register address pointer upper 8 b its (IOAH) I/O register address pointer lower 8 b its (IOAL) EI2OS status register (ISCS) Buffer address pointer upper 8 bits (BAPH) Buffer address pointer middle 8 bits (BAPM) First ISD address (000100H + 8 x ICS) Buffer address pointer lower 8 bits (BAPL) H L Figure 6.6-2 Configuration of EI2OS descriptor (ISD) Table 6.6-1 Correspondence between channel numbers and descriptor addresses Channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Descriptor address 000100H 000108H 000110H 000118H 000120H 000128H 000130H 000138H 000140H 000148H 000150H 000158H 000160H 000168H 000170H 000178H 148 CHAPTER 6 INTERRUPTS MB90560 series Memo MB90560 series CHAPTER 6 INTERRUPTS 149 6.6 Interrupt of Extended Intelligent I/O Service (EIOS) 6.6.2 Registers of the extended intelligent I/O service (EIOS) descriptor (ISD) The extended intelligent I/O service (EI2OS) descriptor (ISD) consists of the following registers. * Data counter (DCT) * I/O register address pointer (IOA) * EI2OS status register (ISCS) * Buffer address pointer (BAP) Note that the initial value of each register is undefined after a reset. s Data counter (DCT) The DCT is a 16-bit register that serves as a counter for the data transfer count. After each data transfer, the counter is decremented by 1. When the counter reaches zero, EI2OS terminates. Figure 6.6-3 shows the configuration of the DCT. Initial value R/W: Read-write X: Undefined Figure 6.6-3 Configuration of DCT s I/O register address pointer (IOA) The IOA is a 16-bit register that indicates the lower address (A15 to A0) of the I/O register used to transfer data to and from the buffer. The upper address (A23 to A16) is all zeros. Any I/O from "000000H" to "00FFFFH" can be specified by address. Figure 6.6-4 shows the configuration of the IOA. Initial value R/W: Read-write X: Undefined Figure 6.6-4 Configuration of I/O register address pointer (IOA) 150 CHAPTER 6 INTERRUPTS MB90560 series s Extended intelligent I/O service (EI2OS) status register (ISCS) The ISCS is an 8-bit register. The ISCS indicates the update/fixed for the buffer address pointer and I/O register address pointer, transfer data format (byte or word), and transfer direction. Figure 6.6-5 shows the configuration of the ISCS. Initial value EI2OS termination control bit Not terminated by a request from the peripheral function. Terminated by a request from the peripheral function Data transfer direction specification bit I/O register address pointer buffer address pointer. Buffer address pointer I/O register address pointer BAP update/fixed selection bit After data transfer, the buffer address pointer is updated. (*1) After data transfer, the buffer address pointer is not updated. Transfer data length specification bit Byte Word IOA update/fixed selection bit After data transfer, the I/O register address pointer is updated. (*2) After data transfer, the buffer address pointer is not updated. Reserved bits 0 must be written to these bits. R/W: Read-write X: Undefined *1 Only the lower 16 bits of the buffer address pointer change. The buffer address pointer can only be incremented. *2 The address pointer can only be incremented. Figure 6.6-5 Configuration of EI2OS status register (ISCS) s Buffer address pointer (BAP) The BAP is a 24-bit register that retains the address used by EI2OS for the next transfer. Since one independent BAP exists for each EI2OS channel, each EI2OS channel can transfer data between any address in the 16-megabyte space and the I/O. If the BF bit (BAP update/fixed selection bit in the EI2OS status register) in the EI2OS status register (ISCS) is set to "update yes," only the lower 16 bits (BAPH, BAPL) of the BAP change; the upper 8 bits (BAPH) do not change. Figure 6.6-6 shows the configuration of the BAP. MB90560 series CHAPTER 6 INTERRUPTS 151 to to to Initial value R/W: Read-write X: Undefined Figure 6.6-6 Configuration of buffer address pointer (BAP) Reference * * * The area that can be specified by the I/O address pointer (IOA) extends from "000000H" to "00FFFFH". The area that can be specified with the buffer address pointer (BAP) extends from "000000H" to "FFFFFFH". The maximum transfer count that can be specified by the data counter (DCT) is 65,536 (64 kilobytes). 152 CHAPTER 6 INTERRUPTS MB90560 series Memo MB90560 series CHAPTER 6 INTERRUPTS 153 6.7 Operation of the extended intelligent I/O service (EIOS) If an interrupt request is generated by a peripheral function, EI2OS activation is set in the corresponding interrupt control register (ICR) that the CPU uses EI2OS to transfer data. When the specified data transfer count terminates, the hardware interrupt is automatically processed. s Operation flow of the extended intelligent I/O service (EI2OS) Figure 6.7-1 shows the flow of EI2OS operation based on the internal microcode of the CPU. Interrupt request generated by peripheral function NO ISE = 1 YES Read ISD/ISCS Interrupt sequence Termination request from peripheral function NO YES SE = 1 NO YES DIR = 1 NO Data indicated by IOA (data transfer) memory indicated by BAP YES Data indicated by BAP (data transfer) memory indicated by BAP IF = 0 NO YES Updage value by BW Update IOA BF = 0 NO Decrement DCT YES Updage value by BW (-1) Update BAP DCT = 00 NO Set S1 and S0 to 00 YES EI2OS termination processing Set S1 and S0 to 01 Set S1 and S0 to 11 Clear interrupt request from the peripheral function Clear ISE to 0 Interrupt sequence Return to CPU operation ISD: ISCS: IF: BW: BF: DIR: SE: EIOS descriptor EIOS status register IOA update/fixed selection bit in the EIOS status register (ISCS) Transfer data length specification bit in the EIOS status register (ISCS) BAP update/fixed selection bit in the EIOS status register (ISCS) Data transfer direction specification bit in the EIOS status register (ISCS) EIOS termination control bit in the EIOS status register (ISCS) Data counter I/O register address pointer Buffer address pointer EIOS enable bit in the interrupt control register S1, S0: EIOS status in the interrupt control register (ICR) DCT: IOA: BAP: ISE: Figure 6.7-1 Flow of extended intelligent I/O service (EI2OS) operation 154 CHAPTER 6 INTERRUPTS MB90560 series 6.7 Operation of the extended intelligent I/O service (EIOS) 6.7.1 Procedure for using the extended intelligent I/O service (EIOS) Before the extended intelligent I/O service (EI2OS) can be used, the system stack area, extended intelligent I/O service (EI2OS) descriptor, interrupt function, and interrupt control register (ICR) must be set. s Procedure for using the extended intelligent I/O service (EI2OS) Figure 6.7-2 shows the EI2OS software and hardware processing. Software processing Start Set the system stack area Set the EI2OS descriptor Initialization Initialize the peripheral function Set the interrupt control register (ICR) Hardware processing Set the built-in peripheral to start operation. Set the interrupt enable bit Set the ILM and I in the PS (Interrupt request) and (ISE = 1) Transfer data NO S1, S0 = "00" Execute the user program (Branch to interrupt vector) Decide whether to end counting or to branch to an interrupt requested by the resource YES S1, S0 = "01" or S1, S0 = "11" Set the extended intelligent I/O service again (switch channels) Process data in the buffer RETI ISE: EI2OS enable bit in the interrupt control register (ICR) S1, S0: EI2OS status of the interrupt control register (ICR) Figure 6.7-1 Procedure for using the extended intelligent I/O service (EI 2OS) MB90560 series CHAPTER 6 INTERRUPTS 155 6.7 Operation of the extended intelligent I/O service (EIOS) 6.7.2 Processing time of the extended intelligent I/O service (EIOS) The time required for processing the extended intelligent I/O service (EI2OS) is varied according to the following factors: * EI2OS status register (ISCS) setting * Address (area) pointed by the I/O register address pointer (IOA) * Address (area) pointed by the buffer address pointer (BAP) * External data bus length for external access * Transfer data length Because the hardware interrupt is activated when data transfer by EI2OS terminates, the interrupt handling time is needed to be considered. s Processing time (one transfer time) of the extended intelligent I/O service (EI2OS) q When data transfer continues The EI2OS processing time for data transfer continuation is shown in Table 6.7-1 based on the EI2OS status register (ISCS) setting. Table 6.7-1 Extended intelligent I/O service execution time EI2OS termination control bit (SE) setting IOA update/fixed selection bit (IF) setting BAP address update/fixed selection bit (BF) setting Fixed Update Terminates due to Ignores termination termination request request from the from the peripheral peripheral Fixed 32 34 Update 34 36 Fixed 33 35 Update 35 37 Unit:Machine cycle (One machine cycle corresponds to one clock cycle of the machine clock (). As shown in Table 6.7-2, compensation is necessary depending on the EI2OS execution condition. Table 6.7-2 Data transfer compensation value for EI2OS execution time Internal access I/O register address pointer B/Even Internal access Buffer address pointer External access B/Even Odd B/Even 8/Odd 0 +2 +1 +4 Odd +2 +4 +3 +6 B/Even +1 +3 +2 +5 8/Odd +4 +6 +5 +8 External access B:Byte data transfer 8:External bus using the 8-bit word transfer Even:Even-numbered address word transfer Odd:Odd-numbered address word transfer 156 CHAPTER 6 INTERRUPTS MB90560 series q When the data counter (DCT) count terminates (final data transfer) Because the hardware interrupt is activated when data transfer by EI2OS terminates, the interrupt handling time is added. The EI2OS processing time when counting terminates is calculated with the following formula: EI2OS processing time when counting terminates = EI2OS processing time when data is transferred + (21 + 6 x Z) Machine cycles Interrupt handling time The interrupt handling time is different for each address pointed to by the stack pointer. Table 6.7-3 shows the compensation value (Z) for the interrupt handling time. Table 6.7-3 Interpolation value (Z) for the interrupt handling time Address pointed to by the stack pointer External 8-bit External even-numbered address External odd-numbered address Internal even-numbered address Internal odd-numbered address Compensation value (Z) +4 +1 +4 0 +2 q For termination by a termination request from the peripheral function (I/O) When data transfer by EI2OS is terminated before completion due to a termination request from the peripheral function (I/O) (ICR: S1, S0 = 11), the data transfer is not performed and a hardware interrupt is activated. The EI2OS processing time is calculated with the following formula. Z in the formula indicates the compensation value for the interrupt handling time (Table 6.7-3). EI2OS processing time for termination before completion = 36 + 6 x Z Machine cycle MB90560 series CHAPTER 6 INTERRUPTS 157 6.8 Exception Processing Interrupt In the F2MC-16LX, the execution of an undefined instruction results in exception processing. Exception processing is basically the same as an interrupt. When the generation of an exception processing is detected on the instruction boundary, ordinary processing is interrupted and exception processing is executed. Generally, exception processing occurs as the result of an unexpected operation. Exception processing should be used only to activate recovery software required for debugging or an emergency. s Exception processing q Exception processing operation The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions. When an undefined instruction is executed, processing equivalent to the INT #10 software interrupt instruction is executed. The following processing is executed before exception processing branches to the interrupt routine: * * * The A, DPR, ADB, DTB, PCB, PC, and PS registers are saved to the system stack. The I flag of the condition code register (CCR) is cleared to 0, and hardware interrupts are masked. The S flag of the condition code register (CCR) is set to 1, and the system stack is activated. The program counter (PC) value saved to the stack is the exact address where the undefined instruction is stored. For 2-byte or longer instruction codes, the code identified as undefined is stored at this address. When the exception factor type must be determined within the exception processing routine, use this PC value. q Return from exception processing When the RETI instruction returns control from exception processing, exception processing restarts because the PC is pointing to the undefined instruction. Provide a solution such as resetting the software. 158 CHAPTER 6 INTERRUPTS MB90560 series Memo MB90560 series CHAPTER 6 INTERRUPTS 159 6.9 Stack Operations for Interrupt Processing Once an interrupt is accepted, the contents of the dedicated registers are automatically saved to the system stack before a branch to interrupt processing. When the interrupt processing terminates, the previous processing is automatically restored from the stack. s Stack operations at the start of interrupt processing Once an interrupt is accepted, the CPU automatically saves the contents of the current dedicated registers to the system stack in the order given below: * * * * * * * Accumulator (A) Direct page register (DPR) Additional data bank register (ADB) Data bank register (DTB) Program bank register (PCB) Program counter (PC) Processor status (PS) Figure 6.9-1 shows the stack operations at the start of interrupt processing. Immediately before interrupt Memory Address Immediately after interrupt Memory Address SP after update Byte Byte Figure 6.9-1 Stack operations at the start of interrupt processing s Stack operations on return from interrupt processing When the interrupt return instruction (RETI) is executed at the termination of interrupt processing, the PS, PC, PCB, DTB, ADB, DPR, and A values are returned from the stack in reverse order from the order they were placed on the stack. The dedicated registers are restored to the status they had immediately before the start of interrupt processing. 160 CHAPTER 6 INTERRUPTS MB90560 series s Stack area q Stack area allocation The stack area is used for saving and restoring the program counter (PC) when the subroutine call instruction (CALL) and vector call instruction (CALLV) are executed in addition to interrupt processing. The stack area is used for temporary saving and restoring of registers by the PUSHW and POPW instructions. The stack area is allocated together with the data area in RAM. Figure 6.9-2 shows the stack area. Vector table (interrupt vector call instruction for a reset) ROM area Stack area Built-in RAM area General-purpose register bank area Built-in I/O area *1 The internal ROM is different for each model. *2 The internal RAM is different for each model. Figure 6.9-2 Stack area q System stack and user stack The system stack area is used for interrupt processing. When an interrupt occurs, the user stack area being used is forcibly switched to the system stack. The system stack area must be set correctly even in a system that mainly uses the user stack area. If division of the stack space is not particularly necessary, use only the system stack. MB90560 series CHAPTER 6 INTERRUPTS 161 6.10 Sample Programs for Interrupt Processing This section contains sample programs for interrupt processing. s Sample programs for interrupt processing q Processing specifications The following is a sample program for an interrupt that uses external interrupt 0 (INT0). q Sample coding DDR1 ENIR ENRR ELVR ICR00 STACK EQU 000011H ; Port 1 direction register EQU 030H ; Interrupt/DTP enable register EQU 031H ; Interrupt/DTP flag EQU 032H ; Request level setting register EQU 0B0H ; Interrupt control register SSEG ; Stack RW 100 STACK_T RW 1 STACK ENDS ;---------Main program ------------------------------------------------------------------------------------------------------------CODECSEG START: MOV RP,#0 ; General-purpose registers use the first bank. MOV ILM, #07H ; Sets ILM in PS to level 7. MOV A, #!STACK_T ; Sets system stack. MOV SSB, A MOVW A, #STACK_T ; Sets stack pointer, then MOVW SP, A ; Sets SSP because S flag = 1. MOV DDR1, #00000000B ; Sets P10/INT0 pin to input. OR CCR, #40H ; Sets I flag of CCR in PS, enables interrupts. MOV E:ICR00, #00H ; Sets interrupt level to 0 (highest priority). MOV I:ELVR, #00000001B ; Requests that INT0 be made level H. MOV I:ENRR, #00H ; Clears INT0 interrupt cause. MOV I:ENRR, #01H ; Enables INT0 input. : LOOP: NOP ; Dummy loop NOP NOP NOP BRA LOOP ; Unconditional jump ;---------Interrupt program ---------------------------------------------------------------------------------------------ED_INT1: MOV I:EIRR, #00H ; Acceptance of new INT0 not allowed NOP NOP NOP NOP NOP NOP RETI ; Return from interrupt CODE ENDS ;--------Vector setting----------------------------------------------------------------------------------------------------VECT CSEG ABS=0FFH ORG 0FFD0H ; Sets vector for interrupt #11 (0BH). DSL ED_INT1 ORG 0FFDCH ; Sets reset vector. DSL START DB 00H ; Sets single-chip mode. VECT ENDS END START 162 CHAPTER 6 INTERRUPTS MB90560 series s Processing specifications of sample program for extended intelligent I/O service (EI2OS) 1)This program detects the H level signal input to the INT0 pin and activates the extended intelligent I/O service (EI2OS). 2)When the H level is input to the INT0 pin, EI2OS is activated. Data is transferred from port 0 to the memory at the 3000H address. 3)The number of transfer data bytes is 100 bytes. After 100 bytes are transferred, an interrupt is generated because EI2OS transfer has terminated. q Sample coding DDR1 ENIR ENRR ELVR ICR00 BAPL BAPM BAPH ISCS IOAL IOAH DCTL DCTH ER0 STACK EQU 000011H ; Port 1-direction register EQU 000030H ; Interrupt/DTP enable register EQU 000031H ; Interrupt/DTP factor register EQU 000032H ; Request level setting register EQU 0000B0H ; Interrupt control register EQU 000100H ; Lower buffer address pointer EQU 000101H ; Middle buffer address pointer EQU 000102H ; Upper buffer address pointer EQU 000103H ; EI2OS status EQU 000104H ; Lower I/O address pointer EQU 000105H ; Upper I/O address pointer EQU 000106H ; Low-order data counter EQU 000107H ; High-order data counter EQU ENRR:0 ; Definition of external interrupt request flag bit SSEG ; Stack RW 100 STACK_T RW 1 STACK ENDS ;-------------------Main program-----------------------------------------------------------------------------------------CODECSEG START: AND CCR, #0BFH ; Clears the I flag of the CCR in the PS and ; prohibits interrupts. MOV RP, #00 ; Sets the register bank pointer. MOV A, #STACK_T ; Sets the system stack. MOV SSB, A MOVW A, #STACK_T ; Sets the stack pointer, then MOVW SP, A ; Sets SSP because the S flag = 1. MOV I:DDR1, #00000000B ; Sets the P10/INT0 pin to input. MOV BAPL, #00H ; Sets the buffer address (003000H). MOV BAPM, #30H MOV BAPH, #00H MOV ISCS, #00010001B ; No I/O address update, byte transfer, ; buffer address updated ; I/O buffer transfer, terminated by the ; peripheral function. MOV IOAL, #00H ; Sets the transfer source address ; (port 0: 000000H). MOV IOAH, #00H MOV DCTL, #64H ; Sets the number of transfer bytes (100 bytes). MOV DCTH, #00H MOV I:ICR00, #00001000B ; EI2OS channel 0, EI2OS enable, ; interrupt level 0 (highest priority) MOV I:ELVR, #00000001B ; Requests that INT0 be made H level. MOV I:ENRR, #00H ; Clears the INT0 interrupt cause. MOV I:ENIR, #01H ; Enables INT0 interrupts. MOV ILM, #07H ; Sets the ILM in the PS to level 7. OR CCR, #40H ; Sets the I flag of the CCR in the PS ; and enables interrupts. MB90560 series CHAPTER 6 INTERRUPTS 163 : LOOP BRA LOOP ; Infinite loop ;---------------Interrupt program--------------------------------------------------------------------------------------------------WARI CLRB ER0 ; Clears interrupt/DTP request flag. : User processing ; Checks EI2OS termination factor, : ; processes data in buffer, sets EI2OS again. RETI CODE ENDS ;---------------Vector processing------------------------------------------------------------------------------------------------VECT CSEG ABS=0FFH ORG 0FFD0H ; Sets vector for interrupt #11 (0BH). DSL WARI ORG 0FFDCH ; Sets reset vector. DSL START DB 00H ; Sets single-chip mode. VECT ENDS END START 164 CHAPTER 6 INTERRUPTS MB90560 series Memo MB90560 series CHAPTER 6 INTERRUPTS 165 CHAPTER 7 SETTING A MODE This chapter describes the operating modes and memory access modes supported by the MB90560 series. 7.1 Setting a Mode ............................................................................... 168 7.2 Mode Pins (MD2 to MD0)............................................................... 169 7.3 Mode Data...................................................................................... 170 7.1 Setting a Mode The F2MC-16LX supports the modes for access method, access areas, and tests. A mode is determined based on the settings by the mode pin at a reset as well as the mode data fetched. s Mode setting The F2MC-16LX supports the modes for access method, access areas, and tests, classified as shown in Figure 7.1-1 in this module. Operating mode Bus mode RUN EPROM Programming Modes Single-chip mode Figure 7.1-1 Mode classification s Operating modes The operating modes control the operating state of the device, and are specified by the mode setting pin (MDx) and Mx bit contents in mode data. Selecting operating modes enables normal operation, and the activation of internal test programs and special test functions. 168 CHAPTER 7 SETTING A MODE MB90560 series 7.2 Mode Pins (MD2 to MD0) Three external pins, MD2 to MD0, are supported as the mode pins. These are used to specify how the reset vector and mode data are fetched. s Mode pins (MD2 to MD0) The mode pins are used to select the data bus (external or internal) used for reading the reset vector and to specify the bus width when the external data bus is selected. For a PROM version, the mode pins are also used to specify PROM programming mode, which is used to write programs and other data to internal ROM. Table 7.2-1 shows the mode pin settings. Table 7.2-1 Mode pin settings MD2 0 0 0 MD2 0 0 1 MD0 0 1 0 The reset sequence and subsequent sequences are controlled by mode data. Setting not allowed Mode name Reset vector access area External data bus width Remarks 0 1 1 Internal vector mode Internal Mode data 1 1 1 1 0 0 1 1 0 1 0 1 PROM programming mode Setting not allowed MD2 to MD0: Connect the pins to Vss for 0 and to Vcc for 1. MB90560 series CHAPTER 7 SETTING A MODE 169 7.3 Mode Data The mode data is at memory location FFFFDFH, and is used to specify the operation after a reset sequence. The mode data is automatically fetched to the CPU. s Mode data During a reset sequence, the mode data at address FFFFDFH is fetched to the mode register in the CPU core. The CPU uses the mode data to set the memory access mode. The contents of the mode register can only be changed during the reset sequence. The settings in the register take effect after the reset sequence. Figure 7.3-1 shows the mode data configuration. 7 Mode data M1 6 M0 5 0 4 0 3 0 2 0 1 0 0 0 Function extension bits (reserved area) Bus mode setting bits Figure 7.3-1 Mode data configuration s Bus mode setting bits The bus mode setting bits specify operating mode after a reset sequence. Table 7.3-1 lists the relationship between the bits and functions. Table 7.3-1 Bus mode setting bits and functions M1 0 0 1 1 M0 0 1 0 1 (Setting not allowed) (Mode data) Function Single-chip mode Remarks 8 bits 170 CHAPTER 7 SETTING A MODE MB90560 series Figure 7.3-2 shows the correspondence between access areas and physical addresses in single-chip mode. FFFFFFH Model #1 FF0000H ROM 00FFFFH Model #2 Model #3 000100H 0000C0H 000000H ROM When mirror ROM function is selected RAM : No access : Internal access Note: Model #x becomes the model-dependent address. Figure 7.3-2 Correspondence between access areas and physical addresses in single-chip mode s Relationship between mode pins and mode data Table 7.3-2 lists the relationship between mode pins and mode data. Table 7.3-2 Relationship between mode pins and mode data Mode Single-chip mode MD2 0 MD1 1 MD0 1 M1 0 M0 0 MB90560 series CHAPTER 7 SETTING A MODE 171 CHAPTER 8 I/O PORTS This chapter describes the functions and operations of the I/O ports. 8.1 Overview of I/O Ports ..................................................................... 174 8.2 Port Register .................................................................................. 175 8.3 Port 0.............................................................................................. 176 8.4 Port 1.............................................................................................. 182 8.5 Port 2.............................................................................................. 188 8.6 Port 3.............................................................................................. 194 8.7 Port 4.............................................................................................. 200 8.8 Port 5.............................................................................................. 206 8.9 Port 6.............................................................................................. 212 8.10 Sample I/O Port Program ............................................................... 218 8.1 Overview of I/O Ports An I/O port can be used as a general-purpose I/O port (parallel I/O port). The MB90560 series has six ports (50 pins). The ports are also used for peripheral function I/O pins (peripheral function I/O pins). s I/O Port Functions Each I/O port outputs data from the CPU to the I/O pins or inputs signals from the I/O pins to the CPU as directed by the port data register (PDR). Each I/O port can also be set the direction of a data flow (input or output) at the I/O pins for each bit using the port data direction register (DDR). The function of each port and the peripheral functions using it are described below: * * * * * * * Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 : General-purpose I/O port : General-purpose I/O port/peripheral function (external interrupt input pins) : General-purpose I/O port/peripheral function (16-bit reload timer/ICU) : General-purpose I/O port/peripheral function (OCU/UART0) : General-purpose I/O port/peripheral function (UART0, 8-bit/16-bit PPG timer) : General-purpose I/O port/peripheral function (analog input pins) : General-purpose I/O port/peripheral function (UART1) Table 8.1-1 summarizes the functions of individual ports. Table 8.1-1 Functions of individual ports Port Pin Input form Output form Function General I/O port Port 0 P00~P07 P10/INT0 ~P17/FRCK P20/TIN0 ~P27/IN3 P30/RTO0 ~P37/SOT0 P40/SCK0 ~P46/PPG5 P50/AN0 ~P57/AN7 P60/SIN1 ~P63/INT7/ DTTI Analog/CMOS (hysteresis) CMOS Analog input General I/O port Analog input CMOS Peripheral function - - - - - - - - - - - - CMOS (hysteresis) CMOS General I/O port Peripheral function General I/O port CMOS pull- Peripheral function up resistor selectable General I/O port bit bit bit bit 15 14 13 12 - - - - - - - - bit 11 - - bit bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10 - - - - - - P07 P06 P05 P04 P03 P02 P01 P00 - - - P27 IN3 - - - - - - - - - - P26 IN2 - - P46 - - - P25 IN1 - - P45 - - - P24 IN0 - - P44 - - - P23 - - - P22 - - - P21 - - - P20 Port 1 P17 P16 P15 P14 P13 P12 P11 P10 Peripheral function FRCK INT6 INT5 INT4 INT3 INT2 INT1 INT0 General I/O port Peripheral function General I/O port - - P37 - - P36 - - P35 - - P34 - - P33 - - P32 - - P31 - - P30 Port 2 TO1 TIN1 TO0 TIN0 - - P43 - - P42 - - P41 - - P40 Port 3 Peripheral function SOT0 SIN0 RTO5 RTO4 RTO3 RTO2 RTO1 RTO0 - - P57 - - P56 - - P55 - - P54 - - P53 - - P52 AN2 - - - P51 AN1 - - - P50 AN0 - Port 4 PPG5 PPG4 PPG3 PPG2 PPG1 PPG0 SCK0 - - - - - - - - - - - P63 - - P62 - - P61 - - P60 Port 5 AN7 AN6 AN5 AN4 AN3 - - - - - Port 6 INT7/ SCK1 SOT1 SIN1 DTTI 174 CHAPTER 8 I/O PORTS MB90560 series 8.2 Port Register This section provides a list of the registers related to the I/O port settings and shows how each port is assigned to the external pins. s Registers for I/O Ports Table 8.2-1 is a list of the registers corresponding to individual ports. Table 8.2-1 Registers and corresponding ports Register Port 0 data register (PDR0) Port 1 data register (PDR1) Port 2 data register (PDR2) Port 3 data register (PDR3) Port 4 data register (PDR4) Port 5 data register (PDR5) Port 6 data register (PDR6) Port 0 data direction register (DDR0) Port 1 data direction register (DDR1) Port 2 data direction register (DDR2) Port 3 data direction register (DDR3) Port 4 data direction register (DDR4) Port 5 data direction register (DDR5) Port 6 data direction register (DDR6) Analog data input enable register (ADER) Port 0 pull-up resistor setting register (RDR0) Port 1 pull-up resistor setting register (RDR1) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 00008CH 00008DH Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB -XXXXXXXB XXXXXXXXB ----XXXXB 00000000B 00000000B 00000000B 00000000B -0000000B 00000000B ----0000B 11111111B 00000000B 00000000B R/W:Read/write enabled R:Read only X:Undefined -:Not used MB90560 series CHAPTER 8 I/O PORTS 175 8.3 Port 0 Port 0 is a general-purpose I/O port. This section provides the configuration of port 0, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. s Port 0 Configuration Port 0 consists of the following: * * * * s Port 0 Pins Table 8.3-1 lists the port 0 pins. Table 8.3-1 Port 0 pins I/O form Port Pin P00 P01 P02 P03 Port 0 P04 P05 P06 P07 P04 P05 P06 P07 General-purpose I/O pins Port 0 data register (PDR0) Port 0 data direction register (DDR0) Port 0 pull-up resistor setting register (RDR0) Port function Input P00 P01 P02 P03 Generalpurpose I/O CMOS (hysteresis) CMOS Circuit type Output C See Section 1.7, "I/O Circuit Types," for information on the circuit types. 176 CHAPTER 8 I/O PORTS MB90560 series s Block Diagram of Port 0 Pins Figure 8.3-1 is a block diagram of the port 0 pins. RDR Port data register (PDR) Pull-up resistor About 50K s Port 0 Registers Port 0 registers are PDR0, DDR0, and RDR0. The bits making up each register correspond to the port 0 pins on a one-to-one basis. Table 8.3-2 lists the port 0 pins and their corresponding register bits. Table 8.3-2 Port 0 pins and their corresponding register bits Port PDR0,DDR0,RDR0 Port 0 Corresponding pin P07 P06 P05 P04 P03 P02 P01 P00 MB90560 series Internal data bus PDR read Output latch PDR write Port data direction register (DDR) Direction latch Pin DDR write DDR read Standby control (SPL = 1) Figure 8.3-1 Block diagram of port 0 pins Register bits and corresponding port pins bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 CHAPTER 8 I/O PORTS 177 8.3 Port 0 8.3.1 Port 0 Registers (PDR0, DDR0, and RDR0) This section describes the port 0 registers. s Functions of Port 0 Registers q Port 0 data register (PDR0) The PDR0 register indicates the state of each pin of port 0. q Port 0 data direction register (DDR0) The DDR0 register specifies the direction of a data flow (input or output) at each pin (bit) of port "0". When a DDR0 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is 0, the port (pin) is set as an input port. q Port 0 pull-up resistor setting register (RDR0) The RDR0 register specifies the selection of a pull-up resistor at each pin (bit) of port 0. When a RDR0 register bit is "1", a pull-up resistor is selected for the corresponding port (pin). When the bit is "0", the pull-up resistor is deselected. Table 8.3-3 lists the functions of the port 0 registers. Table 8.3-3 Port 0 register functions Dat a During reading Read/ Write Register During writing Address Initial value 0 Port 0 data register (PDR0) 1 The pin is at the low level. The pin is at the high level. The direction latch is "0". The direction latch is "1". The setting latch is "0". The setting latch is "1". The output latch is loaded with "0". When the pin functions as an output port, the pin is set to the low level. The output latch is loaded with "1". When the pin functions as an output port, the pin is set to the high level. The output buffer is turned off to place the port in input mode. R/W 000000H XXXXXXXXB Port 0 data direction register (DDR0) 0 R/W The output buffer is turned on to place the port in output mode. The pull-up resistor is cut and the port is placed in the Hi-Z state in input mode. The pull-up resistor is selected and the port is held at the high level in input mode. 000010H 00000000B 1 Port 0 pull-up resistor setting register (RDR0) 0 R/W 00008CH 00000000B 1 R/W X 178 : Read/write enabled : Undefined CHAPTER 8 I/O PORTS MB90560 series Memo MB90560 series CHAPTER 8 I/O PORTS 179 8.3 Port 0 8.3.2 Operation of Port 0 This section describes the operation of port 0. s Operation of Port 0 q Port operation in output mode * * * Setting a bit of the DDR0 register to "1" places the corresponding port pin in output mode. Data written to the PDR0 register in output mode is held in the output latch of the PDR and output to the port pins. The PDR0 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the PDR). If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data register, the target bits of the register are set to the specified value. The bits that have been specified for output using the DDR register are not affected, but for the bits that have been specified for input, a value input from the pins is written to the output latch and output as it is. Before switching the mode for the bits from input to output, therefore, write the output data to the PDR register, then specify output mode in the DDR register. q Port operation in input mode * * * * * Writing a bit of the DDR0 register to "0" places the corresponding port pin in input mode. In input mode, the output buffer is turned off, and the pins are placed in a high impedance state. However, when the RDR0 register is set to "1" to select a pull-up resistor, the pins are held at the high level. Data written to the PDR0 register in input mode is stored in the output latch of the PDR but is not output to the port pins. The PDR0 register can be accessed in read mode to read the level value ("0" or "1") at the port pins. q Port operation after a reset * When the CPU is reset, the DDR0 and PDR registers are initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), the pull-up resistor is cut, and the pins are placed in a high impedance state. The PDR0 register is not initialized when the CPU is reset. To use the port in output mode, therefore, output mode must be specified in the DDR0 register after the output data is set in the PDR0 register. * 180 CHAPTER 8 I/O PORTS MB90560 series q Port operation in stop or time-base timer mode If the pin state setting bit (SPL) in the low-power consumption mode control register (LPMCR) is already "1" when the CPU is shifted to stop or time-base timer mode, the port pins are placed in a high-impedance state. This is because the output buffer is turned off forcibly regardless of the value in the DDR0 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. Note also that when a pull-up resistor is selected, the port pins are held at the high level and not placed in a high-impedance state even when the SPL bit is set to "1". Table 8.3-4 lists the states of the port 0 pins. Table 8.3-4 States of port 0 pins Stop mode or time-base timer mode (SPL = 1, RDR = 0) Input shut down/ output in Hi-z Pin Normal operation Sleep mode Stop mode or time-base timer mode (SPL = 0) General-purpose I/O port Stop mode or time-base timer mode (SPL = 1, RDR = 1) Input shut down/held at H level P00~P07 General-purpose I/O port General-purpose I/O port SPL : Pin state setting bit of low-power mode control register (LPMCR) Hi-z : High impedance MB90560 series CHAPTER 8 I/O PORTS 181 8.4 Port 1 Port 1 is a general-purpose I/O port. It can also be used for peripheral function input. The port pins can be switched individually between the I/O port and peripheral function. This section focuses on the general I/O port function. The section provides the configuration of port 1, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. s Port 1 Configuration Port 1 consists of the following: * * * * s Port 1 Pins The port 1 pins are also used as peripheral function input pins. The pins cannot be used as output port pins when they are used as peripheral function input pins. Table 8.4-1 lists the port 1 pins. Table 8.4-1 Port 1 pins I/O form Port Pin P10/INT0 P11/INT1 P12/INT2 P13/INT3 Port 1 P14/INT4 P15/INT5 P16/INT6 P17/FRCK P14 P15 P16 P17 General-purpose I/O pins/external interrupt input pins (P10/INT0 to P17/FRCK) Port 1 data register (PDR1) Port 1 data direction register (DDR1) Port 1 pull-up resistor setting register (RDR1) Port function P10 P11 P12 P13 Generalpurpose I/O Peripheral function Input INT0 INT1 INT2 INT3 INT4 INT5 INT6 FRCK External interrupt input CMOS (hystere sis) CMOS Output Circuit type C See Section 1.7, "I/O Circuit Types," for information on the circuit types. 182 CHAPTER 8 I/O PORTS MB90560 series s Block Diagram of Port 1 Pins Figure 8.4-1 is a block diagram of port 1 pins. RDR FRCK Port data register (PDR) Peripheral input (INT) Pull-up resistor About 50K s Port 1 Registers Port 1 registers are PDR1, DDR1, and RDR1. The bits making up each register correspond to the port 1 pins on a one-to-one basis. Table 8.4-2 lists the port 1 pins and their corresponding register bits. Table 8.4-2 Port 1 pins and their corresponding register bits Port PDR1,DDR1,RDR1 Port 1 Corresponding pin P17 P16 P15 P14 P13 P12 P11 P10 MB90560 series Internal data bus PDR read Output latch PDR write Port data direction register (DDR) Direction latch Pin DDR write DDR read Standby control (SPL = 1) Figure 8.4-1 Block diagram of port 1 pins Register bits and corresponding port pins bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 CHAPTER 8 I/O PORTS 183 8.4 Port 1 8.4.1 Port 1 Registers (PDR1, DDR1, and RDR1) This section describes the port 1 registers. s Functions of Port 1 Registers q Port 1 data register (PDR1) The PDR1 register indicates the state of each pin of port 1. q Port 1 data direction register (DDR1) The DDR1 register specifies the direction of a data flow (input or output) at each pin (bit) of port 1. When a DDR1 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the port (pin) is set as an input port. q Port 1 pull-up resistor setting register (RDR1) The RDR1 register specifies the selection of a pull-up resistor at each pin (bit) of port 1. When a RDR1 register bit is "1", a pull-up resistor is selected for the corresponding port (pin). When the bit is "0", the pull-up resistor is deselected. During reading The pin is at the low level. The pin is at the high level. The direction latch is "0". The direction latch is "1". The setting latch is "0". The setting latch is "1". Register Data During writing The output latch is loaded with "0". When the pin functions as an output port, the pin is set to the low level. Read/ Write Address Initial value 0 Port 1 data register (PDR1) 1 R/W The output latch is loaded with "1". When the pin functions as an output port, the pin is set to the high level. The output buffer is turned off to place the port in input mode. R/W 1 0 1 The output buffer is turned on to place the port in output mode. The pull-up resistor is cut and the port is placed in the Hi-Z state in input mode. R/W The pull-up resistor is selected and the port is held at the high level in input mode. 000001H XXXXXXXXB Port 1 data direction register (DDR1) 0 000011H 00000000B Port 1 pull-up resistor setting register (RDR1) 00008DH 00000000B R/W X : Read/write enabled : Undefined 184 CHAPTER 8 I/O PORTS MB90560 series Memo MB90560 series CHAPTER 8 I/O PORTS 185 8.4 Port 1 8.4.2 Operation of Port 1 This section describes the operation of port 1. s Operation of Port 1 q Port operation in output mode * * * Setting a bit of the DDR1 register to "1" places the corresponding port pin in output mode. Data written to the PDR1 register in output mode is stored in the output latch of the PDR and output to the port pins as is. The PDR1 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the PDR). q Port operation for peripheral function input When the port is also used for peripheral function input, the value at the pins is always supplied as peripheral function inputs. To use an external signal for the peripheral function, reset the DDR1 register to "0" to place the port in input mode. q Port operation after a reset * When the CPU is reset, the DDR1 and PDR registers are initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), the pull-up resistor is cut, and the pins are placed in a high impedance state. The PDR1 register is not initialized when the CPU is reset. To use the port in output mode, therefore, output mode must be specified in the DDR1 register after the output data is set in the PDR1 register. * 186 CHAPTER 8 I/O PORTS MB90560 series q Port operation in stop or time-base timer mode If the pin state setting bit (SPL) in the low-power mode control register (LPMCR) is already "1" when the CPU is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the DDR1 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. Note also that when a pull-up resistor is selected, the port pins are held at the high level and not placed in a high-impedance state even when the SPL bit is set to 1. Table 8.4-4 lists the states of the port 1 pins. Table 8.4-4 States of port 1 pins Stop mode or time-base timer mode (SPL = 1, RDR = 0) Pin Normal operation Sleep mode Stop mode or time-base timer mode (SPL = 0) Stop mode or timebase timer mode (SPL = 1, RDR = 1) P10/ INT0~P17 /FRCK General-purpose I/O port General-purpose I/O port General-purpose I/O port Input enabled/ output in Hi-z Input shut down/ held at H level SPL : Pin state setting bit of low-power mode control register (LPMCR) Hi-z : High impedance MB90560 series CHAPTER 8 I/O PORTS 187 8.5 Port 2 Port 2 is a general-purpose I/O port. It can also be used for peripheral function input and output. The port pins can be switched in units of bits between the I/O port and the peripheral function. This section focuses on the general I/O port function. This section also provides the configuration of port 2, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. s Port 2 Configuration Port 2 consists of the following: * * * s Port 2 Pins The port 2 I/O pins are also used as peripheral function I/O pins. The pins cannot be used as general-purpose I/O port pins when they are used as peripheral function I/O pins. Table 8.5-1 lists the port 2 pins. Table 8.5-1 Port 2 pins I/O form Port Pin Port function Peripheral function Input P20/TIN0 P21/TO0 P22/TIN1 P23/TO1 Port 2 P24/IN0 P25/IN1 P26/IN2 P27/IN3 P24 P25 P26 P27 P20 P21 P22 P23 Generalpurpose I/O IN0 IN1 IN2 IN3 TIN0 TO0 TIN1 TO1 16-bit reload timer 0 event input 16-bit reload timer 0 timer output 16-bit reload timer 1 event input 16-bit reload timer 1 timer output Input capture channel 0 input Input capture channel 1 input Input capture channel 2 input Input capture channel 3 input General-purpose I/O pins/peripheral function I/O pins (P20/TIN0 to P27/IN3) Port 2 data register (PDR2) Port 2 data direction register (DDR2) Output Circuit type CMOS (hysteresis) CMOS D See Section 1.7, "I/O Circuit Types," for information on the circuit types. 188 CHAPTER 8 I/O PORTS MB90560 series s Block Diagram of Port 2 Pins Figure 8.5-1 is a block diagram of port 2 pins. Peripheral input Port data register (PDR) Peripheral output Peripheral output enable PDR read Output latch s Port 2 Registers Port 2 registers are PDR2 and DDR2. The bits making up each register correspond to the port 2 pins on a one-to-one basis. Table 8.5-2 lists the port 2 pins and their corresponding register bits. Table 8.5-2 Port 2 pins and their corresponding register bits Port PDR2,DDR2 Port 2 Corresponding pin P27 P26 P25 P24 P23 P22 P21 P20 bit7 MB90560 series Internal data bus PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) Figure 8.5-1 Block diagram of port 2 pins Register bits and corresponding port pins bit6 bit5 bit4 bit3 bit2 bit1 bit0 CHAPTER 8 I/O PORTS 189 8.5 Port 2 8.5.1 Port 2 Registers (PDR2 and DDR2) This section describes the port 2 registers. s Functions of Port 2 Registers q Port 2 data register (PDR2) The PDR2 register indicates the state of each pin of port 2. q Port 2 data direction register (DDR2) The DDR2 register specifies the direction of a data flow (input or output) at each pin (bit) of port 2. When a DDR2 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the port (pin) is set as an input port. * Table 8.5-3 lists the functions of the port 2 registers. Table 8.5-3 Port 2 register functions During reading The pin is at the low level. The pin is at the high level. The direction latch is "0". The direction latch is "1". Register Data During writing The output latch is loaded with "0". When the pin functions as an output port, the pin is set to the low level. Read/ Write Address Initial value 0 Port 2 data register (PDR2) 1 R/W The output latch is loaded with "1". When the pin functions as an output port, the pin is set to the high level. The output buffer is turned off to place the port in input mode. R/W 1 The output buffer is turned on to place the port in output mode. 000002H XXXXXXXXB Port 2 data direction register (DDR2)) 0 000012H 00000000B R/W : Read/write enabled X : Undefined 190 CHAPTER 8 I/O PORTS MB90560 series Memo MB90560 series CHAPTER 8 I/O PORTS 191 8.5 Port 2 8.5.2 Operation of Port 2 This section describes the operation of port 2. s Operation of Port 2 q Port operation in output mode * * * Setting a bit of the DDR2 register to "1" places the corresponding port pin in output mode. Data written to the PDR2 register in output mode is stored in the output latch of the PDR and output to the port pins as is. The PDR2 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the PDR). q Port operation for peripheral function output The peripheral function output enable bit is set to enable the port to be used for peripheral function output. The state of the peripheral function enable bit takes precedence when specifying a switch between input and output. Even if a DDR2 register bit is "0", the corresponding port pin is used for peripheral function output if the peripheral function has been enabled for output. Because the value at the pins can be read even if peripheral function output is enabled, the peripheral function output value can be read. q Port operation for peripheral function input When the port is also used for peripheral function input, the value at the pins is always supplied as peripheral function inputs. To use an external signal for the peripheral function, reset the DDR2 register to "0" to place the port in input mode. 192 CHAPTER 8 I/O PORTS MB90560 series q Port operation after a reset * * When the CPU is reset, the DDR2 register is initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), the pins are placed in a high impedance state. The PDR2 register is not initialized when the CPU is reset. To use the port in output mode, therefore, output mode must be specified in the DDR2 register after the output data is set in the PDR2 register. q Port operation in stop or time-base timer mode If the pin state setting bit (SPL) in the low-power mode control register (LPMCR) is already "1" when the CPU is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the DDR2 register. Stop mode or time-base timer mode (SPL = 0) Input enabled/ output in Hi-z Pin Normal operation Sleep mode Stop mode or time-base timer mode (SPL = 0) General-purpose I/O port Stop mode or timebase timer mode (SPL = 1) Input shut down/output in Hi-z P20/INT0~ P27/IN3 General-purpose I/O port General-purpose I/O port SPL : Pin state setting bit of low-power mode control register (LPMCR) Hi-z : High impedance MB90560 series CHAPTER 8 I/O PORTS 193 8.6 Port 3 Port 3 is a general-purpose I/O port. It can also be used for peripheral function input and output. The port pins can be switched in units of bits between the I/O port and peripheral function. This section focuses on the general I/O port function. It provides the configuration of port 3, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. s Port 3 Configuration Port 3 consists of the following: * * * s Port 3 Pins The port 3 I/O pins are also used as peripheral function I/O pins. Therefore, the pins cannot be used as general-purpose I/O port pins when they are used as peripheral function I/O pins. Table 8.6-1 lists the port 3 pins. Table 8.6-1 Port 3 pins Port function (single-chip mode) P30 P31 P32 P33 P34 P35 P36 P37 Generalpurpose I/O RTO0 RTO1 RTO2 RTO3 RTO4 RTO5 SIN0 SOT0 General-purpose I/O pins/peripheral function I/O pins (P30/PPG0 to P37/SOT0) Port 3 data register (PDR3) Port 3 data direction register (DDR3) I/O form Peripheral function Input OCU channel 0 output OCU channel 1 output OCU channel 2 output OCU channel 3 output OCU channel 4 output OCU channel 5 output UART0 data input UART0 data output CMOS (hysteresis) CMOS Port Pin P30/RTO0 P31/RTO1 P32/RTO2 P33/RTO3 Output Circuit type Port 3 P34/RTO4 P35/RTO5 P36/SIN0 P37/SOT0 D See Section 1.7, "I/O Circuit Types," for information on the circuit types. 194 CHAPTER 8 I/O PORTS MB90560 series s Block Diagram of Port 3 Pins Figure 8.6-1 is a block diagram of port 3 pins. Peripheral input Port data register (PDR) Peripheral output Peripheral output enable PDR read Output latch s Port 3 Registers Port 3 registers are PDR3 and DDR3. The bits making up each register correspond to the port 3 pins on a one-to-one basis. Table 8.6-2 lists the port 3 pins and their corresponding register bits. Table 8.6-2 Port 3 pins and their corresponding register bits Port PDR3, DDR3 Port 3 Corresponding pin P37 P36 P35 P34 P33 P32 P31 P30 MB90560 series Internal data bus PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) Figure 8.6-1 Block diagram of port 3 pins Register bits and corresponding port pins bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 CHAPTER 8 I/O PORTS 195 8.6 Port 3 8.6.1 Port 3 Registers (PDR3 and DDR3) This section describes the port 3 registers. s Functions of Port 3 Registers q Port 3 data register (PDR3) The PDR3 register indicates the state of each pin of port 3. q Port 3 data direction register (DDR3) The DDR3 register specifies the direction of a data flow (input or output) at each pin (bit) of port 3. When a DDR3 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the port (pin) is set as an input port. * Table 8.6-3 lists the functions of the port 3 registers. Table 8.6-3 Port 3 register functions During reading The pin is at the low level. The pin is at the high level. The direction latch is "0". The direction latch is "1". Register Data During writing The output latch is loaded with "0". When the pin functions as an output port, the pin is set to the low level. Read/ Write Address Initial value 0 Port 3 data register (PDR3) 1 R/W The output latch is loaded with "1". When the pin functions as an output port, the pin is set to the high level. The output buffer is turned off to place the port in input mode. R/W 1 The output buffer is turned on to place the port in output mode. 000003H XXXXXXXXB Port 3 data direction register (DDR3) 0 000013H 00000000B R/W : Read/write enabled X : Undefined 196 CHAPTER 8 I/O PORTS MB90560 series Memo MB90560 series CHAPTER 8 I/O PORTS 197 8.6 Port 3 8.6.2 Operation of Port 3 This section describes the operation of port 3. s Operation of Port 3 q Port operation in output mode * * * Setting a bit of the DDR3 register to "1" places the corresponding port pin in output mode. Data written to the PDR3 register in output mode is stored in the output latch of the PDR and output to the port pins as is. The PDR3 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the PDR). q Port operation for peripheral function output The peripheral function output enable bit is set to enable the port to be used for peripheral function output. The state of the peripheral function enable bit takes precedence when specifying a switch between input and output. Even if a DDR3 register bit is "0", the corresponding port pin is used for peripheral function output if the peripheral function has been enabled for output. Because the value at the pins can be read even if peripheral function output is enabled, the peripheral function output value can be read. q Port operation for peripheral function input When the port is also used for peripheral function input, the value at the pins is always supplied as peripheral function inputs. To use an external signal for the peripheral function, reset the DDR3 register to "0" to place the port in input mode. 198 CHAPTER 8 I/O PORTS MB90560 series q Port operation after a reset * * When the CPU is reset, the DDR3 register is initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), the pins are placed in a high impedance state. The PDR3 register is not initialized when the CPU is reset. To use the port in output mode, therefore, output mode must be specified in the DDR3 register after the output data is set in the PDR3 register. q Port operation in stop or time-base timer mode If the pin state setting bit (SPL) in the low-power mode control register (LPMCR) is already "1" when the CPU is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the DDR3 register. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. Table 8.6-4 lists the states of the port 3 pins. Table 8.6-4 States of port 3 pins Stop mode or time-base timer mode (SPL = 0) General-purpose I/O port Pin P30/RT00~ P37/SOT0 Normal operation General-purpose I/O port Sleep mode General-purpose I/O port Stop mode or timebase timer mode (SPL = 1) Input shut down/output in Hi-z SPL : Pin state setting bit of low-power mode control register (LPMCR) Hi-z : High impedance MB90560 series CHAPTER 8 I/O PORTS 199 8.7 Port 4 Port 4 is a general-purpose I/O port. It can also be used for peripheral function input and output. The port pins can be switched in units of bits between the I/O port and peripheral function. This section focuses on the general I/O port function. It provides the configuration of port 4, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. s Port 4 Configuration Port 4 consists of the following: * * * s Port 4 Pins The port 4 I/O pins are also used as peripheral function I/O pins. The pins cannot be used as general-purpose I/O port pins when they are used as peripheral function I/O pins. Table 8.7-1 lists the port 4 pins. Table 8.7-1 Port 4 pins Port function (single-chip mode) P40 P41 P42 P43 P44 P45 P46 - Generalpurpose I/O SCK0 PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 - General-purpose I/O pins/peripheral function I/O pins (P40/SCK0 to P45/PPG5) Port 4 data register (PDR4) Port 4 data direction register (DDR4) I/O form Peripheral function Input UART0 serial clock I/O Port Pin P40/SCK0 P41/PPG0 P42/PPG1 P43/PPG2 Output Circuit type D PPG0 output PPG1 output PPG2 output PPG3 output PPG4 output PPG5 output - CMOS (hysteresis) CMOS F P45/PPG4 P46/PPG5 - Port 4 P44/PPG3 See Section 1.7, "I/O Circuit Types," for information on the circuit types. 200 CHAPTER 8 I/O PORTS MB90560 series s Block Diagram of Port 4 Pins Figure 8.7-1 is a block diagram of port 4 pins. Peripheral input Port data register (PDR) Peripheral output Peripheral output enable s Port 4 Registers Port 4 registers are PDR4 and DDR4. The bits making up each register correspond to the port 4 pins on a one-to-one basis. Table 8.7-2 lists the port 4 pins and their corresponding register bits. Table 8.7-2 Port 4 pins and their corresponding register bits Port PDR4,DDR4 Port 4 Corresponding pin - P46 P45 P44 P43 P42 P41 P40 bit7 MB90560 series Internal data bus PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) Figure 8.7-1 Block diagram of port 4 pins Register bits and corresponding port pins bit6 bit5 bit4 bit3 bit2 bit1 bit0 CHAPTER 8 I/O PORTS 201 8.7 Port 4 8.7.1 Port 4 Registers (PDR4 and DDR4) This section describes the port 4 registers. s Functions of Port 4 Registers q Port 4 data register (PDR4) The PDR4 register indicates the state of each pin of port 4. q Port 4 data direction register (DDR4) The DDR4 register specifies the direction of a data flow (input or output) at each pin (bit) of port 4. When a DDR4 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the port (pin) is set as an input port. * Table 8.7-3 lists the functions of the port 4 registers. Table 8.7-3 Port 4 register functions During reading The pin is at the low level. The pin is at the high level. The direction latch is "0". The direction latch is "1". Register Data During writing The output latch is loaded with "0". When the pin functions as an output port, the pin is set to the low level. Read/ Write Address Initial value 0 Port 4 data register (PDR4) 1 R/W The output latch is loaded with "1". When the pin functions as an output port, the pin is set to the high level. The output buffer is turned off to place the port in input mode. R/W 1 The output buffer is turned on to place the port in output mode. 000004H -XXXXXXXB Port 4 data direction register (DDR4) 0 000014H -0000000B R/W : Read/write enabled X - : Undefined : Empty bit 202 CHAPTER 8 I/O PORTS MB90560 series Memo MB90560 series CHAPTER 8 I/O PORTS 203 8.7 Port 4 8.7.2 Operation of Port 4 This section describes the operation of port 4. s Operation of Port 4 q Port operation in output mode * * * Setting a bit of the DDR4 register to "1" places the corresponding port pin in output mode. Data written to the PDR4 register in output mode is stored in the output latch of the PDR and output to the port pins as is. The PDR4 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the PDR). q Port operation for peripheral function output The peripheral function output enable bit is set to enable the port to be used for peripheral function output. The state of the peripheral function enable bit takes precedence when specifying a switch between input and output. Even if a DDR4 register bit is "0", the corresponding port pin is used for peripheral function output if the peripheral function has been enabled for output. Because the value at the pins can be read even if peripheral function output is enabled, the peripheral function output value can be read. q Port operation for peripheral function input When the port is also used for peripheral function input, the value at the pins is always supplied as peripheral function inputs. To use an external signal for the peripheral function, reset the DDR4 register to "0" to place the port in input mode. 204 CHAPTER 8 I/O PORTS MB90560 series q Port operation after a reset * * When the CPU is reset, the DDR4 register is initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), the pins are placed in a high impedance state. The PDR4 register is not initialized when the CPU is reset. To use the port in output mode, therefore, output mode must be specified in the DDR4 register after the output data is set in the PDR4 register. q Port operation in stop or time-base timer mode If the pin state setting bit (SPL) in the low-power mode control register (LPMCR) is already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the DDR4 register. Stop mode or timebase timer mode (SPL = 0) General-purpose I/O port Stop mode or timebase timer mode (SPL = 1) Input shut down/ output in Hi-z Pin Normal operation Sleep mode Hardware standby mode Input shut down/output in Hi-z P40/SIN0~P47/ ATG General-purpose I/O port General-purpose I/ O port SPL : Pin state setting bit of low-power mode control register (LPMCR) Hi-z : High impedance MB90560 series CHAPTER 8 I/O PORTS 205 8.8 Port 5 Port 5 is a general-purpose I/O port. It can also be used for A/D converter analog input. The port pins can be switched in units of bits between the I/O port and analog input. This section focuses on the general I/O port function. It provides the configuration of port 5, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. s Port 5 Configuration Port 5 consists of the following: * * * * s Port 5 Pins The port 5 I/O pins are also used as analog input pins. The pins cannot be used as generalpurpose I/O port pins when they are used for analog input. Similarly, the port 5 I/O pins cannot be used for analog input when they are used as a general-purpose I/O port. Table 8.8-1 lists the port 5 pins. Table 8.8-1 Port 5 pins Port function (single-chip mode) P50 P51 P52 P53 P54 P55 P56 P57 Generalpurpose I/O AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 General-purpose I/O pins/analog input pins (P50/AN0 to P57/AN7) Port 5 data register (PDR5) Port 5 data direction register (DDR5) Analog input enable register (ADER) I/O form Peripheral function Input Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 CMOS (hysteresis) CMOS Port Pin P50/AN0 P51/AN1 P52/AN2 P53/AN3 Output Circuit type Port 5 P54/AN4 P55/AN5 P56/AN6 P57/AN7 E See Section 1.7, "I/O Circuit Types," for information on the circuit types. 206 CHAPTER 8 I/O PORTS MB90560 series s Block Diagram of Port 5 Pins ADER Port data register (PDR) Analog input s Port 5 Registers Port 5 registers are PDR5, DDR5, and ADER. The bits making up each register correspond to the port 5 pins on a one-to-one basis. Table 8.8-2 lists the port 5 pins and their corresponding register bits. Table 8.8-2 Port 5 pins and their corresponding register bits Port Register bits and corresponding port pins Internal data bus Port 5 MB90560 series PDR read Output latch PDR write Port data direction register (DDR) Direction latch Pin DDR write DDR read Standby control (SPL = 1) Figure 8.8-1 Block diagram of port 5 pins PDR5,DDR5,ADER Corresponding pin bit15 P57 bit14 P56 bit13 P55 bit12 P54 bit11 P53 bit10 P52 bit9 P51 bit8 P50 CHAPTER 8 I/O PORTS 207 8.8 Port 5 8.8.1 Port 5 Registers (PDR5, DDR5, and ADER) This section describes the port 5 registers. s Functions of Port 5 Registers q Port 5 data register (PDR5) The PDR5 register indicates the state of each pin of port 5. q Port 5 data direction register (DDR5) The DDR5 register specifies the direction of a data flow (input or output) at each pin (bit) of port 5. When a DDR5 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is 0, the port (pin) is set as an input port. q Analog input enable register (ADER) Each bit of the ADER register specifies whether the corresponding port 5 pin is to be used as a general-purpose I/O port or an analog input pin. Setting an ADER bit to "1" enables the corresponding pin for analog input. Setting the bit to "0" enables the pin for general-purpose I/O. During reading The pin is at the low level. The pin is at the high level. The direction latch is "0". The direction latch is "1". Port I/O mode R/W 1 Analog input mode 000017H 11111111B Register Data During writing Low level is output to the pin. (The output latch is loaded with "0: to turn on the output transistor.) Read/ Write Address Initial value 0 Port 5 data register (PDR5) 1 R/W The pin is placed in a high-impedance state. (The output latch is loaded with "1" to turn off the output transistor.) The output buffer is turned off to place the port in input mode. R/W 1 0 The output buffer is turned on to place the port in output mode. 000005H XXXXXXXB Port 5 data direction register (DDR5) Analog input enable register (ADER) 0 000015H 00000000B R/W : Read/write enabled X 208 : Undefined CHAPTER 8 I/O PORTS MB90560 series Memo MB90560 series CHAPTER 8 I/O PORTS 209 8.8 Port 5 8.8.2 Operation of Port 5 This section describes the operation of port 5. s Operation of Port 5 q Port operation in output mode * Setting a bit of the DDR5 register to "1" places the corresponding port pin in output mode.Data written to the PDR5 register in output mode is held in the output latch of the PDR and output to the port pins. The PDR5 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the PDR). * q Port operation for analog input To use a port pin for analog input, write "1" to the corresponding ADER bit. Doing so disables the port from operating as a general-purpose port pin and enables it to function as an analog input pin. When PDR5 is accessed in read mode in this situation, a value of "0" is read. q Port operation after a reset When the CPU is reset, the DDR5 register is initialized to "0" and the ADER register is initialized to "1" to place the port in analog input mode. To use the port as a general-purpose port, write "0" to the ADER register in advance to place the port in port I/O mode. q Port operation in stop or time-base timer mode If the pin state setting bit (SPL) in the low-power mode control register (LPMCR) is already "1" when the CPU is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly. Note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. Table 8.8-4 lists the states of the port 5 pins. 210 CHAPTER 8 I/O PORTS MB90560 series Table 8.8-4 States of port 5 pins Stop mode or time-base timer mode (SPL = 0) General-purpose I/O port Pin Normal operation General-purpose I/O port Sleep mode General-purpose I/O port Stop mode or timebase timer mode (SPL = 1) Input shut down/output in Hi-z P50/AN0~P57/AN7 SPL : Pin state setting bit of low-power mode control register (LPMCR) Hi-z : High impedance MB90560 series CHAPTER 8 I/O PORTS 211 8.9 Port 6 Port 6 is a general-purpose I/O port. It can also be used for peripheral function input and output. The port pins can be switched in units of bits between the I/O port and peripheral function. This section focuses on the general I/O port function. It provides the configuration of port 6, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. s Port 6 Configuration Port 6 consists of the following: * * * s Port 6 Pins The port 6 I/O pins are also used as peripheral function I/O pins. The pins cannot be used as general-purpose I/O port pins when they are used as peripheral function I/O pins. Table 8.9-1 lists the port 6 pins. Table 8.9-1 Port 6 pins Port function (single-chip mode) P60 P61 P62 P63 - - - - Generalpurpose I/O SIN1 SOT1 SCK1 INT7 - - - - General-purpose I/O pins/peripheral function I/O pins (P60/SIN1 to P62/SCK1) Port 6 data register (PDR6) Port 6 data direction register (DDR6) I/O form Peripheral function Input UART1 data input UART1 data output UART1 serial clock I/O External interrupt input/ DTTI input - - - - CMOS (hysteresis) Port Pin P60/SIN1 P61/SOT1 P62/SCK1 P63/INT7/ DTTI - - - - Output Circuit type Port 6 CMOS D See Section 1.7, "I/O Circuit Types," for information on the circuit types. 212 CHAPTER 8 I/O PORTS MB90560 series s Block Diagram of Port 6 Pins Figure 8.9-1 is a block diagram of port 6 pins. Peripheral input Port data register (PDR) Peripheral output Peripheral output enable s Port 6 Registers Port 6 registers are PDR6 and DDR6. The bits making up each register correspond to the port 6 pins on a one-to-one basis. Table 8.9-2 lists the port 6 pins and their corresponding register bits. Table 8.9-2 Port 6 pins and their corresponding register bits Port PDR6,DDR6 Port 6 Corresponding pin - - - - P63 P62 P61 P60 bit7 MB90560 series Internal data bus PDR read Output latch PDR write Pin Port data direction register (DDR) Direction latch DDR write DDR read Standby control (SPL = 1) Figure 8.9-1 Block diagram of port 6 pins Register bits and corresponding port pins bit6 bit5 bit4 bit3 bit2 bit1 bit0 CHAPTER 8 I/O PORTS 213 8.9 Port 6 8.9.1 Port 6 Registers (PDR6 and DDR6) This section describes the port 6 registers. s Functions of Port 6 Registers q Port 6 data register (PDR6) The PDR6 register indicates the state of each pin of port 6. q Port 6 data direction register (DDR6) The DDR6 register specifies the direction of a data flow (input or output) at each pin (bit) of port 6. When a DDR6 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the port (pin) is set as an input port. Check: To use a peripheral function having input pins, reset the DDR6 register bit corresponding to each peripheral function input pin to "0" to place the port in input mode. Table 8.9-3 lists the functions of the port 6 registers. Table 8.9-3 Port 6 register functions Read/ Write Register Data During reading During writing The output latch is loaded with "0". When the pin functions as an output port, the pin is set to the low level. Address Initial value 0 Port 6 data register (PDR6) 1 The pin is at the low level. The pin is at the high level. The direction latch is "0". The direction latch is "1". R/W The output latch is loaded with "1". When the pin functions as an output port, the pin is set to the high level. The output buffer is turned off to place the port in input mode. R/W 1 The output buffer is turned on to place the port in output mode. 000006H ----XXXXB Port 6 data direction register (DDR6) 0 000016H ----0000B R/W : Read/write enabled X - : Undefined : Empty bit 214 CHAPTER 8 I/O PORTS MB90560 series Memo MB90560 series CHAPTER 8 I/O PORTS 215 8.9 Port 6 8.9.2 Operation of Port 6 This section describes the operation of port 6. s Operation of Port 6 q Port operation in output mode * * * Setting a bit of the DDR6 register to "1" places the corresponding port pin in output mode. Data written to the PDR6 register in output mode is stored in the output latch of the PDR and output to the port pins as is. The PDR6 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the PDR). q Port operation for peripheral function output The peripheral function output enable bit is set to enable the port to be used for peripheral function output. The state of the peripheral function enable bit takes precedence when specifying a switch between input and output. Even if a DDR6 register bit is "0", the corresponding port pin is used for peripheral function output if the peripheral function has been enabled for output. Because the value at the pins can be read even if peripheral function output is enabled, the peripheral function output value can be read. q Port operation for peripheral function input When the port is also used for peripheral function input, the value at the pins is always supplied as peripheral function inputs. To use an external signal for the peripheral function, reset the DDR6 register to "0" to place the port in input mode. 216 CHAPTER 8 I/O PORTS MB90560 series q Port operation after a reset * * When the CPU is reset, the DDR6 register is initialized to "0". As a result, the output buffer is turned off (I/O mode changes to input), the pins are placed in a high impedance state. The PDR6 register is not initialized when the CPU is reset. To use the port in output mode, therefore, output mode must be specified in the DDR6 register after output data is set in the PDR6 register. q Port operation in stop or time-base timer mode If the pin state setting bit (SPL) in the low-power mode control register (LPMCR) is already "1" when the port is shifted to stop or time-base timer mode, the port pins are placed in a highimpedance state. This is because the output buffer is turned off forcibly regardless of the value in the DDR6 register. Stop mode or timebase timer mode (SPL = 0) General-purpose I/O port Pin P60/SIN1~ P63/INT7/DTTI Normal operation General-purpose I/O port Sleep mode General-purpose I/O port Stop mode or timebase timer mode (SPL = 1) Input shut down/output in Hi-z SPL : Pin state setting bit of low-power mode control register (LPMCR) Hi-z : High impedance MB90560 series CHAPTER 8 I/O PORTS 217 8.10 Sample I/O Port Program This section provides a sample program using I/O port pins. s Sample I/O Port Program q Processing specifications * * Ports 0 and 1 are used to turn on all segments of a seven-segment (eight-segment if the decimal point is included) LED. Pin P00 corresponds to the anode common pin of the LED, and pins P10 to P17 correspond to the segment pins. Figure 8.10-1 is an example of connecting the eight-segment LED to the MB90560 ports. MB90560 P00 P17 P16 P15 P14 P13 P12 P11 P10 Figure 8.10-1 Example of eight-segment LED connection q Coding example PDR0 EQU 000000H PDR1 EQU 000001H DDR0 EQU 000010H DDR1 EQU 000011H ;-----------------------------Main program------------------------------------------------------------------------------------------------------------CODE CSEG START: ; Initialization MOV I:PDR0, #00000000B ; Puts P00 at a low level (#xxxxxxx0B). MOV I:DDR0, #11111111B ; Puts all port 0 bits in output mode. MOV I:PDR1, #11111111B ; Sets all port 1 bits to 1. MOV I:DDR1, #11111111B ; Puts all port 1 bits in output mode. CODE ENDS ; -------------------------------------------------------------------------------------------------------------------------------------------------------------END START 218 CHAPTER 8 I/O PORTS MB90560 series Memo MB90560 series CHAPTER 8 I/O PORTS 219 CHAPTER 9 TIMEBASE TIMER This chapter describes the functions and operation of the timebase timer. 9.1 Overview of the Timebase Timer ................................................... 222 9.2 Configuration of the Timebase Timer ............................................. 224 9.3 Timebase Timer Control Register (TBTC)...................................... 226 9.4 Timebase Timer Interrupts ............................................................. 228 9.5 Operation of the Timebase Timer................................................... 230 9.6 Usage Notes on the Timebase Timer............................................. 232 9.7 Sample Program for the Timebase Timer Program ....................... 234 9.1 Overview of the Timebase Timer The timebase timer is an 18-bit free-run counter (timebase counter) that counts up in synchronization with the internal count clock (one-half of the source oscillation). The timer has an interval timer function that can select four intervals. The timebase timer also has functions for timer output of the oscillation stabilization wait interval and for supplying the clocks for the watchdog timer. s Interval timer function The interval timer function repeatedly generates an interrupt request at a given interval. * * An interrupt request is generated when the interval timer bit for the timebase counter overflows. Four types of the interval timer (interval) can be selected. Table 9.1-1 lists the intervals for the timebase timer. Table 9.1-1 Intervals for the timebase timer Internal count clock cycle Interval cycle 212/HCLK (Approx. 1.0 ms) 214/HCLK (Approx. 4.1 ms) 2/HCLK (0.5 s) 216/HCLK (Approx. 16.4 ms) 219/HCLK (Approx. 131.1 ms) HCLK: Oscillation clock Values in parentheses are for a 4 MHz oscillation clock. 222 CHAPTER 9 TIMEBASE TIMER MB90560 series s Clock supply function The clock supply function supplies clocks to the oscillation stabilization wait interval timer and to some peripheral functions. Table 9.1-2 lists the cycle times of clocks supplied from the timebase timer to each peripheral. Table 9.1-2 Clock cycle time supplied from the timebase timer Clock destination Oscillation stabilization wait interval Clock cycle time 213/HCLK (Approx. 2.0 ms) 215/HCLK (Approx. 8.2 ms) Oscillation settling time for crystal vibrator 217/HCLK (Approx. 32.8 ms) 212/HCLK (Approx. 1.0 ms) 214/HCLK (Approx. 4.1 ms) Watchdog timer 216/HCLK (Approx. 16.4 ms) 219/HCLK (Approx. 131.1 ms) PPG timer 29/HCLK (Approx. 128 s) Count-up clock for watchdog timer Remarks Oscillation settling time for ceramic vibrator HCLK: Oscillation clock Values in parentheses occurs during operation of the 4 MHz oscillation clock. MB90560 series CHAPTER 9 TIMEBASE TIMER 223 9.2 Configuration of the Timebase Timer The timebase timer consists of the following four blocks: * Timebase timer counter * Counter clear circuit * Interval timer selector * Timebase timer control register (TBTC) s Block diagram of the timebase timer Figure 9.2-1 shows the block diagram of the timebase timer. To the PPG timer Timebase timer counter HCLK/2 To the watchdog timer To the oscillation stabilization wait interval selector in the clock control section Power-on reset Stop mode start CKSCR: MCS = 1 0 (1) Counter clear circuit Interval timer selector TBOF set TBOF clear Timebase timer control register (TBTC) Timebase timer interrupt signal #34 (22H) (*2) OF: Overflow HCLK: Oscillation clock *1 Switching of the machine clock from the oscillation clock to the PLL clock Figure 9.2-1 Block diagram of the timebase timer 224 CHAPTER 9 TIMEBASE TIMER MB90560 series q Timebase timer counter This 18-bit up counter uses the divide-by-two clock of the oscillation clock (HCLK) as the count clock. q Counter clear circuit Used to clear the counter by writing "0" to the TBTC TBR bit, by a power-on reset, or by transition to stop mode (LPMCR:STP = 1). q Interval timer selector Selects one of four outputs of the timebase timer counter. An overflow of the selected bit becomes an interrupt cause. q Timebase timer control register (TBTC) Selects the interval, clears the counter, controls an interrupt request, and checks the status. MB90560 series CHAPTER 9 TIMEBASE TIMER 225 9.3 Timebase Timer Control Register (TBTC) The timebase timer control register (TBTC) selects the interval, clears the counter, controls interrupts, and checks the status. s Timebase timer control register (TBTC) bit15 bit14 bit13 bit12 bit11 bit10 bit9 Address 0000A9H RESV R/W - bit8 bit7 (WDTC) bit0 Initial value 1- - 00100B TBIE TBOF TBR TBC1 TBC0 R/W R/W W R/W R/W TBC1 TBC0 0 0 1 1 0 1 0 1 Interval selection bit 212/HCLK (Approx. 1.0 ms) 214/HCLK (Approx. 4.1 ms) 216/HCLK (Approx. 16.4 ms) 219/HCLK (Approx. 131 ms) Values in parentheses are for a 4 MHz oscillation clock. Timebase timer initialization bit TBR During reading During writing Clearing of the timebase timer counter and TBOF bit No change, no effect on other bits. 0 1 The read value is always "1". TBOF Interrupt request flag bit During reading During writing Clearing of this bit No change, no effect on other bits. 0 No overflow from the specified bit Overflow from the specified bit 1 TBIE 0 1 RESV Interrupt request enable bit Interrupt request output disabled Interrupt request output enabled Reserved bit R/W : Read/write W : Write only - : Not used x : Undefined : Initial value Be sure to write "1" to this bit. Figure 9.3-1 Timebase timer control register (TBTC) 226 CHAPTER 9 TIMEBASE TIMER MB90560 series Table 9.3-1 Function description of each bit in the timebase timer control register (TBTC) Bit name bit15 bit14 bit13 bit12 RESV: Reserved bit Not used TBIE: Interrupt request enable bit TBOF: Interrupt request flag bit Function * When read, the value is undefined. * Writing has no effect on operation. * Used to enable or disable the output of an interrupt request to the * When this bit and the interrupt request flag bit (TBOF) are "1", an interrupt request is output. CPU. bit11 * This bit is set to 1 when the bit specifying the timebase timer * When this bit and the interrupt request enable bit (TBIE) are "1", * During writing, this bit is cleared with "0". If "1" is written, the bit does not change and there is no effect. bit10 TBR: Timebase timer initialization bit * Used to clear the timebase timer counter. * When "0" is written to this bit, the counter is cleared and the TBOF bit is cleared. If "1" is written, the bit does not change and there is no effect. bit9 bit8 TBC1, TBC0: Interval selection bit * Used to select an interval timer cycle. * The bit for the interval timer of the timebase timer counter is * Four types of interval can be selected. specified. MB90560 series CHAPTER 9 TIMEBASE TIMER 227 9.4 Timebase Timer Interrupts The timebase timer can generate an interrupt request when the bit specifying the timebase timer counter overflows. (Interval timer function) s Timebase timer interrupts The interrupt request flag bit (TBTC:TBOF) is set to "1" when the timebase timer counter counts up with the internal count clock and when the bit for the selected interval timer bit overflows. If the interrupt request enable bit has been enabled (TBTC:TBIE = 1), an interrupt request (#36) is generated in the CPU. Writing "0" to the TBOF bit in the interrupt handling routine clears the interrupt request. When the specified bit overflows, the TBOF bit is set regardless of the TBIE bit value. s Timebase timer interrupts and EI2OS Table 9.4-1 lists the timebase timer interrupt and EI2OS. Table 9.4-1 Timebase interrupts and EI2OS Interrupt level setting register Register name Address 0000BCH Vector table address EI2OS Lower FFFF6CH Upper FFFF6DH Bank FFFF6EH x Interrupt number #36 (24H) x: Not available ICR12 228 CHAPTER 9 TIMEBASE TIMER MB90560 series Memo MB90560 series CHAPTER 9 TIMEBASE TIMER 229 9.5 Operation of the Timebase Timer The timebase timer provides the interval timer function and the clock supply function that supplies clocks to some peripheral functions. s Operation of the interval timer function (timebase timer) The interval timer function generates an interrupt request for each interval The setting in Figure 9.5-1 is required for timebase timer to operate as an interval timer. : Used : Set "0" : Set "1" Figure 9.5-1 Setting of the timebase timer * * The timebase timer counter continues counting up in synchronization with the internal count clock (one-half of the oscillation clock) as long as the clock is being oscillated. When the counter is cleared (TBR = 0), it counts up from "0". When the interval timer bit overflows, the interrupt request flag bit (TBOF) is set to "1". If interrupt request output has been enabled (TBIE = 1), an interrupt is generated for each selected interval based on the cleared time. The interval may become longer than the time set because of timebase timer clearing. * s Oscillation stabilization wait interval timer function The timebase timer is also used as the oscillation stabilization wait interval timer for oscillation and the PLL clocks. The oscillation settling time is set for the interval from the time the counter counts up from "0" (count clear) until the oscillation stabilization wait interval bit overflows. When control returns from timebase timer mode to PLL clock mode, the oscillation stabilization wait interval starts from the middle of counting because the timebase timer counter has been not cleared. Table 9.5-1 shows the clearing of the timebase counter and the oscillation settling times. 230 CHAPTER 9 TIMEBASE TIMER MB90560 series Table 9.5-1 Timebase timer counter clearing and oscillation stabilization wait intervals Operation TBTC: Writing of 0 to TBR Power-on reset o Watchdog reset Releasing of stop mode Transition from oscillation clock mode to PLL clock mode (MCS = 1 0) Releasing of timebase timer mode Releasing of sleep mode o o o Counter clear o TBOF clear o Oscillation clock oscillation stabilization wait interval Oscillation clock oscillation stabilization wait interval (at return to main clock mode) PLL clock oscillation stabilization wait interval PLL clock oscillation stabilization wait interval (at return to PLL clock mode) Oscillation stabilization wait interval o o x x x x o: Available x: Not available s Clock supply function The timebase timer supplies clocks to the watchdog timer. Clearing of the timebase counter affects operation of the watchdog timer. MB90560 series CHAPTER 9 TIMEBASE TIMER 231 9.6 Usage Notes on the Timebase Timer Notes about the effects on peripheral functions of clearing interrupt requests and the timebase timer are given below. s Timebase timer usage notes q Clearing interrupt requests The TBOF bit of the timebase timer control register must be cleared while a timebase timer interrupt is masked by the TBIE bit or the interrupt level mask register (ILM) of the processor status (PS). q Effects of timebase timer clearing Clearing of the timebase timer counter affects the following operations: * * When the timebase timer is using the interval timer function (interval interrupt) When the watchdog timer is being used q Use of the timebase timer as the oscillation settling time timer At power-on, the source oscillation of the main clock stops in main stop mode. After oscillator operation starts, the operating clock supplied by the timebase timer is used to take the oscillation stabilization wait time of the main clock. An appropriate oscillation stabilization wait time must be selected based on the type of oscillating element connected to the main clock oscillator (clock generation section). See Section 4.5, "Oscillation Stabilization Wait Time," for details. q Notes on peripheral functions to which clocks are supplied from the timebase timer In the mode in which the main clock source oscillation stops, the counter is cleared and timebase timer operation stops. When the timebase timer counter is cleared, the clock supplied from the timebase timer is supplied from its initial state. As a result, the H level is shortened and the L level lengthened 1/2 cycle. Although the clock for the watchdog timer is also supplied from its initial state; the watchdog timer operates in normal cycles because the watchdog timer counter is cleared at the same time. Counter value 00FFFH 00800H 00000H Clearing the counter by the program (TBTC: TBR = "0") Clock supplied to PPG PPG can be operated by supplying count clock from the timebase timer (Divide-by-512 source oscillation) Figure 9.6-1 Effect on PPG when clearing timebase timer 232 CHAPTER 9 TIMEBASE TIMER MB90560 series s Operation of the timebase timer The following operations are shown in Figure 9.6-2: * * * A power-on reset occurs. Sleep mode is entered during operation of the interval timer function. A counter clear request is issued. When stop mode is entered, the timebase timer is cleared and its operation stops. On return from stop mode, the timebase timer counts the oscillation settling time. Counter value Clearing by transition to stop mode Oscillation settling overflow Start of CPU operation Power-on reset (option) TBOF bit TBIE bit SLP bit (LPMC register) STP bit (LPMCR register) Interval cycle (TBTC: TBC1, TBC0 = 11H) Clearing by the interrupt handling routine Counter clearing (TBTC: TBR = 0) Sleep Releasing of interval interrupt sleep Stop Releasing of stop by an external interrupt When 11B has been set in the interval selection bit (TBTC:TBC1,TBC0) of the timebase timer control register : Indicates the oscillation settling time. Figure 9.6-2 Timebase timer operations MB90560 series CHAPTER 9 TIMEBASE TIMER 233 9.7 Sample Program for the Timebase Timer Program This section contains a sample program for the timebase timer. s Sample program for the timebase timer q Processing An interval interrupt of 212/HCLK (HCLK: oscillation clock) is repeatedly generated. The interval becomes approx. 1.0 ms (during 4 MHz operation). q Coding example ICR12 EQU 0000BCH ; Timebase timer interrupt control register TBTC EQU 0000A9H ; Timebase timer control register TBOF EQU TBTC:3 ; Interrupt request flag bit ;-------Main program-----------------------------------------------------------------------------------------------CODECSEG START: ; : ; Assumes that stack pointer (SP) has already been ; initialized. AND CCR,#0BFH ; Disables interrupts. MOV I:ICR12 #00H ; Interrupt level 0 (highest) MOV I:TBTC,#10010000B ; Fixes upper 3 bits. ; Enables interrupts and clears TBOF. ; Clears counter. ; Selects interval 212/HCLK MOV ILM,#07H ; Sets PS ILM to level 7. OR CCR,#40H ; Enables interrupts. LOOP: MOV A,#00H ; Endless loop MOV A,#01H BRA LOOP ;-------Interrupt program--------------------------------------------------------------------------------------------WARI: CLRB I:TBOF ; Clears interrupt request flag. ; : ; User handling ; : RETI ; ; Returns from interrupt. CODE ENDS ;-------Vector setting--------------------------------------------------------------------------------------------VECT CSEG ABS=0FFH ORG 0FF6CH ; Sets vector for interrupt #36 (24H). DSL WARI ORG 0FFDCH ; Sets reset vector. DSL START DB 00H ; Sets single-chip mode. VECT ENDS END START 234 CHAPTER 9 TIMEBASE TIMER MB90560 series Memo MB90560 series CHAPTER 9 TIMEBASE TIMER 235 CHAPTER 10 WATCHDOG TIMER This chapter describes the functions and operation of the watchdog timer. 10.1 Overview of the Watchdog Timer ................................................. 238 10.2 Configuration of the Watchdog Timer ........................................... 239 10.3 Watchdog Timer Control Register (WDTC) .................................. 240 10.4 Operation of the Watchdog Timer................................................. 242 10.5 Usage Notes on the Watchdog Timer........................................... 244 10.6 Sample Program for the Watchdog Timer .................................... 245 10.1 Overview of the Watchdog Timer The watchdog timer is a 2-bit counter that uses the timebase timer supply clock as the count clock. After activation, if the watchdog timer is not cleared within a given time, the CPU is reset. s Watchdog timer function The watchdog timer is a counter for handling program crashes. Once the watchdog timer is activated, it must be regularly cleared within a given time. If the program results in an endless loop and the watchdog timer is not cleared over a given time, a watchdog reset is generated for the CPU. Table 10.1-1 lists the watchdog timer intervals. If the watchdog timer is not cleared, a watchdog reset is generated between the minimum time and maximum time. Clear the counter within the minimum time listed in this table. Table 10.1-1 Intervals for the watchdog timer Interval Minimum (*1) Approx. 3.58 ms Approx. 14.33 ms Approx. 57.23 ms Approx. 458.75 ms Maximum (*1) Approx. 4.61 ms Approx. 18.3 ms Approx. 73.73 ms Approx. 589.82 ms Oscillation clock cycle count 214 211 cycle 216 213 cycle 218 215 cycle 221 218 cycle *1 Value during operation of the 4 MHz oscillation clock The maximum and minimum watchdog timer intervals and the oscillation clock cycle count depend on the clear timing. The interval is 3.5 to 4.5 times longer than the cycle of the count clock (timebase timer supply clock). See Section 11.4, "Operation of the Watchdog Timer." 238 CHAPTER 10 WATCHDOG TIMER MB90560 series 10.2 Configuration of the Watchdog Timer The watchdog timer consists of the following five blocks: * Count clock selector * Watchdog counter (2-bit counter) * Watchdog reset generator * Counter clear control circuit * Watchdog timer control register (WDTC) s Block diagram of the watchdog timer Figure 10.2-1 shows the block diagram of the watchdog timer. Watchdog timer control register (WDTC) Watchdog timer Activation with CLR Start of sleep mode Start of hold status mode Start of stop mode Counter clear control circuit Count clock selector 2-bit counter OverWatchdog flow reset generator To the internal reset generator Clear (Timebase timer counter) One-half of HCLK HCLK: Oscillation clock Figure 10.2-1 Block diagram of the watchdog timer q Count clock selector This circuit is used to select the count clock of the watchdog timer from four types of timebase timer outputs. This determines the watchdog reset generation time. q Watchdog counter (2-bit counter) This 2-bit up counter uses the timebase timer output as the count clock. q Watchdog reset generator Used to generate the reset signal by an overflow of the watchdog counter. q Counter clear circuit Used to clear the watchdog counter and to control the operation or stopping of the counter. q Watchdog timer control register (WDTC) Used to activate or clear the watchdog timer; holds the reset generation cause. MB90560 series CHAPTER 10 WATCHDOG TIMER 239 10.3 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) activates and clears the watchdog timer, and displays the reset cause. s Watchdog timer control register (WDTC) Figure 10.3-1 shows the watchdog timer control register (WDTC); Table 11.3-1 describes the function of each bit of the watchdog timer control register (WDTC). bit15 Address 0000A8H (TBTC) bit8 bit7 PONR R bit6 bit5 bit4 bit3 bit2 bit1 WT1 W bit0 WT0 W Initial value XXXXX111B WRST ERST SRST WTE R R R W Interval selection bit (for 4 MHz HCLK) WT1 0 0 1 1 WT0 Minimum 0 1 0 1 Approx. 3.58 ms Approx. 14.33 ms Approx. 57.23 ms Interval Maximum Approx. 4.61 ms Approx. 18.3 ms Approx. 73.73 ms Oscillation clock cycle count 214 211 cycle 216 213 cycle 218 215 cycle 221 218 cycle Approx. 458.75 ms Approx. 589.82 ms HCLK: Oscillation clock WTE Watchdog control bit - Activation of the watchdog timer (At first write after reset) - Clearing of the watchdog timer (At second or subsequent write after reset) No operation 0 1 Reset cause bit PONR WRST ERST SRST 1 * * * R: Read only W: Write only X: Undefined - : The contents of the bit are not guaranteed. *: Retains the previous status. : Initial value 1 * * * 1 * * * 1 Power-on Watchdog timer External pin (RSTX input) RST bit (software reset) Reset cause Figure 10.3-1 Watchdog timer control register (WDTC) The interval becomes 3.5 to 4.5 times longer than the count clock (timebase timer output value) cycle. For details, see Section 11.4, "Operation of the Watchdog Timer." 240 CHAPTER 10 WATCHDOG TIMER MB90560 series Table 10.3-1 Function description of each bit of the watchdog timer control register (WDTC) Bit name Function * Read-only bits for indicating the reset cause. If more than one bit7 bit5 bit4 bit3 PONR, WRST, ERST, SRST: Reset cause bits reset cause occurs, the bit for each reset cause occurring is set to "1". * These bits are all cleared to "0" after the watchdog timer control register (WDTC) is read. * At power-on, the contents of the bits other than the PONR bit are not guaranteed. Therefore, when the PONR bit is "1", ignore the contents of the bits other than the PONR bit. bit2 WTE: Watchdog timer control bit * When "0" is written to this bit, the watchdog timer is activated (first write after reset) or the 2-bit counter is cleared (second or subsequent write after reset). * Writing "1" does not affect operation. bit1 bit0 WT1, WT0: Interval selection bit * Used to select the watchdog timer interval. * Only data at watchdog timer activation is valid. * These bits are write-only. Data written after watchdog timer activation is ignored. MB90560 series CHAPTER 10 WATCHDOG TIMER 241 10.4 Operation of the Watchdog Timer The watchdog timer generates a watchdog reset by an overflow of the watchdog counter. s Watchdog timer operation Operation of the watchdog timer requires the setting in Figure 11.4-1. : Used : Set 0. Figure 10.4-1 Setting of the watchdog timer q Activating the watchdog timer * The watchdog timer is activated when the first "0" after reset is written to the WTE bit of the watchdog timer control register (WDTC). Specify the interval by specifying the WT1 and WT0 bits of the watchdog timer control register at the same time. When watchdog timer activation starts, it can be stopped only by a power-on, or its own reset. * q Clearing the watchdog timer * When a second or subsequent "0" is written to the WTE bit, the 2-bit counter of the watchdog timer is cleared. If the counter is not cleared within the time interval, it overflows and a watchdog reset occurs. The watchdog counter is cleared by reset generation, sleep mode, stop mode, transition to clock mode, or detection of the hold acknowledge signal. In clock mode, the watchdog timer counter is cleared and stops. * * q Intervals for the watchdog timer Figure 11.4-2 shows the relationship between the clear timing of the watchdog timer and intervals. The interval changes according to the clear timing of the watchdog timer and requires 3.5 to 4.5 times longer than the count clock cycle. q Checking a reset cause A reset cause can be determined by checking the PONR, WRST, ERST, and SRST bits of the watchdog timer control register (WDTC) after a reset. 242 CHAPTER 10 WATCHDOG TIMER MB90560 series [WDG timer block diagram] 2-bit counter Clock selector Divide-bytwo circuit Divide-bytwo circuit Reset circuit Reset signal Count enabling and clearing WTE bit Count enable output circuit [Minimum interval] When the WTE bit is cleared immediately before the count clock rises: Counter clearing Count clock a Divide-by-two value b Divide-by-two value c Count enabling Reset signal d 7 x (count clock cycle/2) WTE bit clearing Watchdog reset generation Count start [Maximum interval] When the WTE bit is cleared immediately after the count clock rises: Counter clearing Count clock a Divide-by-two value b Divide-by-two value c Count enabling Count start Reset signal 9 x (count clock cycle/2) WTE bit clearing Watchdog reset generation Figure 10.4-2 Clear timing and watchdog timer intervals MB90560 series CHAPTER 10 WATCHDOG TIMER 243 10.5 Usage Notes on the Watchdog Timer Notes on using the watchdog timer are given below. s Usage notes on the watchdog timer q Stopping the watchdog timer Once the watchdog timer is activated, it cannot stop until a power-on or watchdog reset occurs. The watchdog timer counter is cleared by software reset; however, the watchdog timer does not stop. q Intervals Since a carry signal of the timebase timer is used as the count clock for the interval, the watchdog timer interval may become longer than the setting time when the timebase timer is cleared. q Selecting the interval The interval can be set when the watchdog timer is activated. Data written during operations other than activation is ignored. q Notes on program creation When a program that repeatedly clears the watchdog timer in the main loop is created, the processing time of the main loop including the interrupt processing must be equal to or less than the minimum watchdog timer interval. q Watchdog timer operation in timebase timer mode The timebase timer operates while the timebase timer mode is set. The watchdog timer, however, is temporarily stopped. 244 CHAPTER 10 WATCHDOG TIMER MB90560 series 10.6 Sample Program for the Watchdog Timer This section contains a sample program for the watchdog timer. s Sample program for the watchdog timer q Processing * * The watchdog timer is cleared every time in the main program loop. The main loop must make one iteration within the minimum watchdog timer interval. q Coding example WDTC EQU 0000A8H ; Watchdog timer control register WTE EQU WDTC:2 ; Watchdog control bit ;-------Main program-----------------------------------------------------------------------------------------------------CODE CSEG START: ; : ; Assumes that stack pointer (SP) has already been WDG_START: ` MOV WDTC,#00000011B ; Activates watchdog timer. ; Selects the interval 221 218 cycle. ;--------Main loop---------------------------------------------------------------------------------------------------------MAIN: CLRB I:WTE ; Clears watchdog timer. ; : Clears two bits regularly. ; User processing ; : JMP MAIN ; Loops in less time than the watchdog timer interval. CODE ENDS ;--------Vector setting----------------------------------------------------------------------------------------------------VECT CSEG ABS=0FFH ORG 0FFDCH ; Sets reset vector. DSL START DB 00H ; Sets single-chip mode. VECT ENDS END START MB90560 series CHAPTER 10 WATCHDOG TIMER 245 CHAPTER 11 16-BIT RELOAD TIMER The chapter describes the functions and operation of the 16-bit reload timer. 11.1 Overview of the 16-Bit Reload Timer............................................ 248 11.2 Configuration of the 16-Bit Reload Timer ..................................... 252 11.3 16-Bit Reload Timer Pins.............................................................. 254 11.4 16-Bit Reload Timer Registers...................................................... 255 11.5 16-Bit Reload Timer Interrupts...................................................... 262 11.6 Operation of the 16-Bit Reload Timer ........................................... 264 11.7 Usage Notes on the 16-Bit Reload Timer ..................................... 272 11.8 Sample Programs for the 16-Bit Reload Timer............................. 273 11.1 Overview of the 16-Bit Reload Timer The 16-bit reload timer is synchronized with three types of internal clocks for counting down in internal clock mode, and it counts down by detecting an optional edge input to the external pin in event counter mode. This timer defines that an underflow condition results when the counter value changes from "0000H" to "FFFFH". Thus, an underflow will occur after an interval of [reload register setting value + 1] counts. Either of two modes can be selected for counting. In reload mode, the value set for the count is reloaded to repeat counting for an underflow. In single-shot mode, the counting is stopped with an underflow. The counter underflow allows the occurrence of an interrupt and coordination with the extended intelligent I/O service (EI2OS). The MB90560 series 16-bit reload timer has two built-in channels. s 16-bit reload timer operating modes Table 11.1-1 lists the operating modes of the 16-bit reload timer. Table 11.1-1 16-bit reload timer operating modes Clock mode Counter operation Reload mode Internal clock mode One-shot mode Event count mode (external clock mode) Reload mode Software trigger operation One-shot mode Operation of 16-bit reload timer Software trigger operation External trigger operation External gate input operation s Internal clock mode Internal clock mode allows selection of one of three types of internal clock for the following operations: q Software trigger operation When "1" is written to the TRG bit of the timer control status register (TMCSR), counting starts. Trigger input by the TRG bit is always valid for external trigger input as well as for external gate input. q External trigger operation When selected edges (rising, falling, and both edges) are input to the TIN0 and TIN1 pins, counting starts. q External gate input operation While the selected signal level ("L" or "H") is being input to TIN0 and TIN1 pins, counting continues. 248 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series s Event count mode (external clock mode) When selected valid edges (rising, falling, and both edges) are input to TIN0 and TIN1 pins, the timer counts down at these edges. When an external clock with a constant period is used, this timer can also be used as an interval timer. s Counter operation q Reload mode When an underflow (from "0000H" to "FFFFH") occurs during counting down, the count setting value is reloaded to continue counting. Since the 16-bit reload timer causes an interrupt request to occur for an underflow condition, it can be used as an interval timer. A toggle waveform inverted at each underflow can also be output from TO0 and TO1 pins. Table 11.1-2 lists the intervals for the 16-bit reload timer. Table 11.1-2 Intervals for the 16-bit reload timer Count clock Count clock period 21/ (0.125 s) Internal clock 23/ (0.5 s) 25/ (2.0 s) Interval 0.125 s to 8.192 ms 0.5 s to 32.768 ms 2.0 s to 131.1 ms 0.5 s or more External clock : Machine clock 23/ or more (0.5 s) Values in parentheses are for a 16 MHz machine clock. q Single-shot mode When an underflow (from "0000H" to "FFFFH") occurs during counting down, counting stops, causing an interrupt to occur for the underflow condition. During counter operation, a rectangular waveform that indicates when the count is in progress can be output from the TO0 and TO1 pins. Reference * * 16-bit reload timer 0 can be used to create the baud rate of UART0/UART1. 16-bit reload timer 1 can be used as the start trigger of the A/D converter. MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 249 s 16-bit reload timer interrupts and EI2OS Table 11.1-3 lists 16-bit reload timer interrupts and EIOS. Table 11.1-3 16-bit reload timer interrupts and EI2OS Interrupt control register Register name ICR09 ICR10 Address Vector table address EI2OS Lower Upper Bank Channel Interrupt number 16-bit reload timer 0 (*1) 16-bit reload timer 1 (*2) #30 (1EH) #32 (20H) 0000B9H 0000BAH FFFF84H FFFF7CH FFFF85H FFFF7DH FFFF86H FFF7EH : *1 *2 Available when ICR09/ICR10 or the interrupt causes sharing the interrupt vector are not used. The same interrupt number is used for 8-bit timer counter underflow and 16-bit reload timer 0. The same interrupt number is used for 16-bit free-running timer underflow and 16-bit reload timer 1. 250 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series Memo MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 251 11.2 Configuration of the 16-Bit Reload Timer 16-bit reload timers 0 and 1 each consist of the following seven blocks: * Count clock generation circuit * Reload control circuit * Output control circuit * Operation control circuit * 16-bit timer register (TMR) * 16-bit reload register (TMRLR) * Timer control status register (TMCSR) s Block diagram of the 16-bit reload timer Figure 11.2-1 shows the block diagram of the 16-bit reload timer. Internal data bus 16-bit reload register Reload signal Reload control circuit 16-bit timer register (down counter) Count clock generation circuit Machine clock Prescaler Clear Internal clock Pin Input control circuit Clock selector External clock Select signal Function selection Operation control circuit Gate input Valid clock judgment circuit Wait signal To UART0 and UART1 (*1) Output control circuit Output signal generation Invert circuit Timer control status register (TMCSR0)(*1) Interrupt request signal #30 (1EH)(*2) <#32 (20H)> *1 This register includes channel 0 and channel 1. The register enclosed in < and > indicates the channel 1 register. *2 Interrupt number Figure 11.2-1 Block diagram of the 16-bit reload timer 252 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series q Count clock generation circuit This circuit generates the count clock for the 16-bit reload timer from the machine clock or external input clock. q Reload control circuit This circuit controls the reload operation when the timer is started and when an underflow occurs. q Output control circuit This circuit controls the inversion of the TO pin output by an underflow of the 16-bit timer register and enabling and disabling of TO pin output. q Operation control circuit This circuit controls starting and stopping of the 16-bit reload timer. q 16-bit timer register (TMR) This register is a 16-bit down counter. The current counter value is read from this register during a read operation. q 16-bit reload register (TMRLR) The interval for the 16-bit reload timer is set in this register. The setting value of this register is loaded into the 16-bit timer register and decremented. q Timer control status register (TMCSR) This register selects the count clock of the 16-bit reload timer and the operating mode, sets operating conditions, starts a trigger with software, enables or disables counting, selects reload or single-shot mode and the pin output level, enables or disables timer output, controls interrupts, and controls the status. MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 253 11.3 16-Bit Reload Timer Pins This section describes the pins of the 16-bit reload timer and provides a pin block diagram. s 16-bit reload timer pins The pins of the 16-bit reload timer are shared with the general-purpose ports. Table 11.3-1 lists the functions of the pins, I/O format, and settings required to use the 16-bit reload timer. Table 11.3-1 16-bit reload timer pins Pin name Pin function Port 2 I/O pin/ timer input Port 2 I/O pin/ timer output Port 2 I/O pin/ timer input Port 2 I/O pin/ timer output CMOS output/ CMOS hysteresis input I/O format Pull-up option Standby control Settings required for pins Setting for the input port (DDR2: bit 0 = 0) Setting for timer output enable (TMCSR0: OUTE = 1) Available Setting for the input port (DDR2: bit 2 = 0) Setting for timer output enable (TMCSR1: OUTE = 1) P20/TIN0 P21/TO0 Not Available P22/TIN1 P23/TO1 s Block diagram of the 16-bit reload timer pins Figure 11.3-1 shows the block diagram of the16-bit reload timer pins. Peripheral input* Port data register (PDR) 1 Peripheral output* 1 Peripheral output enable*1 PDR read Output latch Internal data bus PDR write Pin Port data direction register (DDR) Direction latch P20/TIN0 P21/TO0 P22/TIN1 P23/TO1 DDR write DDR read Standby control (SPL = 1) Standby control: Stop, clock mode with SPL=1 *1 Only pins with peripheral functions are used for peripheral I/O Figure 11.3-1 Block diagram of the 16-bit reload timer pins 254 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series 11.4 16-Bit Reload Timer Registers The 16-bit reload timer registers are as follows. s 16-bit reload timer registers Figure 11.4-1 shows 16-bit reload timer registers. 16-bit reload timer 0 Address 000083H,82H 000085H,84H TMCSR0 (timer control status register) TMR0/TMRLR0 (16-bit timer register/16-bit reload register) (*1) 16-bit reload timer 1 000087H,86H TMCSR1 (timer control status register) 000089H,88H TMR1/TMRLR1 (16-bit timer register/16-bit reload register) (*1) *1 This register functions as a 16-bit timer register (TMR) during reading, and functions as a 16-bit reload register (TMRLR) during writing. Figure 11.4-1 16-bit reload timer registers MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 255 11.4 16-Bit Reload Timer Registers 11.4.1 Timer control status register, upper part (TMCSR0, TMCSR1: H) Bits 11 to bit 7 of the timer control status registers (TMCSR0 and TMCSR1) are used to select the operating mode of the 16-bit reload timer and set the operating conditions. This section describes bit 7: the MOD0 bit. s Timer control status register, upper part (TMCSR0, TMCSR1: H) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 TMSCR L bit0 TMCSR0 000083 H CSL1 CSL0 MOD2 MOD1 MOD0 R/W R/W R/W R/W R/W Initial value XXXX00000B TMCSR1 000087 H MOD2 MOD1 MOD0 0 0 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 Operating mode selection bit (Internal clock mode) Input pin function Trigger disabled Rising edge Trigger input Falling edge Both edges "L" level "H" level Valid edge and level Gate input MOD2 MOD1 MOD0 X X X X 0 0 1 1 0 1 0 1 Operating mode selection bit (Event clock mode) Input pin function Valid edge Rising edge Event input Falling edge Both edges CSL1 CSL0 0 0 R/W X 0 1 Count clock selection bit Function 21 / Internal clock mode 23 / 2 5/ Count clock (0.125 S) (0.5 S) (2.0 S) 1 0 Read/Write 1 1 Event clock mode Not used Undefined Initial value Machine cycle. Value in parentheres are for 16MHz machine clock External event input Figure 11.4-2 Timer control status register, upper part (TMCSR0, TMCSR1: H) 256 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series Table 11.4-1 Function description of each bit of the upper part of the timer control status register (TMCSR0, TMCSR1: H) Bit name bit15 bit14 bit13 bit12 Function Not used * When these bits are read, their values are undefined. * Writing to these bits has no effect on operation. * Selects the count clock. * When these bits are not set to "11B", internal clock mode is set. The * When these bits are set to "11B", event count mode is set. The external clock edges are counted in this mode. bit11 bit10 CSL1, CSL0: Count clock selection bits * The MOD2 bit is used to select input pin functions. * When the MOD2 bit is "0", the input pin is used as a trigger input MOD2, MOD1, MOD0: Operating mode selection bits pin, so that whenever a valid edge is input, the contents of the reload register are loaded into the counter and counting continues. The MOD1 and MOD0 bits are used to select the type of valid edge. * When the MOD2 bit is "1", the input pin becomes a gate, meaning that counting will continue only as long as a valid level signal is input. The MOD1 bit is an unused bit, and the MOD0 bit is used to select the valid level. bit9 bit8 bit7 MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 257 11.4 16-Bit Reload Timer Registers 11.4.2 Timer control status register, lower part (TMCSR0, TMCSR1: L) The lower seven bits of the timer control status registers (TMCSR0 and TMCSR1) are used to set operating conditions for the 16-bit reload timer, enable and disable operation, control interrupts, and check the status. s Timer control status register, low part (TMCSR0, TMCSR1: L) bit15 Address TMCSR0 000082H TMCSR1 000086H (TMCSR:H bit8 bit7 bit6 bit5 bit4 bit3 bit2 UF R/W bit1 bit0 Initial value 00000000B MOD0* OUTE OUTL RELD INTE R/W R/W R/W R/W R/W CNTE TRG R/W R/W TRG 0 1 CNTE 0 1 Software trigger bit No change, no effect on other bits After reloading, counting starts. Count enable bit Counting stopped Counting enabled (wait for the start trigger) Underflow interrupt request flag bit UF 0 1 INTE 0 1 RELD 0 1 During reading Without counter underflow With counter underflow During writing This bit is cleared. No change, no effect on other bits Interrupt request enable bit Interrupt request output disabled Interrupt request output enabled Reload selection bit One-shot mode Reload mode Pin output level selection bit OUTL In single-shot mode (RELD = 0) In reload mode (RELD = 1) 0 1 Square wave of H during counting Toggle output of L when counting is started. Square wave of L during count Toggle output of H when counting is started. Timer output enable bit OUTE Pin functions R/W: Read/write : Initial value 0 1 General-purpose port Timer output Registers and pins corresponding to each channel TMCSR0 P21 TO0 TMCSR1 P23 TO1 * : See Section 10.4.1, "Timer control status register, high part," for MOD0 (bit 7) Figure 11.4-3 Timer control status register, low part (TMCSR0, TMCSR1: L) 258 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series Table 11.4-2 Function description of each bit of the low part of the timer control status register (TMCSR0, TMCSR1: L) Bit name Function bit6 OUTE: Timer output enable bit * This bit enables or disables output from the timer output pin. * When this bit is "0", the pin functions as a general-purpose port. * In reload mode, the output waveform of this timer output pin toggles. In single-shot mode, the timer outputs a rectangular waveform that indicates that counting is in progress is output. When this bit is "1", the pin functions as a timer output pin. bit5 OUTL: Pin output level selection bit * This register is used to select the output level of the timer output * The output level of the pin is inverted depending on whether this bit is "0" or "1". pin. * This bit enables reloading. * When this bit is "1", the timer is in reload mode. At the same time an bit4 RELD: Reload selection bit underflow occurs, the contents of the reload register are loaded into the counter, and counting continues. * When this bit is "0", the timer is in single-shot mode. Counting stops when an underflow occurs. bit3 INTE: Interrupt request enable bit UF: Underflow interrupt request flag bit CNTE: Count enable bit * This bit enables or disables output of an interrupt request to the * When this bit and the interrupt request flag (UF) bit are "1", the timer outputs an interrupt request. CPU. bit2 * This bit is set to "1" when a counter underflow occurs. * Writing "0" to this bit clears it. Writing "1" to this bit does not change * This bit is also cleared when EI2OS is activated. * The bit enables or disables counting. * When this bit is set to "1", the counter is placed in trigger standby mode. When a trigger occurs, actual counting starts. the bit value and has no effect on other bits. bit1 * This bit starts the interval timer function or counter function with bit0 TRG: Software trigger bit * Writing "1" to this bit applies a software trigger, causing the contents of the reload register to be loaded into the counter and starting counter operation. Writing "0" to this bit has no effect. * Trigger input from this trigger is always valid when the CNTE bit is set to "1" regardless of the operating mode. software. MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 259 11.4 16-Bit Reload Timer Registers 11.4.3 16-bit timer register (TMR0, TMR1) The 16-bit timer register (TMR0, TMR1) is used to read the count value from the 16-bit down counter. s 16-bit timer register (TMR0, TMR1) Figure 10.4-4 shows the 16-bit timer registers (TMR0, TMR1). Address TMR0: 000085H TMR1: 000089H Initial value Address TMR0: 000084H TMR1: 000088H Initial value R: Read only X: Undefined Figure 11.4-4 16-bit timer register (TMR0, TMR1) The 16-bit timer register is used to read the counter value from the 16-bit down counter. When counting is enabled (TMCSR: CNTE = 1) to start counting, the value written to the 16-bit reload register is loaded into this register, and counting down starts. This register value is stored when the counter is in stop status (TMCSR: CNTE = 0). 260 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series 11.4 16-Bit Reload Timer Registers 11.4.4 16-bit reload register (TMRLR0, TMRLR1) The 16-bit reload register (TMRLR0, TMRLR1) sets a reload value in the 16-bit down counter. The value written to this register is loaded into the down counter, and the down counter starts with this value. s 16-bit reload register (TMRLR0, TMRLR1) Figure 11.4-5 shows the 16-bit reload registers (TMRLR0, TMRLR1). Address 000085H 000089H Initial value Address 000084H 000088H Initial value W: Write only X: Undefined Figure 11.4-5 16-bit reload register (TMRLR0, TMRLR1) The initial value of the counter is set in this register when counting is disabled (TMCSR: CNTE = 0), regardless of the operating mode of the 16-bit reload timer. When counting is enabled (TMCSR: CNTE = 1) and the counter is started, counting down starts from the value written to this register. In reload mode, the value set in the 16-bit reload register (TMRLR) is reloaded into the counter when an underflow occurs, and counting down continues. In single-shot mode, the counter stops at FFFFH when an underflow occurs. MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 261 11.5 16-Bit Reload Timer Interrupts The 16-bit reload timer is able to generate an interrupt request when an underflow of the counter is occurred. It is also coordinated with the extended intelligent I/O service (EI2OS). s 16-bit reload timer interrupts Table 11.5-1 lists the interrupt control bits and interrupt causes of the 16-bit reload timer. Table 11.5-1 Interrupt control bits and interrupt causes of the 16-bit reload timer 16-bit reload timer 0 Interrupt request flag bit Interrupt request enable bit Interrupt cause TMCSR0: UF TMCSR0: INTE 16-bit reload timer 1 TMCSR1: UF TMCSR: INTE Underflow of the 16-bit down counter (TMR1) Underflow of the 16-bit down counter (TMR0) In the 16-bit reload timer, the UF bit of the timer control status register (TMCSR) is set to 1 by an underflow (from 0000H to FFFFH) of the down counter. If an interrupt request is enabled (TMCSR: INTE = 1) in this operation, the interrupt request is output to the interrupt controller. s 16-bit reload timer interrupts and EI2OS Table 11.5-2 lists the 16-bit reload timer interrupts and EIOS. Table 11.5-2 16-bit reload timer interrupts and EI2OS Interrupt control register Register name ICR09 ICR10 Address Vector table address EI2OS Lower Upper Bank Channel Interrupt number 16-bit reload timer 0 (*1) 16-bit reload timer 1 (*2) #30 (1EH) #32 (20H) 0000B9H 0000BAH FFFF84H FFFF7CH FFFF85H FFFF7DH FFFF86H FFFF7EH : Available when ICR09 or the interrupt causes sharing the interrupt vector are not used. *1 The same interrupt number as that for 8-bit timer counter underflow and 16-bit reload timer 0 underflow. *2 The same interrupt number as that for 16-bit free-run timer overflow and 16-bit reload timer 1 underflow. 262 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series s EI2OS function of the 16-bit reload timer Since the 16-bit reload timer has a circuit that coordinates with EI 2OS, the counter can start EI2OS when an underflow occurs. However, EI2OS is available only when other peripheral functions sharing the interrupt control register (ICR) do not use interrupts. For example, when 16-bit reload timer 1 uses EIOS, interrupts of the 16-bit free-run timer must be disabled. MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 263 11.6 Operation of the 16-Bit Reload Timer This section describes the 16-bit reload timer settings and counter operating status. s 16-bit reload timer settings q Internal clock mode setting The setting shown in Figure 11.6-1 is required to operate this timer as an interval timer. Other than 11 Set the initial value (reload value) of the counter. : Used : Set 1. Figure 11.6-1 Internal clock mode setting q Event counter mode setting The setting shown in Figure 11.6-2 is required to operate this timer as an event counter. Set the initial value (reload value) of the counter. : Used : Set 1. : Set the bit corresponding to the pin used to 0. Figure 11.6-2 Event counter mode setting MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 264 s Counter operating status The counter status is determined by the CNTE bit of the timer control status register (TMCSR) and the internal WAIT signal. Possible settings include the stop status (STOP status), trigger wait status (WAIT status), and running status (RUN status). Figure 11.6-3 shows the transitions of these counter statuses. Reset CNTE = 0, WAIT = 1 STOP TIN: Input disabled TOT: General-purpose port Counter: The counter value is retained when the counter stops. Immediately after a reset, it is undefined. CNTE = 0 CNTE = 0 CNTE = 1 TRG = 0 CNTE = 1 TRG = 1 CNTE = 1, WAIT = 1 WAIT TIN: Only trigger input enabled TO: Output initial value Counter: The counter value is retained when the counter stops. Immediately after a reset, it is undefined until a value is loaded. TRG = 1 (Software trigger) External trigger from TIN UF = 1 & RELD = 0 (Single-shot mode) RUN CNTE = 1, WAIT = 0 TIN: Functions as TIN TO: Functions as TO Counter: Run UF = 1 & RELD = 1 (Reload mode) LOAD CNTE = 1, WAIT = 0 TRG = 1 (Software trigger) Loading ends. The contents of the reload register are loaded into the counter WAIT TRG CNTE UF RELD : : : : : : : State transition by hardware State transition by register access Wait signal (internal signal) Software trigger bit of timer control status register (TMCSR) Count enable bit of timer control status register (TMCSR) Underflow interrupt request flag bit of timer control status register (TMCSR) Reload selection bit of timer control status register (TMCSR) Figure 11.6-3 Counter status transition MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 265 11.6 Operation of the 16-Bit Reload Timer 11.6.1 Reload Mode (Internal Clock Mode) Synchronized with the internal count clock, the 16-bit reload timer is used for counting down of the 16-bit counter and generating an interrupt request to the CPU when the counter is underflow. It can also output a toggle waveform to the timer output pin. s Operation in reload mode (internal clock mode) When counting is enabled (TMCSR: CNTE = 1) and the timer is started by the software trigger bit (TMCSR: TRG) or external trigger, the value of the reload register (TMRLR) is loaded into the counter, and counting starts. If the count enable bit and software trigger bit are set to 1 simultaneously, counting starts simultaneously with the enabling of counting. When an underflow of the counter value (from "0000H" to "FFFFH") occurs, the value of the 16-bit reload register (TMRLR) is loaded into the counter, and counting continues. If the underflow interrupt request flag (UF) bit is set to "1" and the interrupt request enable (INTE) bit is "1", an interrupt request is generated. The timer can also output to the TO pin a toggle waveform, which is inverted for each underflow. q Software trigger operation When "1" is written to the TRG bit of the timer control status register (TMCSR), the counter is started. Figure 11.6-4 shows software trigger operation in reload mode. Count clock Counter Data load signal UF bit CNTE bit TRG bit TO pin T: Machine cycle Reload data Reload data Reload data Reload data * It takes 1T time from trigger input to loading of the reload data. Figure 11.6-4 Count operation in reload mode (software trigger operation) 266 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series q External trigger operation When a valid edge (rising, falling, and both edges can be selected) is input to the TIN pin, the counter is started. Figure 11.6-5 shows external trigger operation in reload mode. Count clock Reload data Counter Data load signal UF bit CNTE bit TIN pin TO pin T: Machine cycle Reload data Reload data Reload data * It takes 2T to 2.5T time from trigger input to loading of the reload data. Figure 11.6-5 Counting in reload mode (external trigger operation) Count clock Counter Data load signal Reload data Reload data CNTE bit TRG bit TIN pin TO pin T: Machine cycle * It takes 1T time from trigger input to loading of the reload data. Figure 11.6-6 Count operation in reload mode (software trigger and gate input operation) 11.6 Operation of the 16-Bit Reload Timer 11.6.2 Single-shot Mode (Internal Clock Mode) Synchronized with the internal count clock, the 16-bit reload timer is used for counting down of the 16-bit counter and generating an interrupt request to the CPU when the counter is underflow. It can also output to the TO pin a rectangular waveform indicating that counting is in progress. s Single-shot mode (Internal clock mode) When counting is enabled (TMCSR: CNTE = 1) and the timer is started with the software trigger bit (TMCSR: TRG) or external trigger, counting starts. If the count enable bit and software trigger bit are set to "1" simultaneously, counting starts simultaneously with the enabling of counting. When an underflow of the counter value (from "0000H" to "FFFFH") occurs, the counter stops in the "FFFFH" state. If the underflow interrupt request flag (UF) bit is set to "1" and the interrupt request enable (INTE) bit is "1", an interrupt request is generated. The timer can also output to the TO pin a rectangular waveform indicating that counting is in progress. q Software trigger operation When "1" is written to the TRG bit of the timer control status register (TMCSR), the counter is started. Figure 11.6-7 shows the software trigger operation in single-shot mode. Count clock Reload data Reload data Counter Data load signal UF bit CNTE bit TRG bit TO pin Wait for trigger input T: Machine cycle * It takes 1T time from trigger input to loading of the reload data. Figure 11.6-7 Count operation in single-shot mode (software trigger operation) 268 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series q External trigger operation When a valid edge (rising, falling, and both edges can be selected) is input to the TIN pin, the counter is started. Figure 11.6-8 shows external trigger operation in single-shot mode. Count clock Reload data Reload data Counter Data load signal UF bit CNTE bit TIN bit TO pin Wait for trigger input T: Machine cycle * It takes 2T to 2.5T time from external trigger input to loading of the reload data. Figure 11.6-8 Count operation in single-shot mode (external trigger operation) Count clock Reload data Reload data Counter Data load signal UF bit CNTE bit TRG bit T* TO pin Wait for trigger input T: Machine cycle * It takes 1T time from trigger input to loading of the reload data. Figure 11.6-9 Count operation in single-shot mode (software trigger and gate input operation) 11.6 Operation of the 16-Bit Reload Timer 11.6.3 Event count mode In the 16-bit reload timer, an input edge from the TIN pin is used to count down the 16bit counter and an interrupt request to the CPU is generated when the counter is underflow. It can also output a toggle waveform or rectangular waveform to the TO pin. s Event count mode When counting is enabled (TMCSR: CNTE = 1) and the counter is started (TMCSR: TRG = 1), the value of the reload register is loaded into the counter. Counting down is then done every time a valid edge (rising, falling, and both edges can be selected) of the pulse input to the TIN pin (external count clock) is detected. When the count enable bit and software trigger bit are set to "1" simultaneously, counting is started simultaneously with the enabling of counting. q Operation in reload mode When an underflow of the counter value (from "0000H" to "FFFFH") occurs, the value of the reload register (TMRLR) is loaded into the counter, and counting continues. If the underflow interrupt request flag (UF) bit is set to "1" and the interrupt request enable bit (TMCSR: INTE) is 1, an interrupt request is generated. The timer can also output to the TO pin a toggle waveform, which is inverted for each underflow. Figure 11.6-10 shows counting in reload mode. TIN pin Counter Data load signal UF bit CNTE bit TRG bit TO pin Reload data Reload data Reload data Reload data T: Machine cycle * It takes 1T time from trigger input to loading of the reload data. Figure 11.6-10 Count operation in reload mode (event count mode) 270 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series q Operation in single-shot mode When an underflow of the counter value (from "0000H" to "FFFFH") occurs, the counter stops in the FFFFH state. If the underflow interrupt request flag (UF) bit is set to "1" and the interrupt request enable (INTE) bit is "1", an interrupt request is generated. The timer can also output to the TO pin a rectangular waveform indicating that counting is in progress. Figure 11.6-11 shows counting in single-shot mode. TIN pin Counter Data load signal UF bit CNTE bit TRG bit TO pin Reload data Reload data Wait for trigger input T: Machine cycle * It takes 1T time from trigger input to loading of the reload data. Figure 11.6-11 Counter operation in single-shot mode (event count mode) MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 271 11.7 Usage Notes on the 16-Bit Reload Timer Notes on using the 16-bit reload timer are given below. s Usage notes on the16-bit reload timer q Notes on using a program for setting * Write a value to the 16-bit reload register (TMRLR) when counting stops (TMCSR: CNTE = 0). Also, a value can be read from the 16-bit timer register (TMR) even during counting, but always be sure to use a word transfer instruction (MOVW A, dir, etc.). Change the CSL1 and CSL0 bits of the timer control status register (TMCSR) when the counter has stopped (TMCSR: CNTE = 0). * q Notes about interrupts * When the UF bit of the timer control status register (TMCSR) is set to 1 and an interrupt request is enabled (TMCSR: INTE = 1), control cannot be returned from interrupt processing. Always clear the UF bit. Since the 16-bit reload timer 0 shares an interrupt vector with 8-bit timer 0/1/2, interrupt causes must be checked carefully by the interrupt processing routine when interrupts are used. Furthermore, when EI2OS is used by the 16-bit reload timer 0, 8-bit timer 0/1/2 interrupts must be disabled * Since the 16-bit reload timer 1 shares an interrupt vector with 16-bit free-run timer, interrupt causes must be checked carefully by the interrupt processing routine when interrupts are used. Furthermore, when EI2OS is used by the 16-bit reload timer 0, 16-bit free-run timer interrupts must be disabled * 272 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series 11.8 Sample Programs for the 16-Bit Reload Timer This section contains sample programs for the 16-bit reload timer in internal clock mode and event count mode. s Sample program in internal clock mode q Processing * * * * * A 25-ms interval timer interrupt is generated with 16-bit reload timer 0. The timer is used in reload mode to repeatedly generate an interrupt. The timer is started with a software trigger. External trigger input is not used. EI2OS is not used. 16 MHz is used for the machine clock, and 2s is used for the count clock. q Coding example ICR09 EQU 0000B9H ; Interrupt control register for the 16-bit reload timer TMCSR EQU 000082H ; Timer control status register TMR EQU 000084H ; 16-bit timer register TMRLR EQU 000084H ; 16-bit reload register UF EQU TMCSR0:2 ; Interrupt request flag bit CNTE EQU TMCSR0:1 ; Counter operation enable bit TRG EQU TMCSR0:0 ; Software trigger bit ;-------Main program-----------------------------------------------------------------------------------------------CODE CSEG START: ; : ; Assumes that stack pointer (SP) has already been ; initialized. AND CCR,#0BFH ; Interrupt disable MOV I:ICR09,#00H ; Interrupt level 0 (strongest) CLRB I:CNTE ; Temporary stopping of counter MOVW I:TMRLR0,#30D4H ; Sets data for 25-ms timer. MOVW I:TMCSR0,#00001000000011011B ; Interval timer operation, 2 s clock ; Disables external trigger and external output. ; Selects reload mode, and enables interrupts. ; Clears interrupt flag, and starts counter. MOV ILM,#07H ; Sets ILM in PS to level 7 OR CCR,#40H ; Interrupt enable LOOP: MOV A,#00H ; Endless loop MOV A,#01H ; BRA LOOP ; ;-------Interrupt program-------------------------------------------------------------------------------------------WARI: CLRB I:UF ; Clears interrupt request flag. ; : ; User processing ; : RETI ; Returns from interrupt MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 273 CODEENDS ;-------Vector setting-----------------------------------------------------------------------------------------------VECT CSEG ABS=0FFH ORG 0FF84H ; Sets vector for interrupt #29 (1DH). DSL WARI ORG 0FFDCH ; Sets reset vector DSL START DB 00H ; Sets single-chip mode. VECT ENDS END START s Sample program in event count mode q Processing * * * * When the rising edge of the pulse input to the external event input pin is counted 10,000 times with 16-bit reload timer/counter 0, an interrupt is generated. The timer operates in single-shot mode. External trigger input selects the rising edge. EI2OS is not used. q Coding example ICR09 EQU 0000B9H ; Interrupt control register for the 16-bit reload timer TMCSR EQU 000082H ; Timer control status register TMR EQU 000084H ; 16-bit timer register TMRLR EQU 000084H ; 16-bit reload register DDR2 EQU 000012H ; Port data register UF EQU TMCSR0:2 ; Interrupt request flag bit CNTE EQU TMCSR0:1 ; Counter operation enable bit TRG EQU TMCSR0:0 ; Software trigger bit ;-------Main program-----------------------------------------------------------------------------------------------CODE CSEG START: ; : ; Assumes that stack pointer (SP) has already been ; initialized. AND CCR,#0BFH ; Interrupt disable MOV I:ICR09,#00H ; Interrupt level 0 (strongest) MOV I:DDR2,#00H ; Sets P20/TIN0 pin to input. CLRB I:CNTE ; Temporary stopping of counter MOVW I:TMRLR0,#2710H ; Sets reload value to 10,000. MOVW I:TMCSR0,#0000110010001011B ; Counter operation, external trigger, rising ; Disables edge and external output. ; Selects single-shot mode and enables interrupts. ; Clears interrupt flag, starts counter. MOV ILM,#07H ; Sets ILM in PS to level 7. OR CCR,#40H ; Interrupt enable LOOP: MOV A,#00H ; Endless loop MOV A,#01H ; BRA LOOP ; 274 CHAPTER 11 16-BIT RELOAD TIMER MB90560 series ;-------Interrupt program-------------------------------------------------------------------------------------------WARI: CLRB I:UF ; Clears interrupt request flag. ; : ; User processing ; : RETI ; Returns from interrupt. CODE ENDS ;-------Vector setting------------------------------------------------------------------------------------------------VECTC SEG ABS=0FFH ORG 0FF84H ; Sets vector for interrupt #30 (1EH). DSL WARI ORG 0FFDCH ; Sets reset vector DSL START DB 00H ; Sets single-chip mode. VECT ENDS END START MB90560 series CHAPTER 11 16-BIT RELOAD TIMER 275 CHAPTER 12 MULTI-FUNCTION TIMER This chapter describes the functions and operation of the Multi-function timer in MB90560 series. 12.1 Overview of Multi-function Timer .................................................. 278 12.2 Block Diagram of Multi-function Timer.......................................... 280 12.3 Register of Multi-Function Timer................................................... 284 12.4 Operation of Multi-Function Timer ................................................ 324 12.1 Overview of Multi-function Timer The multi-function timer consists of a 16-bit free-run timer, six 16-bit output compare, four 16-bit input capture, 6 channels of 8-bit PPG timer (3 channels of 16-bit PPG timer) and a waveform generator. By using this waveform generator, 12 independent waveform can be outputted through 16-bit free-run timer. Furthermore input pulse width measurement and external clock cycle measurement can be done. s 16-bit free-run timer (X1) The 16-bit free-run timer consists of a 16-bit up-counter, control register, 16-bit compare clear register and a prescaler. The output value of this counter will be used as the count clock of the output compares and input captures * * * 6 types of counter operation clock (, /2, /4, /8, /16, /32, /64 /128) can be selected. : Internal clock An interrupt is generated when there is an overflow in the counter value or comparing match with compare clear register (Mode setting is necessary for compare match) Reset, software clear, compare match with compare clear register will reset the counter value to "0000H" s Output compare (X6) The output compare consists of six 16-bit compare registers, compare output latch and compare control registers. An interrupt is generated and output level is inverted when the value of 16-bit free run timer and compare register are matched. * * * * 6 compare registers can be operated independently. Output pins and interrupt flag are corresponding to each compare register. 2 compare register can be paired to control the output pins. Inverts output pins by using 2 compare register together. Setting the initial value for each output pin is possible. An interrupt is generated when compare register is matched. s Input capture (x4) Input capture consists of 4 independent external input pins, the corresponding capture register and capture control register. By detecting any edge of the input signal from the external pin, the value of the 16-bit free-run timer can be stored in the capture register and an interrupt is generated simultaneously. * * * 3 types of trigger edge (rising edge, falling edge, both edge) of the external input signal can be selected. 4 input captures can operated independently. An interrupt is generated by detecting a valid edge from external input. 278 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series s 8/16-bit PPG timer (8-bit PPG x 6, 16-bit PPG x 3) 8/16-bit PPG timer consists of six 8-bit down-counter, twelve 8-bit re-load register and three 8-bit control register. By using it as 8/16-bit re-load timer, it is possible to operate as an event counter. By setting of 8/16-bit "L" width and `H' width, it is possible to output a pulse with any cycle duty ratio. * * * 8-bit PPG output operation mode 6 channels of 8-bit PPG output can be operated independently. 16-bit PPG output operation mode 3 channels of 16-bit PPG output can be operated independently. 8+8-bit PPG output operation mode In this mode, Ch/0/Ch2/Ch4 can be operated as an 8-bit prescaler, in which an underflow output of Ch/0/Ch2/Ch4 is used as a count clock for Ch1/Ch3/Ch5. It is possible to output any cycle from any 8-bit PPG output. PPG output operation The 8/16-bit PPG timer can output pulse waveforms with variable period and duty ratio. Also, it can be used as D/A converter in conjunction with an external circuit. * s Waveform generator The waveform generator consists of three 8-bit re-load registers, three timer control registers and 8-bit waveform control register. With waveform generator, it is possible to generate realtime output, 8/16-bit PPG waveform output, non-overlap 3-phase waveform output for inverter control and DC chopper waveform output. * * * * It is possible to generate a non-overlap waveform output based on dead-time of 8-bit timer. (Dead-time timer function) It is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel mode.(Dead-time timer function) By detecting realtime output compare match, GATE signal of the PPG timer operation will be generated to start or stop PPG timer operation. (GATE function) When a match is detected by real-time output compare, the 8-bit timer is activated. The PPG timer can be started or stopped easily by generating a GATE signal for PPG operation until the 8-bit timer stops. (GATE function) Forced stop control using DTTI pin input External pin control can be performed through clockless DTTI pin input even when oscillation is stopped. (The pin level can be set by each pin or software.) * MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 279 12.2 Block Diagram of Multi-function Timer Block diagram of multi-function timer is shown in the section. s Realtime I/O Block Diagram Interrupt #31 (1FH) IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Pre-scaler Clock 16-bit free-run timer 16-bit compare clear register Compare register 0/2/4 Compare circuit Interrupt #34 (22H) ICLR ICRE A/D MSI3~0 Compare Circuit F2MC-16LXBUS Compare register 1/3/5 T Q RT0/2/4 (Waveform Generator) CMOD Compare Circuit IOP1 IOP0 IOE1 T IOE0 Q RT1/3/5 (Waveform Generator) Interrupt #13, #17, #21 #15, #19, #23 IN0/2 Capture register 0/2 Edge Detect EG11 EG10 EG01 EG00 Capture register 1/3 Edge Detect IN1/3 ICP0 ICP1 ICE0 ICE1 Interrupt #33, #35 #33, #35 Figure 12.2-1 BLock Diagram of Realtime I/O 280 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series s 8/16-bit PPG timer block Diagram PC02 PC01 PC00 POS0 PEN0 SST0 POE0 PUF0 PIE0 Selector Pre-scaler Control circuit GATE0/1 PCNT0 (Down Counter) reload Selector Ch1/3/5 port PPG0/2/4 Interrupt #14, #18, #22 F2MC-16LXBUS PRLL0/2/4* PRLBH0/2/4 PRLH0/2/4* PC102 PC11 PC10 POS1 PEN1 SST1 POE1 PUF1 PIE1 Ch0/2/4 Selector Pre-scaler Control circuit GATE1 Interrupt #16, #20, #24 PCNT0 (Down Counter) reload Selector PPG1/3/5 PRLL1/3/5* PRLBH1/3/5 PRLH1/3/5* * : PRLL0/2/4, PRLH0/2/4. PRLL1/3/5 and PRLH1/3/5 are PPG reload registers. Figure 12.2-2 Block Diagram of 8/16-bit PPG Timer MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 281 s Waveform Generator Block Diagram Pre-scaler Clock DCK2 DCK1 DCK0 TMD1 TMD0 NRSL DTIL DTIE DTTI Control Circuit DTTI GATE0/1 (PPG timer) RT0 RT1 8-bit timer Compare circuit TO0 Waveform Generator TO1 RTO0/U Selector RTO1/X Selector U 8-bit reload register 0 Dead-time Generator X GATE2/3 (PPG timer) F2MC-16LXBUS RT2 RT3 8-bit timer Compare circuit TO0 Waveform Generator TO1 RTO2/V Selector RTO3/Y Selector V 8-bit reload register 1 Dead-time Generator Y GATE4/5 (PPG timer) RT4 RT5 8-bit timer Compare circuit Waveform Generator TO4 TO5 RTO4/W Selector RTO5/Z Selector W 8-bit reload register 2 Dead-time Generator Z PPG selection circuit PGS1, PGS0 PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 Figure 12.2-3 Block Diagram of Waveform Generator 282 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Memo MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 283 12.3 Register of Multi-Function Timer This section describes registers of multi-function timer. s 16-bit Free-Run Timer Registers Compare Clear Register (Upper) 15 Address: 000059H Read/write Initial value CL15 R/W X 14 CL14 R/W X 13 CL13 R/W X 12 CL12 R/W X 11 CL11 R/W X 10 CL10 R/W X 9 CL09 R/W X 8 CL08 R/W X Bit Number CPCLR Compare Clear Register (Lower) 7 Address: 000058H Read/write Initial value Timer Data Register (Upper) 15 Address: 00005BH Read/write Initial value T15 R/W 0 14 T14 R/W 0 13 T13 R/W 0 12 T12 R/W 0 11 T11 R/W 0 10 T10 R/W 0 9 T09 R/W 0 8 T08 R/W 0 Bit Number TCDT CL07 R/W X 6 CL06 R/W X 5 CL05 R/W X 4 CL04 R/W X 3 CL03 R/W X 2 CL02 R/W X 1 CL01 R/W X 0 CL00 R/W X Bit Number CPCLR Timer Data Register (Lower) 7 Address: 00005AH Read/write Initial value T07 R/W 0 6 T06 R/W 0 5 T05 R/W 0 4 T04 R/W 0 3 T03 R/W 0 2 T02 R/W 0 1 T01 R/W 0 0 T00 R/W 0 Bit Number TCDT Timer Control Status Register (Upper) 15 Address: 00005DH Read/write Initial value ECKE R/W 0 R/W X R/W X 14 13 12 MSI2 R/W 0 11 MSI1 R/W 0 10 MSI0 R/W 0 9 ICLR R/W 0 8 ICRE R/W 0 Bit Number TCCS Timer Control Status Register (Lower) 7 Address: 00005CH Read/write Initial value IVF R/W 0 6 IVFE R/W 0 5 STOP R/W 0 4 3 2 CLK2 R/W 0 1 CLK1 R/W 0 0 CLK0 R/W 0 Bit Number MODE SCLR R/W 0 R/W 0 TCCS Figure 12.3-1 Registers of 16-bit Free-Run Timer 284 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series s Output Compare Registers Compare Register (Upper) Address: ch0 000071H ch1 000073H ch2 000075H ch3 000077H ch4 000079H ch5 00007BH Read/write Initial value Compare Register (Lower) Address: ch0 000070H ch1 000072H ch2 000074H ch3 000076H ch4 000078H ch5 00007AH Read/write Initial value 15 OP15 R/W X 14 13 OP12 R/W X 12 OP11 R/W X 11 OP10 R/W X 10 9 8 Bit number OCCP0~5 OP14 OP13 R/W X R/W X OP09 OP08 R/W X R/W X 7 OP07 R/W X OP06 R/W X 6 OP05 R/W X 5 OP04 R/W X 4 3 2 1 0 Bit number OCCP0~5 OP03 OP02 R/W X R/W X OP01 OP00 R/W X R/W X Compare Control Register (Upper) 15 Address: ch1 00007DH ch3 00007FH ch5 000081H Read/write Initial value R/W X R/W X R/W X 14 13 12 11 10 9 8 Bit number OCS1/3/5 CMOD OTE1 OTE0 R/W 0 R/W 0 R/W 0 OTD1 OTD0 R/W 0 R/W 0 Compare Control Register (Lower) 7 Address: ch0 00007CH ch2 00007EH ch4 000080H Read/write Initial value IOP1 R/W 0 IOP0 R/W 0 6 IOE1 R/W 0 5 IOE0 R/W 0 R/W X R/W X 4 3 2 1 0 Bit number OCS0/2/4 CST1 CST0 R/W 0 R/W 0 Figure 12.3-2 Registers of Output Compare MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 285 s Input capture registers Input Capture Register (Upper) Address: ch0 000061H ch1 000063H ch2 000065H ch3 000067H Read/write Initial value 15 CP15 R/W X CP14 R/W X 14 CP13 R/W X 13 CP12 R/W X 12 CP11 R/W X 11 CP10 R/W X 10 CP09 R/W X 9 CP08 R/W X 8 Bit number IPCP0~3 Input Capture Register (Lower) Address: ch0 000060H ch1 000062H ch2 000064H ch3 000066H Read/write Initial value Capture Control Register (Upper) 15 Address: 000069H Read/write Initial value ICP3 R/W 0 14 ICP2 R/W 0 13 ICE3 R/W 0 12 ICE2 R/W 0 11 EG31 R/W 0 10 EG30 R/W 0 9 EG21 R/W 0 8 EG20 R/W 0 Bit Number ICS23 7 CP07 R/W X CP06 R/W X 6 CP05 R/W X 5 CP04 R/W X 4 3 2 CP01 R/W X 1 CP00 R/W X 0 Bit number IPCP0~3 CP03 CP02 R/W X R/W X Capture Control Register (Lower) 7 Address: 000068H Read/write Initial value ICP1 R/W 0 6 ICP0 R/W 0 5 ICE1 R/W 0 4 ICE0 R/W 0 3 EG11 R/W 0 2 EG10 R/W 0 1 EG01 R/W 0 0 EG00 R/W 0 Bit Number ICS01 Figure 12.3-3 Registers of 16-bit Input Capture 286 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series s 8/16-bit PPG Timer Registers PPG Reload Register (Upper) Address: ch0 000039H ch1 00003BH ch2 000041H ch3 000043H ch4 000049H ch5 00004BH Read/write Initial value PPG Reload Register (Lower) Address: ch0 000038H ch1 00003AH ch2 000040H ch3 000042H ch4 000048H ch5 00004AH Read/write Initial value PPG1/3/5 Control Register 15 Address: ch1 00003DH ch3 000045H ch5 00004DH Read/write Initial value PPG0/2/4 Control Register 7 Address: ch0 00003CH ch2 000044H ch4 00004CH Read/write Initial value PPG Clock Control Register 7 Address: ch0,1 00003EH ch2,3 000046H ch4,5 00004EH Read/write Initial value PC12 R/W 0 PC11 R/W 0 6 PC10 R/W 0 5 PC02 R/W 0 4 3 2 1 0 Bit number PCS01/23/45 PC01 PC00 R/W 0 R/W 0 R/W X R/W X PEN0 R/W 0 SST0 R/W 0 6 5 4 3 2 1 Reserved 15 14 13 12 11 10 9 8 Bit number PRLH0~5 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 7 6 5 4 3 2 1 0 Bit number PRLL0~5 R/W X R/W X 14 R/W X 13 R/W X 12 R/W X 11 R/W X 10 R/W X 9 R/W X 8 Bit number PPGC1/3/5 PEN1 R/W 0 SST1 R/W 0 POE1 PIE1 R/W 0 R/W 0 PUF1 MD01 R/W 0 R/W 0 MD00 R/W 0 Reserved R/W 1 0 Bit number PPGC0/2/4 POE0 PIE0 R/W 0 R/W 0 PUF0 POS1 POS0 R/W 0 R/W 0 R/W 0 R/W 1 Figure 12.3-4 Registers of 8/16-bit PPG Timers MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 287 s Waveform Generator Registers 8-bit Reload Register 7 Address: ch0 000050H ch1 000052H ch2 000054H Read/write Initial value 8-bit timer Control Register 15 Address: ch0 000051H ch1 000053H ch2 000055H Read/write Initial value 14 13 12 TMIE R/W 0 11 10 9 8 Bit number DTCR0/1/2 DMOD GTEN PGEN TMIF R/W 0 R/W 0 R/W 0 R/W 0 TMD2 TMD1 TMD0 R/W 0 R/W 0 R/W 0 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 Bit number TMRR0/1/2 Waveform Control Register 7 Address: 000056H Read/write Initial value DTIE R/W 0 6 DTIL R/W 0 5 NRSL R/W 0 4 DCK2 R/W 0 3 DCK1 R/W 0 2 DCK0 R/W 0 1 PGS1 R/W 0 0 PGS0 R/W 0 Bit Number SIGCR Figure 12.3-5 Registers of Waveform Generator 288 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Memo MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 289 12.3 Registers of Multi-function timer 12.3.1 Registers of 16-bit Free-Run Timer This section describe registers of 16-bit free-run timer and register details. Those register are compare clear registers, timer data register and timer control status register. s 16-bit Free-Run Timer Registers Compare Clear Register (Upper) 15 Address: 000059H Read/write Initial value CL15 R/W X 14 CL14 R/W X 13 CL13 R/W X 12 CL12 R/W X 11 CL11 R/W X 10 CL10 R/W X 9 CL09 R/W X 8 CL08 R/W X Bit Number CPCLR Compare Clear Register (Lower) 7 Address: 000058H Read/write Initial value Timer Data Register (Upper) 15 Address: 00005BH Read/write Initial value T15 R/W 0 14 T14 R/W 0 13 T13 R/W 0 12 T12 R/W 0 11 T11 R/W 0 10 T10 R/W 0 9 T09 R/W 0 8 T08 R/W 0 Bit Number TCDT CL07 R/W X 6 CL06 R/W X 5 CL05 R/W X 4 CL04 R/W X 3 CL03 R/W X 2 CL02 R/W X 1 CL01 R/W X 0 CL00 R/W X Bit Number CPCLR Timer Data Register (Lower) 7 Address: 00005AH Read/write Initial value T07 R/W 0 6 T06 R/W 0 5 T05 R/W 0 4 T04 R/W 0 3 T03 R/W 0 2 T02 R/W 0 1 T01 R/W 0 0 T00 R/W 0 Bit Number TCDT Timer Control Status Register (Upper) 15 Address: 00005DH Read/write Initial value ECKE R/W 0 R/W X R/W X 14 13 12 MSI2 R/W 0 11 MSI1 R/W 0 10 MSI0 R/W 0 9 ICLR R/W 0 8 ICRE R/W 0 Bit Number TCCS Timer Control Status Register (Lower) 7 Address: 00005CH Read/write Initial value IVF R/W 0 6 IVFE R/W 0 5 STOP R/W 0 4 3 2 CLK2 R/W 0 1 CLK1 R/W 0 0 CLK0 R/W 0 Bit Number MODE SCLR R/W 0 R/W 0 TCCS Figure 12.3.1-1 Registers of 16-bit Free-Run Timer 290 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series 12.3.1 Registers of 16-bit Free-run Timer 12.3.1.1 Compare Clear Register (CPCLR) Compare clear register (CPCLR) is 16-bit register. When this register is matched with the count value of 16-bit free-run timer, the 16-bit free-run timer will be reset to "0000H". s Compare Clear Register (CPCR) Compare Clear Register (Upper) 15 Address: 000059H Read/write Initial value CL15 R/W X 14 CL14 R/W X 13 CL13 R/W X 12 CL12 R/W X 11 CL11 R/W X 10 CL10 R/W X 9 CL09 R/W X 8 CL08 R/W X Bit Number CPCLR Compare Clear Register (Lower) 7 Address: 000058H Read/write Initial value CL07 R/W X 6 CL06 R/W X 5 CL05 R/W X 4 CL04 R/W X 3 CL03 R/W X 2 CL02 R/W X 1 CL01 R/W X 0 CL00 R/W X Bit Number CPCLR Figure 12.3.1.1-1 Compare Clear Register (CPCR) Compare Clear Register is 16-bit register and is used to compare the count value of the 16-bit free-run timer. The initial value of this register is undetermined, so that the register must be set a value before starting an operation. Word access instruction to this register is recommended. When this register is matched with the count value of 16-bit free-run timer, 16-bit free-run timer will be reset to "0000 H" and the compare clear interrupt flag will be set. Furthermore, when the interrupt operation is enabled, interrupt request will be sent to the CPU. MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 291 12.3.1 Registers of 16-bit Free-run Timer 12.3.1.2 Timer Data Register (TCDT) The timer data register (TCDT) is used to read the count value of 16-bit free-run timer. s Timer Data Register (TCDT) Timer Data Register (Upper) 15 Address: 00005BH Read/write Initial value T15 R/W 0 14 T14 R/W 0 13 T13 R/W 0 12 T12 R/W 0 11 T11 R/W 0 10 T10 R/W 0 9 T09 R/W 0 8 T08 R/W 0 Bit Number TCDT Timer Data Register (Lower) 7 Address: 00005AH Read/write Initial value T07 R/W 0 6 T06 R/W 0 5 T05 R/W 0 4 T04 R/W 0 3 T03 R/W 0 2 T02 R/W 0 1 T01 R/W 0 0 T00 R/W 0 Bit Number TCDT Figure 12.3.1.2-1 Timer Data Register The timer data register is used to read the count value of the 16-bit free-run timer. The counter value is cleared to '0000' upon a reset. The timer value can be set by writing a value to this register. However, ensure that the value is written while the operation is stopped (STOP=1). Word access instruction to the timer data register is recommended. The 16-bit free-run timer is initialized upon the following factors: * * * Reset Clear bit (CLR) of control status register A match between compare clear register and the timer counter value (This can be performed only in an appropriate mode.) 292 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Memo MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 293 12.3.1 Registers of 16-bit Free-run Timer 12.3.1.3 Timer Control Status Register (TCCS) The timer control status register (TCCS) is 16-bit register and used to control the operation of 16-bit free-run timer s Timer control status register (Upper) Address 00005DH Bit 15 ECKE R/W Bit 14 -- -- Bit 13 -- -- Bit 12 MSI2 R/W Bit 11 MSI1 R/W Bit 10 MSI0 R/W Bit 9 ICLR R/W Bit 8 ICRE R/W Initial value 0XX00000B ICRE 0 1 Compare interrupt request enable bit Enable interrupt request Disable interrupt request Compare interrupt request flag bit SC11 Read 0 1 Count value and set value is not matched Count value and set value is match Write Clear this bit No effect MSI2 MSI1 MSI0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Masking interrupt bits Interrupt is generated when 1st match Interrupt is generated when 2nd match Interrupt is generated when 3rd match Interrupt is generated when 4th match Interrupt is generated when 5th match Interrupt is generated when 6th match Interrupt is generated when 7th match Interrupt is generated when 8th match ECKE X : Indeterminate : Initial value -- : not used 0 1 Select Internal clock Clock selection bit Select external clock from FRCK pin R/W : Read and write Figure 12.3.1.3-1 Timer Control Status Register (Upper) 294 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.1.3-1 Timer Control Status Register (Upper) Bit Bit Function Bit 15 * This bit is used to select either external or internal count clock source for the 16-bit free-run timer. Change this bit when the output compare and input capture are in stop status because ECKE: the clock will be changed as soon as this bit is changed. Clock Selection Note: When selecting internal clock, set the count clock to bit bit 2~0 (CLK2~0). This count clock will become the base clock. When inputting clock from FRCK pin, set DDR1:bit7="0" * The read value is indeterminate. * Writing to this bit has no effect on the operation. * These bits are used to set the number of times of masking the compare clear interrupt. 16-bit free-run timer will reload the count value every time when these 3 bits is not "000B" and the 3 bits will be decrement by 1 until these 3 bits becomes "000B". The number of masking interrupt = the value of these 3 bits. (i.e. When masking two times and interrupt is generated in the 3rd time of the match, set the value = "010B". However, there is no masking interrupt when the value is "000B". Bit 14 Bit 13 Unused bit Bit 12 Bit 11 Bit 10 MIS2~0: Masking interrupt bit Bit 9 * This bit is an interrupt request flag for compare clear. * When the compare clear register and 16-bit free-run timer value ICLR: are matched and the counter is cleared, this bit will become "1". Compare * Interrupt is generated when the interrupt request enable bit Interrupt (Bit8: ICRE) is set to "1". request flag bit * Writing "0" will clear this bit. * Writing "1" has no effect. * In Read-Modify-Write operation, "1" is always read. ICRE: Compare * This is the interrupt request enable bit for the compare clear. Interrupt * When this bit is "1" and the interrupt flag (Bit9: ICLR) is set to request enable "1", an interrupt will be generated. bit Bit 8 MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 295 s TImer control status register (Lower) Address 00005CH Bit 7 IVF R/W Bit 6 IVFE R/W Bit 5 STOP R/W Bit 4 MODE R/W Bit 3 SCLR R/W Bit 2 CLK2 R/W Bit 1 CLK1 R/W Bit 0 CLK0 R/W Initial value 00000000B Clock frequency selection bit CLK2 CLK1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 CLK0 0 1 0 1 0 1 0 1 Count clock /2 /4 /8 /16 /32 /64 /128 = 16MHz = 8MHz = 4MHz = 1MHz 62.5 ns 125 ns 0.25 s 0.5 s 1 s 2 s 4 s 8 s 125 ns 0.25 s 0.5 s 1 s 2 s 4 s 8 s 16 s 0.25 s 0.5 s 1 s 2 s 4 s 8 s 16 s 32 s 1 s 2 s 4 s 8 s 16 s 32 s 64 s 128 s : Machine cycle Clear bit SCLR Write 0 1 MODE 0 1 No effect Initialize counter to "0000H" Always read "0" Read Initialization condition bit Initialize counter by reset and clear bit (bit3: SCLR) Initialize counter by reset, clear bit (bit3: SCLR) and match values with compare register 5 of output compare. Counter enable bit Counting is enabled (operation) Counting is disabled (Stop) Timer interrupt request enable bit Interrupt is disabled Interrupt is enabled Timer interrupt request flag bit STOP 0 1 IVFE 0 1 IVF Read R/W : Read and Write : Initial value 0 1 No interrupt Request Has interrupt request Write Clear this bit No effect Figure 12.3.1.3-2 Timer Control Status Register (Lower) 296 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.1.3-2 Timer Control Status Register (Lower) Bit Function Bit 7 * This bit is an interrupt request flag for 16-bit free-run timer. * This bit will be set to "1" when the 16-bit free-run timer is IVF: overflow. Timer Interrupt * Interrupt will be generated when the timer interrupt request request enable bit (Bit6: IVFE) is set to "1". flag bit * Writing "0" will clear this bit. * Writing "1" has no effect. * In Read-Modify-Write operation, "1" is always read. IVFE: * This is the interrupt request enable bit for 16-bit free-run timer Timer interrupt clear. request enable * When this bit is "1" and the timer interrupt request flag bit (Bit7: bit ICLR) is set to "1", an interrupt will be generated. * This bit is used to stop/start the counting of the 16-bit free-run timer. * Writing "1" to this bit will stop the counting of the 16-bit free-run STOP: timer Counter enable * Writing "0" to this bit will start the counting of the 16-bit free-run bit timer. Note: When the 16-bit free-run timer is stopped, the output compare operation will be also stopped * This bit is used to set the initializing condition for the 16-bit freerun timer. * When it is "0", 16-bit free-run counter will be initialized by the reset and the clear bit reset (bit 3:SCLR). * When it is "1", 16-bit free-run timer will be initialized by not only the reset and the clear bit reset (bit 3:SCLR), but also when the count value is matched with the compare clear register. Note: Initialization of the counter value will be at the changing point of the count value. * This bit is used to initialize the 16-bit free-run time to the value of "0000H". * Writing "1" will initialize 16-bit free-run counter to "0000H" * Writing "0" has no meaning. * Read value is always "0" Note: Initialization of the counter value will be at the changing point of the count value. Note: If the initialization when the counter is stopped, write "0000H" to the data register. * This bit is used to select count clock for the 16-bit free-run timer. Change this bit when the output compare and input capture are in stop status because the clock will be changed as soon as this bit is changed. Bit 6 Bit 5 Bit 4 MODE: Initialization condition bit Bit 3 SCLR: Clear bit Bit 2 Bit 1 Bit 0 CLK2~0: Clock frequency section bit MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 297 12.3 Registers of Multi-Function Timer 12.3.2 Registers of 16-bit Output Compare This section describe registers of 16-bit output compare and register details. s Output Compare Registers Compare Register (Upper) Address: ch0 000071H ch1 000073H ch2 000075H ch3 000077H ch4 000079H ch5 00007BH Read/write Initial value Compare Register (Lower) Address: ch0 000070H ch1 000072H ch2 000074H ch3 000076H ch4 000078H ch5 00007AH Read/write Initial value 15 OP15 R/W X OP14 R/W X 14 OP13 R/W X 13 OP12 R/W X 12 OP11 R/W X 11 OP10 R/W X 10 OP09 R/W X 9 OP08 R/W X 8 Bit number OCCP0~5 7 OP07 R/W X OP06 R/W X 6 OP05 R/W X 5 OP04 R/W X 4 3 2 OP01 R/W X 1 OP00 R/W X 0 Bit number OCCP0~5 OP03 OP02 R/W X R/W X Compare Control Register (Upper) 15 Address: ch1 00007DH ch3 00007FH ch5 000081H Read/write Initial value R/W X R/W X R/W X 14 13 12 11 10 9 8 Bit number OCS1/3/5 CMOD OTE1 OTE0 R/W 0 R/W 0 R/W 0 OTD1 OTD0 R/W 0 R/W 0 Compare Control Register (Lower) 7 Address: ch0 00007CH ch2 00007EH ch4 000080H Read/write Initial value IOP1 R/W 0 IOP0 R/W 0 6 IOE1 R/W 0 5 IOE0 R/W 0 R/W X R/W X 4 3 2 CST1 R/W 0 1 CST0 R/W 0 0 Bit number OCS0/2/4 Figure 12.3.2-1 Registers of Output Compare 298 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series 12.3.2 Registers of 16-bit Output Compare 12.3.2.1 Compare Registers (OCCP0~5) Compare registers (OCCP0~5) are used to set the compare value for the 16-bit free-run timer. s Compare Registers (OCCP0~5) Compare Register (Upper) Address: ch0 000071H ch1 000073H ch2 000075H ch3 000077H ch4 000079H ch5 00007BH Read/write Initial value Compare Register (Lower) Address: ch0 000070H ch1 000072H ch2 000074H ch3 000076H ch4 000078H ch5 00007AH Read/write Initial value 15 OP15 R/W X OP14 R/W X 14 OP13 R/W X 13 OP12 R/W X 12 11 10 OP09 R/W X 9 OP08 R/W X 8 Bit number OCCP0~5 OP11 OP10 R/W X R/W X 7 OP07 R/W X 6 5 OP04 R/W X 4 3 2 OP01 1 OP00 0 Bit number OCCP0~5 OP06 OP05 R/W X R/W X OP03 OP02 R/W X R/W X R/W R/W X X Figure 12.3.2.1-1 Compare Registers (OCCP0~5) The compare registers (OCCP0~5) are 16-bit registers which are used to compare the count value of 16-bit free run timer. The initial values of the compare registers (OCCP0~5) are undetermined, so that the value must be set before enabling the operation. Word access instruction to this register is recommended. When the value of this register matches that of the 16-bit free-run timer, a compare signal is generated to set the output compare interrupt flag. If output is enabled, the output level (RT0~5) corresponding to the compare register (OCCP0~5) is reversed. MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 299 12.3.2 Registers of 16-bit Output Compare 12.3.2.2 Compare Control Registers (OSC0/1/2/3/4/5) Compare control register is used to control the output level, output enable, output reverse mode, compare operation enable, compare match interrupt enable and compare match interrupt flag for RTO0~5. s Compare control register (Upper, OSC1/3/5) Address ch1: 00007DH Ch3: 00007FH Ch5: 000081H Bit 15 -- -- Bit 14 -- -- Bit 13 -- -- Bit 12 CMOD R/W Bit 11 OTE1 R/W Bit 10 OTE0 R/W Bit 9 OTD1 R/W Bit 8 OTD0 R/W Initial value XXX00000B OTD0 0 1 OTD1 0 1 OTE0 0 1 OTE1 0 1 CMOD 0 X : Indeterminate : Initial value -- : not used 1 Output level bit Output "0" for RT0/RT2/RT4 Output "1" for RT0/RT2/RT4 Output level bit Output "0" for RT1/RT3/RT5 Output "1" for RT1/RT3/RT5 Output enable bit General-purpose port (port 30/32/34) Output compare output pin (RT0/RT2/RT4) Output enable bit General-purpose port (Port 31/33/35) Output compare output pin (RT1/RT3/RT5) Output level reverse mode bit RT0/2/4: The level is reversed upon a match with compare register 0/ 2/ 4. RT1/3/5: The level is reversed upon a match with compare register 1/3/5 respectively RT0/2/4: The level is reversed upon a match with compare register 0/2/4. RT1/3/5: The level is reversed upon a match with compare register 0 or 1, 2 or 3, 4 or 5. R/W : Read and write Figure 12.3.2.2-1 Compare Control Register (Upper, OSC1/3/5) 300 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.2.2-1 Compare Control Register (Upper, OSC1/3/5) Bit Bit Bit 15 Bit 14 Bit 13 Unused bit Function * The read value is indeterminate. * Writing to this bit has no effect on the operation. * CMOD is used to switch the pin output level reverse mode upon a match while pin output is enabled (OTE1=1 or OTE0=1). * When CMOD=0 (default), the output level of the pin is reversed upon a match with corresponding compare register. RT0/2/4: The level is reversed upon a match between the 16-bit free-run timer and compare register 0/2/4. RT1/3/5: The level is reversed upon a match between the 16-bit free-run timer and compare register 1/3/5. * When CMOD=1, the output level of the pin corresponding to compare register is reversed as same as when CMOD=0. However, the output level of the pin (RT1) corresponding to compare register 1 is reversed only when a match is detected in both compare register 0 and 1. If compare registers 0 and 1 have the same value, the same operation as when only one compare register is used. RT0/2/4: The level is reversed upon a match between the 16-bit free-run timer and compare register 0/2/4. RT1/3/5: The level is reversed upon a match between the 16-bit free-run timer and compare register 0 or 1, 2 or 3, 4 or 5. * This bit is used to enable output compare pin output for output compare 1/3/5. * The initial value for these bits is '0'. Note: The output enable bit of the waveform generator must be set when dead-time timer is used in the waveform generator. * This bit is used to enable output compare pin output for output compare 0/2/4. * The initial value for these bits is '0.' Note: The output enable bit of the waveform generator must be set when dead-time timer is used in the waveform generator. * This bit is used to change the pin output level for output compare 1/3/5 when the output compare pin output is enabled. * The initial value of the compare pin output is '0.' * Ensure that the compare operation is stopped before a value is written. When reading this bit, this bit indicate the output compare pin output value * This bit is used to change the pin output level for output compare 0/2/4 when the output compare pin output is enabled. * The initial value of the compare pin output is '0.' * Ensure that the compare operation is stopped before a value is written. When reading this bit, this bit indicates the output compare pin output value. CHAPTER 12 MULTI-FUNCTION TIMER 301 Bit 12 CMOD: Output Level reverse mode bit Bit 11 OTE1: Output enable bit Bit 10 OTE0: Output enable bit Bit 9 OTD1: Output level bit Bit 8 OTD0: Output level bit MB90560 series s Compare control register (Lower, OSC0/2/4) Address ch0: 00007CH ch2: 00007EH ch4: 000080H Bit 7 IOP1 R/W Bit 6 IOP0 R/W Bit 5 IOE1 R/W Bit 4 IOE0 R/W Bit 3 -- -- Bit 2 -- -- Bit 1 CST1 R/W Bit 0 CST0 R/W Initial value 00000000B CST0 0 1 Compare operation enable bit Disable compare operation for compare register 0/2/4 Enable compare operation for compare register 0/2/4 CST1 0 1 Compare operation enable bit Disable compare operation for compare register 1/3/5 Enable compare operation for compare register 1/3/5 IOE0 0 1 Compare match interrupt enable bit Disable compare match interrupt for compare register 0/2/4 Enable Compare match interrupt for compare register 0/2/4 IOE1 0 1 Compare match interrupt enable bit Disable compare match interrupt for compare register 1/3/5 Enable Compare match interrupt for compare register 1/3/5 IOP0 0 1 Compare match interrupt flag bit No compare match interrupt for compare register 0/2/4 Compare match interrupt for compare register 0/2/4 IOP1 0 1 R/W : Read and Write : Initial value -- : not used Compare match interrupt flag bit No compare match interrupt for compare register 1/3/5 Compare match interrupt for compare register 1/3/5 Figure 12.3.2.2-2 Compare Control Register (Lower, OSC0/2/4) 302 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.2.2-2 Compare Control Register (Lower, OSC0/2/4) Bit Function Bit 7 * This bit is an interrupt flag for when compare register 1/3/5 is matched with the value of 16-bit free-run timer. * '1' is written to this bit when the compare register value matches IOP1: the 16-bit free-run timer value. Compare match * While the interrupt request bits (IOE1) is enabled, an output interrupt flag bit compare interrupt occurs when the IOP1 bit is set. * Writing "0" will clear this bit. * Writing "1" has no effect. * In Read-Modify-Write operation, "1" is always read. * This bit is an interrupt flag for when compare register 0/2/4 is matched with the value of 16-bit free-run timer. * '1' is written to this bit when the compare register value matches IOP0: the 16-bit free-run timer value. Compare match * While the interrupt request bits (IOE0) is enabled, an output interrupt flag bit compare interrupt occurs when the IOP0 bit is set. * Writing "0" will clear this bit. * Writing "1" has no effect. * In Read-Modify-Write operation, "1" is always read. IOE1: * This bit is used to enable output compare interrupt for compare Compare match register 1/3/5. interrupt enable * While the '1' is written to this bit, an output compare interrupt bit occurs when an interrupt flag (IOP1) is set. IOE0: * This bit is used to enable output compare interrupt for compare Compare match register 0/2/4. interrupt enable * While the '1' is written to this bit, an output compare interrupt bit occurs when an interrupt flag (IOP0) is set. Unused bit * The read value is indeterminate. * Writing to this bit has no effect on the operation. * This bit is used to enable the compare operation between 16-bit free-run timer and compare register 1/3/5 * Ensure that a value is written into the compare register and timer data register before the compare operation is enabled. Note: Since output compare is synchronized with the 16-bit free-run timer clock, stopping the 16-bit free-run timer stops compare operation. * This bit is used to enable the compare operation between 16-bit free-run timer and compare register 0/2/4 * Ensure that a value is written into the compare register and timer data register before the compare operation is enabled. Note: Since output compare is synchronized with the 16-bit free-run timer clock, stopping the 16-bit free-run timer stops compare operation. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CST1: Compare operation enable bit Bit 0 CST0: Compare operation enable bit MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 303 12.3 Registers of Multi-Function Timer 12.3.3 Registers of 16-bit Input Capture The section describe the registers of 16-bit input capture, which are input capture registers and capture control registers. s Input capture registers Input Capture Register (Upper) Address: ch0 000061H ch1 000063H ch2 000065H ch3 000067H Read/write Initial value 15 CP15 R/W X CP14 R/W X 14 CP13 R/W X 13 CP12 R/W X 12 CP11 R/W X 11 CP10 R/W X 10 CP09 R/W X 9 CP08 R/W X 8 Bit number IPCP0~3 Input Capture Register (Lower) Address: ch0 000060H ch1 000062H ch2 000064H ch3 000066H Read/write Initial value Capture Control Register (Upper) 15 Address: 000069H Read/write Initial value ICP3 R/W 0 14 ICP2 R/W 0 13 ICE3 R/W 0 12 ICE2 R/W 0 11 EG31 R/W 0 10 EG30 R/W 0 9 EG21 R/W 0 8 EG20 R/W 0 Bit Number ICS23 7 CP07 R/W X CP06 R/W X 6 CP05 R/W X 5 CP04 R/W X 4 3 2 CP01 R/W X 1 CP00 R/W X 0 Bit number IPCP0~3 CP03 CP02 R/W X R/W X Capture Control Register (Lower) 7 Address: 000068H Read/write Initial value ICP1 R/W 0 6 ICP0 R/W 0 5 ICE1 R/W 0 4 ICE0 R/W 0 3 EG11 R/W 0 2 EG10 R/W 0 1 EG01 R/W 0 0 EG00 R/W 0 Bit Number ICS01 Figure 12.3.3-1 Registers of 16-bit Input Capture 304 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series 12.3.3 Registers of 16-bit input Capture 12.3.3.1 Input Capture Register (IPCP0~3) Input Capture registers are used to hold the count value of 16-bit timer when a valid edge of the input waveform is detected. s Input capture register (IPCP0~3) Input Capture Register (Upper) Address: ch0 000061H ch1 000063H ch2 000065H ch3 000067H Read/write Initial value 15 CP15 R/W X CP14 R/W X 14 CP13 R/W X 13 CP12 R/W X 12 CP11 R/W X 11 CP10 R/W X 10 CP09 R/W X 9 CP08 R/W X 8 Input Capture Register (Lower) Address: ch0 000060H ch1 000062H ch2 000064H ch3 000066H Read/write Initial value 7 CP07 R/W X CP06 R/W X 6 CP05 R/W X 5 CP04 R/W X 4 3 2 CP01 R/W X 1 CP00 R/W X 0 Bit number IPCP0~3 CP03 CP02 R/W X R/W X Figure 12.3.3.1-1 Input Capture Registers (IPCP0~3) This register is used to store the value of the 16-bit timer when a valid edge of the corresponding external pin input waveform is detected. (Word access instruction to this register is recommended. No data can be written to this register.) MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 305 12.3.3 Registers of 16-bit input Capture 12.3.3.2 Capture Control Registers (ICS23, ICS01) Capture control registers (ICS23, ICS01) are used to control edge selection, interrupt request enable and interrupt request flag for input capture 0~3. s Capture control register (ICS23) Address 000069H Bit 15 ICP3 R/W Bit 14 ICP2 R/W Bit 13 ICE3 R/W Bit 12 ICE2 R/W Bit 11 EG31 R/W Bit 10 EG30 R/W Bit 9 EG21 R/W Bit 8 EG20 R/W Initial value 00000000B EG21 0 0 1 1 EG31 0 0 1 1 ICE2 0 1 ICE3 0 1 EG20 0 1 0 1 EG30 0 1 0 1 Edge selection bit (input capture 2) No Edge detection (Stop) Rising edge detection Falling edge detection Both edges detection Edge selection bit (input capture 3) No Edge detection (Stop) Rising edge detection Falling edge detection Both edges detection Interrupt request enable bit (Input capture 2) Disable interrupt request Enable interrupt request Interrupt request enable bit (Input capture 3) Disable interrupt request Enable interrupt request Interrupt request flag bit (Input capture 2) ICP2 Read 0 1 No valid detected Valid detected Write Clear this bit No effect Interrupt request flag bit (Input capture 3) ICP3 Read 0 R/W : Read and Write : Initial value 1 No valid detected Valid detected Write Clear this bit No effect Figure 12.3.3.2-1 Capture Control Register (ICS23) 306 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.3.2-1 Capture Control Register (ICS23) Bit Bit Function * This bit is used as interrupt request flag for input capture 3. * "1" is written to this bit upon detection of a valid edge of an external input pin. * While the interrupt enable bit (ICE3) is set, an interrupt can be generated upon detection of a valid edge. * Writing "0" will clear this bit. * Writing "1" has no effect. * In Read-Modify-Write operation, "1" is always read. * This bit is used as interrupt request flag for input capture 2. * "1" is written to this bit upon detection of a valid edge of an external input pin. * While the interrupt enable bit (ICE2) is set, an interrupt can be generated upon detection of a valid edge. * Writing "0" will clear this bit. * Writing "1" has no effect. * In Read-Modify-Write operation, "1" is always read. * This bit is used to enable input capture interrupt request for input capture 3. * While "1" is written to this bit, an input capture interrupt is generated when the interrupt flag (ICP3) is set. * This bit is used to enable input capture interrupt request for input capture 2. * While "1" is written to this bit, an input capture interrupt is generated when the interrupt flag (ICP2) is set. * These bits are used to specify the valid edge polarity of an external input for input capture 3. * These bits are also used to enable input capture operation. * These bits are used to specify the valid edge polarity of an external input for input capture 2. * These bits are also used to enable input capture operation. Bit 15 ICP3: Interrupt request flag bit (Input capture 3) Bit 14 ICP2: Interrupt request flag (Input capture 2) Bit 13 ICE3: Interrupt request enable bit (Input capture 3) ICE2: Interrupt request enable bit (Input capture 2) EG31, EG30: Edge selection bit (Input capture 3) EG21, EG20: Edge selection bit (Input capture 2) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 307 s Capture control register (ICS01) Address 000068H Bit 7 ICP1 R/W Bit 6 ICP0 R/W Bit 5 ICE1 R/W Bit 4 ICE0 R/W Bit 3 EG11 R/W Bit 2 EG10 R/W Bit 1 EG01 R/W Bit 0 EG00 R/W Initial value 00000000B EG01 0 0 1 1 EG11 0 0 1 1 ICE0 0 1 ICE1 0 1 EG00 0 1 0 1 EG10 0 1 0 1 Edge selection bit (input capture 0) No Edge detection (Stop) Rising edge detection Falling edge detection Both edges detection Edge selection bit (input capture 1) No Edge detection (Stop) Rising edge detection Falling edge detection Both edges detection Interrupt request enable bit (Input capture 0) Disable interrupt request Enable interrupt request Interrupt request enable bit (Input capture 1) Disable interrupt request Enable interrupt request Interrupt request flag bit (Input capture 0) ICP0 Read 0 1 No valid detected Valid detected Write Clear this bit No effect Interrupt request flag bit (Input capture 1) ICP1 Read 0 R/W : Read and Write : Initial value 1 No valid detected Valid detected Write Clear this bit No effect Figure 12.3.3.2-2 Capture Control Register (ICS01) 308 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.3.2-2 Capture Control Register (ICS01) Bit Function * This bit is used as interrupt request flag for input capture 1. * "1" is written to this bit upon detection of a valid edge of an external input pin. * While the interrupt enable bit (ICE1) is set, an interrupt can be generated upon detection of a valid edge. * Writing "0" will clear this bit. * Writing "1" has no effect. * In Read-Modify-Write operation, "1" is always read. * This bit is used as interrupt request flag for input capture 0. * "1" is written to this bit upon detection of a valid edge of an external input pin. * While the interrupt enable bit (ICE0) is set, an interrupt can be generated upon detection of a valid edge. * Writing "0" will clear this bit. * Writing "1" has no effect. * In Read-Modify-Write operation, "1" is always read. * This bit is used to enable input capture interrupt request for input capture 1. * While "1" is written to this bit, an input capture interrupt is generated when the interrupt flag (ICP1) is set. * This bit is used to enable input capture interrupt request for input capture 0. * While "1" is written to this bit, an input capture interrupt is generated when the interrupt flag (ICP0) is set. * These bits are used to specify the valid edge polarity of an external input for input capture 1. * These bits are also used to enable input capture operation. * These bits are used to specify the valid edge polarity of an external input for input capture 0. * These bits are also used to enable input capture operation. Bit 7 ICP1: Interrupt request flag bit (Input capture 1) Bit 6 ICP0: Interrupt request flag (Input capture 0) Bit 5 ICP1: Interrupt request enable bit (Input capture 1) ICP0: Interrupt request enable bit (Input capture 0) EG11, EG10: Edge selection bit (Input capture 1) EG01, EG00: Edge selection bit (Input capture 0) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 309 12.3 Registers of Multi-Function Timer 12.3.4 Register of 8/16-bit PPG Timer This section describe registers of 8/16-bit PPG timer, that are PPG reload timer x 6, PPG control register x 6 and PPG clock control register x 3. s 8/16-bit PPG Timer Registers PPG Reload Register (Upper) Address: ch0 000039H ch1 00003BH ch2 000041H ch3 000043H ch4 000049H ch5 00004BH Read/write Initial value PPG Reload Register (Lower) Address: ch0 000038H ch1 00003AH ch2 000040H ch3 000042H ch4 000048H ch5 00004AH Read/write Initial value PPG1/3/5 Control Register 15 Address: ch1 00003DH ch3 000045H ch5 00004DH Read/write Initial value PPG0/2/4 Control Register 7 Address: ch0 00003CH ch2 000044H ch4 00004CH Read/write Initial value PPG Clock Control Register 7 Address: ch0,1 00003EH ch2,3 000046H ch4,5 00004EH Read/write Initial value PC12 R/W 0 PC11 R/W 0 6 PC10 R/W 0 5 PC02 R/W 0 4 3 2 1 0 Bit number PCS01/23/45 PC01 PC00 R/W 0 R/W 0 R/W X R/W X PEN0 R/W 0 SST0 R/W 0 6 5 4 3 2 1 Reserved 15 14 13 12 11 10 9 8 Bit number PRLH0~5 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 7 6 5 4 3 2 1 0 Bit number PRLL0~5 R/W X R/W X 14 R/W X 13 R/W X 12 R/W X 11 R/W X 10 R/W X 9 R/W X 8 Bit number PPGC1/3/5 PEN1 R/W 0 SST1 R/W 0 POE1 PIE1 R/W 0 R/W 0 PUF1 MD01 R/W 0 R/W 0 MD00 R/W 0 Reserved R/W 1 0 Bit number PPGC0/2/4 POE0 PIE0 R/W 0 R/W 0 PUF0 POS1 POS0 R/W 0 R/W 0 R/W 0 R/W 1 Figure 12.3.4-1 Registers of 8/16-bit PPG Timers 310 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series 12.3.4 Registers of 8/16-bit PPG Timer 12.3.4.1 PPG Reload Register (PRLH0~5, PRLL0~5) PPG reload registers (PRLH0~5, PRLL0~5) are 8-bit register that is used to store the reload values for the down counter. s PPG reload register (PRLH0~5, PRLL0~5) PPG Reload Register (Upper) Address: ch0 000039H ch1 00003BH ch2 000041H ch3 000043H ch4 000049H ch5 00004BH Read/write Initial value PPG Reload Register (Lower) Address: ch0 000038H ch1 00003AH ch2 000040H ch3 000042H ch4 000048H ch5 00004AH Read/write Initial value R/W X R/W X 15 14 13 12 11 10 9 8 Bit number PRLH0~5 R/W X R/W X R/W X R/W X R/W X R/W X R/W X 7 6 5 4 3 2 1 0 Bit number PRLL0~5 R/W X R/W X R/W X R/W X R/W X R/W X R/W X Figure 12.3.4.1-1 PPG Reload Register (PRLH0~5, PRLL0~5) These are 8-bit registers that is used to store the reload values for the down counter. Their function are described below. Table 12.3.4.1-1 Function of PPG Reload registers Register Name PRLL0-5 PRLH0~5 Function Store the Lower byte of reload value Store the Upper byte of reload value These registers are readable and writable. Note: In 8+8-bit PPG mode, setting different values in PRLL and PRLH of ch0/2/4 may cause the PPG waveform of ch1/3/5 to vary in each cycle. Write the same value to PRLL and PRLH of ch0/2/4. MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 311 12.3.4 Registers of 8/16-bit PPG Timer 12.3.4.2 PPG Control Register (PPGC0~5) PPG control registers (PPGC0~5) are used to control the operation mode, interrupt request enable, interrupt request flag, output enable, start selection, operation enable and the output level polarity for PPG0~5 timers. s PPG1/3/5 control register (PPGC1/3/5) Address ch1: 00003DH ch3: 000045H ch5: 00004DH Bit 15 PEN1 R/W Bit 14 SST1 R/W Bit 13 POE1 R/W Bit 12 PIE1 R/W Bit 11 PUF1 R/W Bit 10 MD01 R/W Bit 9 MD00 R/W Bit 8 Reserved Initial value 00000001B R/W M0D1 0 0 1 1 MOD0 0 1 0 1 PPG1/3/5 timer operation mode bit 8-bit PPG 2ch independent mode 8 + 8-bit PPG mode Reserved (setting inhibited) 16-bit PPG 1ch mode Interrupt request flag bit for PPG1/3/5 PUF1 Read 0 1 PIE1 0 1 POE1 0 1 SST1 0 1 PEN1 0 1 R/W : Read and Write : Initial value No overflow of PPG1/3/5 timer Overflow of PPG1/3/5 timer Write Clear this bit No effect Interrupt request enable bit for PPG1/3/5 Disable interrupt request for PPG1/3/5 Enable interrupt request for PPG1/3/5 Output enable bit for PPG1/3/5 General-purpose port (P42/44/46) PPG output port for PPG1/3/5 Start select bit for PPG1/3/5 PPG1/3/5 will be operated when PEN1="1". PPG1/3/5 will be operated when GATE="H". Operation enable bit for PPG1/3/5 Sop operation for PPG1/3/5 Start operation for PPG1/3/5 Figure 12.3.4.2-1 PPG1/3/5 Control Register (PPGC1/3/5) 312 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.4.2-1 PPG1/3/5 Control Register (PPGC1/3/5) Bit Bit PEN1: Operation enable bit for PPG1/3/5 SST1: Start select bit for PPG1/3/5 POE1: Output enable bit PIE1: Interrupt request enable bit for PPG1/3/5 Function * This bit is used to enable the operation of PPG1/3/5. * When SST1="0", writing "1" will start the PPG1/3/5 operation and writing "0" will stop the operation. * When SST1="1", setting this bit cause no effect. * This bit is used to select the start condition of PPG1/3/5. * After writing "0" to this bit, the PPG1/3/5 will be operated depending on the PEN1 bit. * Writing "1" to PEN1 bit while this bit is "1", PPG1/3/5 will be operated while the GATE signal is "H". * This bit is used to select either the pulse output of PPG1/3/5 or general-purpose port. * This bit is used to enable an interrupt request for PPG1/3/5. * While "1" is written to this bit, PPG1/3/5 is generated an interrupt when the interrupt flag (PUF1) is set. * This bit is used as an interrupt request flag for PPG1/3/5 underflow. * In 8-bit PPG 2ch independent mode or 8+8-bit PPG mode, "1" is written to this bit when an underflow occurs as a result of the ch0/2/4 counter value becoming between 00H and FFH. * In 16-bit PPG 1ch mode, "1" is written to this bit when an underflow occurs as a result of the ch1/ch0, ch2/ch3 and ch4/ ch5 counter value becoming between 0000H and FFFFH. * Writing "0" will clear this bit. Writing "1" has no effect. * In Read-Modify-Write operation, "1" is always read. * This bit is used to select operation mode of PPG1/3/5. Note: Do not set "10" in this bit. Note: When these bits are set to "01", do not set the PPGC0/2/4:PEN0 and PPGC1/3/5:PEN1 bits to "01". It is recommended that the PEN0 and PEN1 bits be set to "11" or "00". When MOD1 and MOD0 are set to "11", rewrite PPGC0/2/4 and PPGC1/3/5 by word transfer to set the PEN0 and PEN1 bits to "11" or "00". Note: When these bits are set to "01", be sure to set the PPGC0/2/4:PEN0 bit to "1" before setting the PPGC1/ 3/5:SST1 bit to "1". When the PEN0 bit is set to "0", be sure to set the SST1 bit to "0" in advance. When MOD1 and MOD0 are set to "11", rewrite PPGC0/2/4 and PPGC1/3/5 by word transfer to set the SST0 and SST1 bits to "11" or "00". * Always setting this bit to "1" when setting PPGC1/3/5 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 PUF1: Interrupt request flag bit for PPG1/3/5 Bit 10 Bit 9 MD01, MD00: PPG1/3/5 timer operation mode bit Bit 8 Reserved bit MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 313 s PPG0/2/4 control register (PPGC0/2/4) Address ch0: 00003CH ch2: 000044H ch4: 00004CH Bit 7 PEN0 R/W Bit 6 SST0 R/W Bit 5 POE0 R/W Bit 4 PIE0 R/W Bit 3 PUF0 R/W Bit 2 POS1 R/W Bit 1 POS0 R/W Bit 0 Reserved Initial value 00000001B R/W POS0 0 1 POS1 0 1 Pulse polarity bit for PPG0/2/4 Positive pulse Negative pulse (reverse mode) Pulse polarity bit for PPG1/3/5 Positive pulse Negative pulse (reverse mode) Interrupt request flag bit for PPG0/2/4 PUF0 Read 0 1 PIE0 0 1 POE0 0 1 SST0 0 1 PEN0 R/W : Read and Write : Initial value 0 1 No overflow of PPG0/2/4 timer Overflow of PPG0/2/4 timer Write Clear this bit No effect Interrupt request enable bit for PPG0/2/4 Disable interrupt request for PPG0/2/4 Enable interrupt request for PPG0/2/4 Output enable bit for PPG0/2/4 General-purpose port (P41/43/45) PPG output port for PPG0/2/4 Start select bit for PPG0/2/4 PPG0/2/4 will be operated when PEN1="1". PPG0/2/4 will be operated when GATE="H". Operation enable bit for PPG0/2/4 Sop operation Start operation Figure 12.3.4.2-2 PPG0/2/4 Control Register (PPGC0/2/4) 314 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.4.2-2 PPG0/2/4 Control Register (PPG0/2/4) Bit PEN0: Operation enable bit for PPG0/2/4 SST0: Start select bit for PPG0/2/4 POE0: Output enable bit PIE0: Interrupt request enable bit for PPG0/2/4 Function * This bit is used to enable the operation of PPG0/2/4. * When SST1="0", writing "1" will start the PPG0/2/4 operation and writing "0" will stop the operation. * When SST1="1", setting this bit cause no effect. * This bit is used to select he start condition of PPG0/2/4. * After writing "0" to this bit, the PPG0/2/4 will be operated depending on the PEN1 bit. * Writing "1" Writing "1" to PEN0 bit while this bit is "1", PPG0/2/4 will be operated while the GATE signal is "H". * This bit is used to select either the pulse output of PPG0/2/4 or general-purpose port. * This bit is used to enable an interrupt request for PPG0/2/4. * While '1' is written to this bit, PPG0/2/4 is generated an interrupt when the interrupt flag (PUF0) is set. * This bit is used as an interrupt request flag for PPG0/2/4 underflow. * In 8-bit PPG 2ch independent mode or 8-bit prescaler + 8-bit PPG mode, '1' is written to this bit when an underflow occurs as a result of the ch0/2/4 counter value becoming between 00H and FFH. * In 16-bit PPG 1ch mode, '1' is written to this bit when an underflow occurs as a result of the ch1/ch0, ch2/ch3 and ch4/ ch5 counter value becoming between 0000H and FFFFH. * Writing "0" will clear this bit. Writing "1" has no effect. * In Read-Modify-Write operation, "1" is always read. * ThIs bit is used to select the pulse polarity to the external pin for PPG1/3/5 * ThIs bit is used to select the pulse polarity to the external pin for PPG0/2/4. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PUF0: Interrupt request flag bit for PPG0/2/4 Bit 2 POS1: Pulse polarity selection bit POS1: Pulse polarity selection bit Reserved bit Bit 1 Bit 0 * Always setting this bit to "1" when setting PPGC0/2/4 MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 315 12.3.4 Registers of 8/16-bit PPG Timer 12.3.4.3 PPG Clock Control Register (PCS01/23/45) PPG clock control registers (PCS01/23/45) are used to control the operating clock frequency for PPG0~5. s PPG clock control register (PCS01/23/45) Address Bit 7 Bit 6 PC11 R/W Bit 5 PC10 R/W Bit 4 PC02 R/W Bit 3 PC01 R/W Bit 2 PC00 R/W Bit 1 -- -- Bit 0 -- -- Initial value 000000XXB ch0,1: 00003EH PC12 ch2,3: 000046H ch4,5: 00004EH R/W PC02 0 0 0 0 1 1 1 1 PC01 0 0 1 1 0 0 1 1 PC00 0 1 0 1 0 1 0 1 Operation clock for ch0/2/4 (62.5 ns, =16MHz) /2 (125 ns, =16MHz) /4 (250 ns, =16MHz) /8 (500 ns, =16MHz) /16 (1 s, =16MHz) /32 (2 s, =16MHz) /64 (4 s, =16MHz) Input clock from timebase trimmer : Machine clock PC12 0 0 0 0 1 1 1 1 X : Indeterminate : Initial value -- : not used R/W : Read and write PC11 0 0 1 1 0 0 1 1 PC10 0 1 0 1 0 1 0 1 Operation clock for ch1/3/5 (62.5 ns, =16MHz) /2 (125 ns, =16MHz) /4 (250 ns, =16MHz) /8 (500 ns, =16MHz) /16 (1 s, =16MHz) /32 (2 s, =16MHz) /64 (4 s, =16MHz) Input clock from timebase trimmer : Machine clock Figure 12.3.4.3-1 PPG0/1/2/3/4/5 Clock Control Register (PCD01/23/45) 316 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.4.3-1 PPG0/1/2/3/4/5 Clock Control Register (PPG0/2/4) Bit Bit 7 Bit 6 Bit 5 PC12~0: Operation clock control bit for PPG1/3/5 PC02~0: Operation clock control bit for PPG0/2/4 Function * These bits select the PPG1/3/5 down counter operation clock. Note: In 8 + 8-bit PPG mode or in 16-bit PPG mode, PPG1/3/ 5 operates in response to a counter clock from PPG0/ 2/4. Therefore, the PCS12~0 bits are invalid. Bit 4 Bit 3 Bit 2 * These bits select the PPG0/2/4 down counter operating clock. Bit 1 Bit 0 Unused bit * The read values are indeterminate. * Writing to these bits have no effect on the operation. MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 317 12.3 Registers of Multi-Function Timer 12.3.5 Registers of Waveform Generator This section describe registers of waveform generator and their details. Those registers are 8-bit reload register x 3, 8-bit timer control register x 3, waveform control register x 1. s Waveform Generator Registers 8-bit Reload Register 7 Address: ch0 000050H ch1 000052H ch2 000054H Read/write Initial value 8-bit timer Control Register 15 Address: ch0 000051H ch1 000053H ch2 000055H Read/write Initial value 14 13 12 TMIE R/W 0 11 10 9 8 Bit number DTCR0/1/2 DMOD GTEN PGEN TMIF R/W 0 R/W 0 R/W 0 R/W 0 TMD2 TMD1 TMD0 R/W 0 R/W 0 R/W 0 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 Bit number TMRR0/1/2 Waveform Control Register 7 Address: 000056H Read/write Initial value DTIE R/W 0 6 DTIL R/W 0 5 NRSL R/W 0 4 DCK2 R/W 0 3 DCK1 R/W 0 2 DCK0 R/W 0 1 PGS1 R/W 0 0 PGS0 R/W 0 Bit Number SIGCR Figure 12.3.5-1 Registers of Waveform Generator 318 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series 12.3.5 Registers of Waveform Generator 12.3.5.1 8-bit Reload Register (TMRR0/1/2) 8-bit reload registers hold the compare value of 8-bit timers. s 8-bit reload registers (TMRR0/12) 8-bit Reload Register 7 Address: ch0 000050H ch1 000052H ch3 000054H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 Bit number TMRR0/1/2 Figure 12.3.5.1-1 8-bit Reload Registers (TMRR0/1/2) These registers is used to store the comparison value of 8-bit timers. These registers will be reloaded when the 8-bit timer is started to operate. Therefore, if the value is re-written into those registers during timer operation, those value will be valid at the next timer initiation/operation. In dead-time timer mode, these registers are used to set the non-overlap time. * Non-overlap time = (set value +1) x selected clock. Note: The value of "00H" cannot be set. In timer mode, these registers are used to set the GATE time for PPG timer operation. * GATE time = (set value +1) x selected clock. Note: The value of "00H" cannot be set. MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 319 12.3.5 Registers of Waveform Generator 12.3.5.2 8-bit Timer Control Register (DTCR0/1/2) 8-bit timer control registers (DTCR0/1/2) are used to control the operation mode, interrupt request enable, interrupt request flag, PPG output enable, GATE signal enable and output level polarity for the waveform generator. s 8-bit timer control register (DTCR0/1/2) Address ch0: 000051H ch1: 000053H ch2: 000055H Bit 15 DMOD R/W Bit 14 GTEN R/W Bit 13 PGEN R/W Bit 12 TMIF R/W Bit 11 TMIE R/W Bit 10 TMD2 R/W Bit 9 TMD1 R/W Bit 8 TMD0 Initial value 00000000B R/W TMD2 TMD1 TMD0 0 0 0 0 0 1 Operation mode bit Waveform generator is stopped. 8-bit timer can be used as reload timer. PPG timer output pulse while RT signal is "H". The PPG timer that outputs pulse must be set in advance in the waveform control register. The rising edge of each RT signal will trigger 8bit timer to start. PPG will run until the 8-bit timer stopped. (Timer mode) Generate non-overlap signal by RT signal. (Dead-time timer mode) RT signal acts as a GATE signal for PPG timers. PPG generates non-overlap signal. (Dead-time timer mode) Interrupt request enable bit 0 1 1 1 0 1 0 0 1 TMIE 0 1 Disable an interrupt when the 8-bit timer underflow Enable an interrupt when the 8-bit timer underflow Interrupt request flag bit TMIF Read 0 1 PGEN 0 1 GTEN 0 1 DMOD 0 R/W : Read and Write : Initial value 1 No counter underflow detected Counter underflow detected PPG output enable bit Disable PPG output Enable PPG output GATE signal enable bit Disable GATE signal output (Asynchronous mode) Enable GATE signal output (Synchronous mode) Output polarity control bit Positive level output Negative level output Write Clear this bit No effect Figure 12.3.5.2-1 8-bit Timer Control Register (DTCR0/1/2) 320 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.5.2-1 8-bit Timer Control Registers (DTCR0/1/2) Bit Bit DMOD: Output polarity control bit GTEN: GATE signal enable bit PGEN: PPG output enable bit TMIF: Interrupt request flag bit Function * This bit is used to set the output polarity when using 8-bit timer as dead-time timer. * By setting this bit, it is possible to invert the output polarity. * If 8-bit timer is not set for dead-time timer operation (Bit11:TMD2=0), setting this bit has no effect. * This bits is used to enable the GATE signal output for PPG timer operation. Bit 15 Bit 14 Bit 13 * This bit is used to enable the output of PPG timers to RTO0~5 pins. * * * * This bit is used as an interrupt request flag for 8-bit timers. This bit will be set to "1" when 8-bit timer is underflow. Writing "0" will clear this bit. Writing "1" has no effect. In Read-Modify-Write operation, "1" is always read. Bit 12 Bit 11 TMIE: Interrupt request enable bit * This bit is used as the start bit and the interrupt enable bit for the 8-bit timer. * Writing "1" to this bit will start the operation for the 8-bit timer. * When this bit is "1" and the interrupt flag bit (Bit12:TIMF) is "1", an interrupt is generated. Note: Bit2~0:TMD2~0 is "000B" is the condition for using the 8-bit timer as reload timer. * These bit are used to select the operation mode of the waveform generator. Note: In PPG timers, the channel is set by waveform control register. Note: Setting TMD2:0 other than `000', `0001', `010', `100' and `111' is prohibited. Other setting will cause an error. When operating in dead time timer mode, the operation mode of RTO1/3/5 must set by 2ch mode. Bit 10 Bit 9 Bit 8 TMD2~0: Operation mode bit MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 321 12.3.5 Registers of Waveform Generator 12.3.5.3 Waveform Control Register (SIGCR) Waveform control register is used to control how the PPG0~5 output to RTO0~5, operating clock frequencies, noise cancelling function enable, DTTI input enable and DTTI input polarity. s Waveform control register (SICGCR) Address 000056H Bit 7 DTIE R/W Bit 6 DTIL R/W Bit 5 NRSL R/W Bit 4 DCK2 R/W Bit 3 DCK1 R/W Bit 2 DCK0 R/W Bit 1 PGS1 R/W Bit 0 PGS0 R/W Initial value 00000000B PPG0~5 output thru RTO0~5 table PGS1 PGS0 Operation mode RTO0 RTO1 RTO2 RTO3 RTO4 RTO5 0 0 1 1 0 1 0 1 8bit x 6 ch PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 8-bit x 3 ch PPG1 PPG1 PPG3 PPG3 PPG5 PPG5 8-bit x 2 ch PPG1 PPG3 PPG1 PPG3 PPG1 PPG3 8-bit x 1 ch PPG1 PPG1 PPG1 PPG1 PPG1 PPG1 DCK2 DCK1 DCK0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Operating clock selection bit (62.5 ns, =16MHz) /2 (125 ns, =16MHz) /4 (250 ns, =16MHz) /8 (500 ns, =16MHz) /16 (1 s, =16MHz) /32 (2 s, =16MHz) /64 (4 s, =16MHz) Prohibited : Machine clock NRSL 0 1 DTIL 0 1 DTIE R/W : Read and Write : Initial value 0 1 Noise cancelling function selection bit DTTI input is not go thru the noise cancelling circuit. DTTI input is not go thru the noise cancelling circuit. DTTI input polarity selection bit "0" input "1" input DTTI input enable bit Disable DTTI input Enable DTTI input Figure 12.3.5.3-1 Waveform Control Register (SIGCR) 322 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Table 12.3.5.3-1 Waveform Control Register (SIGCR) Bit DTIE: DTTI input enable bit Function Bit 7 * This bit is used to enable to receive DTTI input to control the output level of RTO0~5 pin. Bit 6 DTIL: DTTI input * This bit is used to select the level polarity of DTTI input to polarity selection control the output level of RTO0~5 pin. bit * This bit is used to select the noise cancelling function. * Noise cancelling circuit will receive DTTI input signal when the valid level is held until the counter overflows. The counter is 2bit counter which is operated by the valid level input. Note: To cancel the noise pulse width, it takes approximately 4 machine cycles. When the noise cancelling circuit is selected, the input will become invalid if the internal clock is stopped, for example in stop mode. * These bits are used to select the operating clock for the 8-bit timer. * These bits are to select which the PPG timer is used to output pulses directly to RTO0~5. * When the 8-bit timer control register, bit 14:GTEN is set to "1", GATE signal (synchronized mode) will be output to the corresponding PPG. Note: The operation mode in the table on the Figure 12.3.5.31 is written with PPG timer setting, so the corresponding PPG timer output and operation start/ stop control is possible when setting 16-bit mode for the PPG timer. Also, PPG output is possible without using PPG timer GATE function (asynchronized mode), but PPG timer must be operating in software initiation. Bit 5 NRSL: Noise cancelling function selection bit Bit 4 Bit 3 Bit 2 DCK2~0: Operating clock Selection bit Bit 1 Bit 0 PGS1, PGS0: PPG output to RTO selection bit MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 323 12.4 Operation of Multi-Function Timer This section describes the operation of the multifunctional timer unit. s Operation of Multifunctional Timers q 16-bit free-running timer The 16-bit free-running timer starts counting up from counter value "0000H" after a reset has been completed. The counter value is used as the reference time for 16-bit output compare and 16-bit input capture. q 16-bit output compare The output compare unit is used to compare the value set in the specified compare register with the value of the 16-bit free-running timer. If a match is detected, the interrupt flag is set and the output level is inverted q 16-bit input capture The input capture unit is used to detect a specified valid edge. If a valid edge is detected, the interrupt flag is set and the value of 16-bit free-run timer is fetched and stored into the capture register. q 8/16-bit PPG timer This PPG timer has two channels of PPG units each of which is 8 bits long. The timer can operate in normal two-channel independent mode. In addition, by connecting the two channels, it can also operate in two other modes, i.e., 8 + 8-bit PPG mode and 16-bit PPG mode. q Waveform generator The waveform generator can generate various timing waveforms using the real-time outputs (RT0 to RT5), 8/16-bit PPG timer, and 8-bit timer. 324 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Memo MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 325 12.4 Operation of Multi-Function Timer 12.4.1 Operation of 16-bit Free-run Timer The 16-bit free-running timer starts counting up from counter value "0000H" after a reset has been completed. The counter value is used as the reference time for 16-bit output compare and 16-bit input capture. s 16-bit free-run timer operation The counter value is cleared in the following conditions: * * * * * When an overflow has occurred. When a match with output compare clear register is detected. (Mode setting is necessary.) When "1" is written to the CLR bit of the TCCS register during operation. When "0000H" is written to the TCDT register during stop. Reset An interrupt can be generated when an overflow occurs or when the counter is cleared due to a match with compare clear register. (Compare match interrupts can be used only in an appropriate mode.) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Interrupt Time Overflow Figure 12.4.1-1 Clearing the counter by an overflow Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Compare clear register value Interrupt BFFFH Match Match Time Figure 12.4.1-2 Clearing the counter upon a match with compare clear register 326 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series s 16-bit free-run timer timing The 16-bit free-run timer is incremented based on the input clock (internal or external clock). When external clock is selected, the 16-bit free-run timer counts up at a rising edge. External clock input Count clock Counter value N N+1 Figure 12.4.1-3 16-bit Free-run timer count timing The counter can be cleared upon a reset, software clear, or a match with compare clear register. By a reset or software clear, the counter is immediately cleared. By a match with compare clear register, the counter is cleared in synchronization with the count timing. Compare register value Compare match N Counter value N 0000H Figure 12.4.1-4 16-bit Free-run timer clear timing MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 327 12.4 Operation of Multi-Function Timer 12.4.2 Operation of 16-bit Output Compare The output compare unit is used to compare the value set in the specified compare register with the value of the 16-bit free-running timer. If a match is detected, the interrupt flag is set and the output level is inverted. s 16-bit output compare operation a) Compare operation can be performed for individual channel (CMOD=0) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Compare register 0 value Compare register 1 value RTO0 RTO1 Compare 0 BFFFH 7FFFH Time interrupt Compare 1 interrupt Figure 12.4.2-1 Sample output waveform when compare registers 0 and 1 are used individually when the initial output value is "0". 328 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series b) Output level can be changed by using a pair of compare registers (CMOD="1") Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Compare register 0 value Compare register 1 value RTO0 RTO1 Compare 0 interrupt Compare 1 interrupt BFFFH 7FFFH Time Figure 12.4.2-2 Sample output waveform when compare registers 0 and 1 are used in a pair when the initial output value is "0". MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 329 s 16-bit output compare timing q Output levels can be changed by using two pairs of compare registers. (At CMOD = 1) When the free-running timer matches the value set in the compare register, the output compare unit generates a compare match signal to invert the output and generate an interrupt. When a compare match occurs, the output is inverted in synchronization with the count timing of the counter. No comparison is performed with the counter value during replacement of the compare registers.By using 2 compare registers, output level can be changed ("1" when CMOD="1") Note: When the compare register is updated, comparison with the counter value is not performed. Counter value Compare clear register 0 value Compare clear register 0 write Compare clear register 1 value Compare clear register 1 write N N+1 N+2 N+3 No match signal is generated. M N+1 L N+3 Compare 0 stop Compare 1 stop Figure 12.4.2-3 Compare operation upon update of compare registers Counter value Compare register value Compare match Interrupt N N+1 N Figure 12.4.2-4 Compare interrupt timing Counter value Compare register value Compare match signal Pin output N N+1 N N+1 N Figure 12.4.2-5 Output pin change timing 330 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Memo MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 331 12.4 Operation of Multi-Function Timer 12.4.3 Operation of 16-bit Input Capture The input capture unit is used to detect a specified valid edge. If a valid edge is detected, the interrupt flag is set and the value of 16-bit free-run timer is fetched and stored into the capture register. s 16-bit Input capture operation Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset IN0 IN1 IN example Capture register 0 Capture register 1 Capture register example Capture 0 interrupt Capture 1 interrupt Capture example interrupt Interrupt is generated with another valid edge Note: Capture 0: Rising edge Capture 1: Falling edge Capture example: Both edges Interrupt is cleared by software Undefined Undefined Undefined BFFFH 7FFFH 3FFFH 7FFFH Time Figure 12.4.3-1 Sample input capture timing 332 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series s 16-bit input capture input timing Machine clock Counter value Input capture input Capture signal Capture register Interrupt N N+1 Valid edge N+1 Figure 12.4.3-2 16-bit input capture timing for input signals MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 333 12.4 Operation of Multi-Function Timer 12.4.4 Operation of 8/16-bit PPG Timers This section describe operation and timing of 8/16-bit PPG timers. The operation and timing of ch0/ch1 will be explained here. The operation and timing of ch2 and ch4 is the same as ch 0 and the operation and timing of ch 3 and ch 5 is the same as ch 1. Two channels of PPG time can be used in three modes: independent two-channel mode, 8bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the L side (PRLL) and the other is for the H side (PRLH). The values written in these registers are reloaded into the 8-bit down counter (PCNT), from the L side and H side in turn. Thus, the values are decremented for each count clock, and the pin output (PPG) value is inverted upon a reload caused by a counter underflow. This operation results in L-wide or H-wide pulse outputs, corresponding to the reload register value. Further more the output polarity can be selected by software. The operation is started and resumed by writing data in the corresponding register bit. The Table 12.4.4-1 below lists the relationship between the reload operation and pulse outputs. Table 12.4.4-1 Reload operation and pulse output Reload operation PRLH PCNT PRLL PCNT Pin output change Positive polarity PPG0/1 [0 1] Rise PPP0/1 [1 0] Fall Negative Polarity PPP0/1 [1 0] Fall PPG0/1 [0 1] Rise When 1 is set in bit 4 (PIE0) of PPGC0 or in bit 12 (PIE1) of PPGC1, an interrupt request is output upon an underflow from "00H" to "FFH" (or underflow from "0000H" to "FFFFH" in 16-bit PPG mode) of each counter. s Operation mode This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. * 8-bit 2ch independent mode In this mode, the two channels of 8-bit PPG units operate independently. The PPG0 pin is connected to the ch0 PPG output and the PPG1 pin is connected to the ch1 PPG output. * 8 + 8-bit PPG mode In this mode, ch0 is used as an 8-bit prescaler while the count in ch1 is based on underflow outputs from ch0. Thus, 8-bit PPG waveforms can be output at any cycles. The PPG0 is connected to the ch0 prescaler output and the PPG1 pin is connected to the ch1 PPG output. * 16-bit PPG mode In this mode, ch0 and ch1 are connected and used as a single 16-bit PPG. The PPG0 and PPG1 pins are connected to the 16-bit PPG output. 334 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series s PPG output operation Writing '1' to bit7 (PEN0) of PPGC0 register will activate ch0 PPG timer to start counting when bit6 (SST0) of PPGC0 register is "0" (Software activation). Alternately, GATE signal becoming "H" will activate ch0 PPG timer to start counting when bit6 (SST0) of PPGC0 register is "1" (Hardware activation). Similarly, writing '1' to bit15 (PEN1) of PPGC1 register will activate ch1 PPG timer to start counting when bit14 (SST1) of PPGC1 register is "0" (Software activation). Alternately, GATE signal becoming "H" will activate ch1 PPG timer to start counting when bit14 (SST1) of PPGC1 register is "1" (Hardware activation). Once the operation has started, counting is terminated by writing '0' to bit 7 (PEN0) of PPGC0 or in bit 15 (PEN1) of PPGC1, or when the GATE signal changes to "L". Once the counting is terminated, the pulse output is maintained at the "L" level when it is positive polarity output. (the pulse output is maintained at the "H" level when it is negative polarity output.) In 8 + 8-bit PPG mode, do not set ch1 to be in operation while ch0 operation is stopped. For software activation of 16-bit PPG mode, ensure to set bit 7 (PEN0) of PPGC0 register and bit 15 (PEN1) of PPGC1 register simultaneously to start or stop the PPG timer. The Figure 12.4.4-1 below is a diagram of PPG output operation. During PPG operation, a pulse wave is continuously output at a frequency and duty ratio (the ratio of the H-level period of the pulse wave to the L-level period). PPG continues operation until stop is specified explicitly. When activate PPG timer by software PEN Starts operation based on PEN (from L side). Output pin PPGx T x (L+1) T x (H+1) When activate PPG timer by hardware SST GATE Output pin PPGx Starts operation based on GATE signal "H" T x (L+1) T x (H+1) L: H: T: PRLL value PRLH value Input from peripheral clock (, /4, /16) or timer base counter (depending on the clock selection by PPGC) Figure 12.4.4-1 PPG output operation, output waveform MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 335 s Reload value and pulse width relation The pulse width of the output is determined by multiplying "the reload register value + 1" by the count clock cycle. Note that when the reload register value is "00H" during 8-bit PPG operation or "0000H" during 16-bit PPG operation, the pulse width is equivalent to one count clock cycle. In addition, note that when the reload register value is "FFH" during 8-PPG operation, the pulse width is equivalent to 256 count clock cycles. When the reload register value is "FFFFH" during 16-bit PPG operation, the pulse width is equivalent to 65,536 count clock cycles. The formula of pulse width calculation is given below. PL = T x (L+1) PH = T x (H+1) L: H: T: PL : PH : PRLL value value Input clock cycle High pulse width Low pulse width Note: The above formula is for the positive output polarity. The PL and PH setting will be the other way around when negative polarity is used. s Count clock selection The count clock used for the operation of this block is supplied from a machine clock or time base timer. The count clock can be selected from 8 types. The count clock for ch 0 PPG timer is selected by setting bit 4 to 2 (PC02 to 0) of the PCS01 register and the count clock for ch1 PPG timer is selected by setting bit 7 to 5 (PC12 to 0) of the PCS01 register. The clock is selected from 1/64 to 1 times of the machine clock and time base timer input. However, in 8 + 8-bit PPG mode or 16-bit PPG mode, the ch1 PPG timer is operated by receiving a count clock from ch0 PPG timer. Therefore bit 7 to 5 (PC12 to 0) of the PCS01 register are invalid. Note: When the time base counter input is used, the first count cycle after a trigger or a stop may be shifted. The cycle may also be shifted if the time base counter is cleared during operation of this module. In 8 + 8-bit PPG mode, if ch1 is activated while ch0 is in operation and ch1 is stopped, the first count cycle may be shifted. 336 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series s Pulse pin output control The pulses generated by the operation of the 8/16-bit PPG timer can be output to external pins PPG0 and PPG1. The external pin output enable can be done by setting bit 5 (POE0) of the PPGC0 register (PPG0 control register) for the PPG0 pin and setting bit 13 (POE1) of the PPGC1 register (PPG1 control register) for the PPG1 pin. When "0" is written to these bits (initial value), the pulses are not output to the corresponding external pins; the pins will work as general-purpose ports. In 16-bit PPG mode, the same waveform is output from PPG0 and PPG1. Thus, the same output can be obtained by enabling any one external pin. In 8 + 8-bit PPG mode, the 8-bit prescaler (Ch0 PPG timer) toggle output waveform is output to PPG0, while the 8-bit PPG waveform (Ch1 PPG timer) is output to PPG1. The Figure 12.4.4-2 below is a diagram of output waveforms in this mode. PH0 PPG0 PPG1 PL1 PH1 PL0 PL0 = T x (L0+1) PH0 = T x (L0+1) PL1 = T x (L0+1) x (L1+1) PH1 = T x (L0+1) x (H1+1) L0 L1 H1 T : : : : P H0 : ch0 PRLL value and ch0 PRLH value ch1 PRLL value ch1 PRLH value Input clock cycle PPG0 high pulse width PPG0 low pulse width PPG1 high pulse width PPG1 low pulse width P L0 : P H1 : P L1 : Note: Set the same value in ch0 PRLL and ch0 PRLH. Figure 12.4.4-2 8+8 PPG output operation waveform MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 337 s Interrupts An interrupt request is generated when the reload value is counted out and a underflow occurs. In 8-bit PPG 2ch independent mode or 8 + 8-bit PPG mode, an interrupt request is generated by a underflow in each counter. In 16-bit PPG mode, PUF0 and PUF1 are set simultaneously by a underflow in the 16-bit counter. Therefore, enable only PIE0 or PIE1 to unify the interrupt causes. In addition, simultaneously clear the interrupt causes for PUF0 and PUF1. s Reload register write timing In any operation mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a data item to these registers, a pulse of unexpected width may be output depending on the timing. PPG0 A B A B C B C D C x Figure 12.4.4-3 Write timing chart D Assume that PRLL is updated from A to C before point x in the time chart above, and PRLH is updated from B to D after point x. Since the PRL values at point x are PRLL=C and PRLH=B, a pulse of L side count value C and H side count value B is output only once. Similarly, to write data in PRL of ch0 and ch1 in 16-bit PPG mode, use a long word transfer instruction, or use word transfer instructions in the order of ch0 and then ch1. In this mode, the data is only temporarily written to ch0 PRL. Then, the data is actually written into ch0 PRL when the ch1 PRL is written to. In any operation mode other than 16-bit PPG mode, ch0 and ch1 PRL are written independently. ch0 PRL write data Transferred in synchronization with ch1 write in 16-bit PPG mode ch1 PRL write data ch0 write in a mode other than 16-bit PPG mode Temporary latch ch1 write ch0 PRL ch1 PRL Figure 12.4.4-4 PRL write operation block diagram 338 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Memo MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 339 12.4.4 Operation of Waveform Generator 12.4.5 Operation of Waveform Generator Waveform generator can produce various waveform such as dead-time, by using the realtime outputs (RT0~5), 8/16-bit PPG timers and 8-bit timers. s Waveform generator The waveform generator can generate several timing waveform as follows: * By using 8-bit timer as dead-time timer, non-overlap signal of RT1, 3, 5 inverting signal can be generated. It is possible to make non-overlap signal of the selected PPG timer clock inverted signal only when RT1, 3, 5 is at the "H" level.(dead-time generation). With RT0~5 rising edge, the 8-bit timer is started and the selected PPG timer keeps outputting until when the value of the 8-bit timer is matched with the value of TMRR register (8-bit reload register). * Figure 12.4.5-1 is the block diagram of the waveform generator. RT0 RT1 RT2 Selector RT3 8-bit timer 0 RT4 RT5 8-bit timer 1 8-bit timer 2 Selector Port RTO2/V Port Dead-time control circuit Selector Port RTO0/U RTO1/X PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 G0 O G1 O G2 O O O G3 G4 Selector PPG output and GATE signal Control circuit Selector Port RTO3/X Selector Port RTO4/W Port RTO5/Z O G5 DTTI Figure 12.4.5-1 Waveform Generator 340 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series Memo MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 341 12.4.5 Operation of Waveform Generator 12.4.5.1 Operation of Dead-timer Control Circuit The dead-time control circuit will input the realtime output (RT1/3/5) and the selected PPG timer pulse output, and output non-overlap signals (inverted signals) to external pins. s Making non-overlap signals by using RT1/3/5 When selecting non-overlap signal for a active level "0" (positive polarity) in DTCR:bit 15 (DMOD), a delay corresponding to the non-overlap time set in the TMRR register (8-bit reload register) is applied. The delay is applied at a rising edge of RT1/3/5 or its falling edge. If RT1/3/5 pulse width is smaller than the set non-overlap time, the 8-bit timer will restart counting from "00 H" at the nest RT's edge. Setting up registers: * CPCLR : XXXXH (Cycle setting) * TCDT : 0000H * OSC0~5 : ---1XXXXXXXX--11B * TCCS : ------XXXX0X0XXXB * DTCR0~2 : 00000100B * OCCP0~5 : XXXXH (Compare value) * TMRR0~2 : XXXXXXXXXB (non-overlap timing setting) * SIGR : XXXXXX00B (DTTI input and 8-bit timer count clock setting) Note: "X" must be set according to the operation. TMRR set value Count Value RT1 U X one machine cycle one machine cycle Pin name U V W X Y Z Output signal Signal with delay is applied at RT1 rising edge Signal with delay is applied at RT3 rising edge Signal with delay is applied at RT5 rising edge Signal with delay is applied at RT1 falling edge Signal with delay is applied at RT3 falling edge Signal with delay is applied at RT5 falling edge Figure 12.4.5.1-1 Positive Polarity Non-overlap Signal Generation by RT1/3/5 342 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series When selecting non-overlap signal for a active level "1" (positive polarity) in DTCR:bit 15 (DMOD), a delay corresponding to the non-overlap time set in the TMRR register (8-bit reload register) is applied. The delay is applied at a rising edge of RT1/3/5 or its falling edge. If RT1/3/5 pulse width is smaller than the set non-overlap time, the 8-bit timer will restart counting from "00 H" at the nest RT's edge. Setting up registers: * CPCLR : XXXXH (Cycle setting) * TCDT : 0000H * OSC0~5 : ---1XXXXXXXX--11B * TCCS : ------XXXX0X0XXXB * DTCR0~2 : 10000100B * OCCP0~5 : XXXXH (Compare value) * TMRR0~2 : XXXXXXXXXB (non-overlap timing setting) * SIGR : XXXXXX00B (DTTI input and 8-bit timer count clock setting Note: "X" must be set according to the operation. TMRR set value Count Value RT1 U X one machine cycle one machine cycle Pin name U V W X Y Z Output signal Signal with delay is applied at RT1 rising edge Signal with delay is applied at RT3 rising edge Signal with delay is applied at RT5 rising edge Signal with delay is applied at RT1 falling edge Signal with delay is applied at RT3 falling edge Signal with delay is applied at RT5 falling edge Figure 12.4.5.1-2 Negative Polarity Non-overlap Signal Generation by RT1/3/5 MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 343 s Making non-overlap signals by using PPG When selecting non-overlap signal for a active level "0" (positive polarity) in DTCR:bit 15 (DMOD), a delay corresponding to the non-overlap time set in the TMRR register (8-bit reload register) is applied. The delay is applied at a rising edge of PPG timer pulse signal or its inverted signal. If PPG timer pulse width is smaller than the set non-overlap time, the 8-bit timer will start counting from "00 H" at the next edge of PPG pulse. Setting up registers: * CPCLR : XXXXH (Cycle setting) * TCDT : 0000H * OSC0~5 : ---1XXXXXXXX--11B * TCCS : ------XXXX0X0XXXB * DTCR0~2 : 01000111B * OCCP0~5 : XXXXH (Compare value) * TMRR0~2 : XXXXXXXXXB (non-overlap timing setting) * SIGR : XXXXXX00B (DTTI input and 8-bit timer count clock setting) Note: "X" must be set according to the operation. TMRR set value Count Value PPG1 U X one machine cycle one machine cycle Pin name U V W X Y Z Output signal Signal with delay is applied at PPG1 rising edge Signal with delay is applied at PPG3 rising edge Signal with delay is applied at PPG5 rising edge Signal with delay is applied at PPG1 falling edge Signal with delay is applied at PPG3 falling edge Signal with delay is applied at PPG5 falling edge Figure 12.4.5.1-3 Positive Polarity Non-overlap Signal Generation by PPG timer 344 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series When selecting non-overlap signal for a active level "1" (positive polarity) in DTCR:bit 15 (DMOD), a delay corresponding to the non-overlap time set in the TMRR register (8-bit reload register) is applied. The delay is applied at a rising edge of PPG timer pulse signal or its inverted signal. If PPG timer pulse width is smaller than the set non-overlap time, the 8-bit timer will start counting from "00 H" at the next edge of PPG pulse. Setting up registers: * CPCLR : XXXXH (Cycle setting) * TCDT : 0000H * OSC0~5 : ---1XXXXXXXX--11B * TCCS : ------XXXX0X0XXXB * DTCR0~2 : 11000111B * OCCP0~5 : XXXXH (Compare value) * TMRR0~2 : XXXXXXXXXB (non-overlap timing setting) * SIGR : XXXXXX00B (DTTI input and 8-bit timer count clock setting) Note: "X" must be set according to the operation. TMRR set value Count Value PPG1 U X one machine cycle one machine cycle Pin name U V W X Y Z Output signal Signal with delay is applied at PPG1 rising edge Signal with delay is applied at PPG3 rising edge Signal with delay is applied at PPG5 rising edge Signal with delay is applied at PPG1 falling edge Signal with delay is applied at PPG3 falling edge Signal with delay is applied at PPG5 falling edge Figure 12.4.5.1-4 Negative Polarity Non-overlap Signal Generation by PPG timer MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 345 12.4.5 Operation of Waveform Generator 12.4.5.2 Operation of PPG Output and GATE Signal Control Circuit The PPG output and GATE signal control circuit will output the selected PPG pulse to external pins when "1" is written to DCTR:bit 14, 13 (GTEN, PGEN). Furthermore, it output the GATE signal which controls PPG timer operation. It generated GATE signal by using realtime outputs or 8-bit timers and output to PPG timers. s Generating a PPG output/GATE signal during each RT is at "H" level Setting up registers: * CPCLR : XXXXH (Cycle setting) * TCDT : 0000H * OSC0~5 : ---0XXXXXXXX--11B * TCCS : ------XXXX0X0XXXB * DTCR0~2 : 01111001B * OCCP0~5 : XXXXH (Compare value) * TMRR0~2 : XXXXXXXXXB (non-overlap timing setting) * SIGR : XXXXXX00B (DTTI input and 8-bit timer count clock setting Note: "X" must be set according to the operation. Count Value FFFFH BFFFH 7FFFH 3FFFH 0000H PPG0 PPG1 Compare register 0 value Compare register 1 value RT0 RT1 GATE0 GATE1 RTO0 RTO1 BFFFH 7FFFH Time Figure 12.4.5.2-1 Generating PPG output/GATE signal during each RT is at "H" level 346 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series s Generating PPG output/GATE signal until value of 8-bit timer and 8-bit reload register is matched. (Starting the 8-bit timer at every rising edge of the RT) Setting up registers: * CPCLR : XXXXH (Cycle setting) * TCDT : 0000H * OSC0~5 : ---0XXXXXXXX--11B * TCCS : ------XXXX0X0XXXB * DTCR0~2 : 01111010B * OCCP0~5 : XXXXH (Compare value) * TMRR0~2 : XXXXXXXXXB (non-overlap timing setting) * SIGR : XXXXXX00B (DTTI input and 8-bit timer count clock setting Note: "X" must be set according to the operation. Count Value FFFFH BFFFH 7FFFH 3FFFH 0000H PPG0 PPG1 Compare register 0 value Compare register 1 value RT0 RT1 GATE0 GATE1 RTO0 RTO1 time of 8-bit timer 0 time of 8-bit timer 1 Time BFFFH 7FFFH Figure 12.4.5.2-2 Generating PPG output/GATE signal until the value 8-bit timer and 8-bit reload register is matched. Note: Each 8-bit timer is used for two RTs. i.e. 8-bit timer 0 is used for RT0 and RT1; 8-bit timer 1 is used for RT2 and RT3; 8-bit timer 2 is used for RT4 and RT5. Therefore, do not use an RT and attempt to start the corresponding timer that is already operating. Doing so may cause that the outputting GATE signal will be extended and malfunction will be occurred. MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 347 12.4.5 Operation of Waveform Generator 12.4.5.3 Operation of DTTI Pin Control By setting "1" to waveform control register, SIGCR:bit 7 (DTIE), for the wave output of RTO0~5 can be controlled by the DTTI pin. A valid input level which is set by SIGCR:bit 6 (DTIL) and is detected, the output of RTO0~5 will be fixed to an inactive level. The inactive level can be set pin by pin to PDR3 of port 3 by software. s DTTI pin input operation Even when the valid DTTI pin input is detected, the timer will keep running for the waveform generator operation, but no waveform will outputted to external pins. Setting up registers: * CPCLR : XXXXH (Cycle setting) * TCDT : 0000H * OSC0~5 : ---1XXXXXXXX--11B * TCCS : ------XXXX0X0XXXB * DTCR0~2 : 00000100B * OCCP0~5 : XXXXH (Compare value) * TMRR0~2 : XXXXXXXXXB (non-overlap timing setting) * SIGR : 110XXXXXB (DTTI input and 8-bit timer count clock setting) Note: "X" must be set according to the operation. Count Value FFFFH BFFFH 7FFFH 3FFFH 0000H Compare register 0 value Compare register 1 value RT1 BFFFH 7FFFH Time RTO0 RTO1 DTTI Figure 12.4.5.3-1 Operation when DTTI input is enabled 348 CHAPTER 12 MULTI-FUNCTION TIMER MB90560 series s DTTI pin noise cancelling function By setting bit 5 (NRSL) of the waveform control register (SIGCR) to "1", the noise cancelling function for DTTI pin input is enabled. When noise cancelling function is enabled, approximately 4 machine cycles of delay (due to noise cancelling circuit) will be occurred for inactive level fix timing of output pin. Since the noise cancelling circuit operates by using machine clock, the DTTI input is invalid at stop mode (oscillator is stopped) even if the DTTI input is enabled. MB90560 series CHAPTER 12 MULTI-FUNCTION TIMER 349 CHAPTER 13 UART This chapter explains the functions and operation of UART. 13.1 Overview of UART ........................................................................ 352 13.2 Configuration of UART.................................................................. 354 13.3 UART Pins .................................................................................... 358 13.4 UART Registers............................................................................ 360 13.5 UART Interrupts............................................................................ 372 13.6 UART Baud Rates ........................................................................ 376 13.7 Operation of UART ....................................................................... 386 13.8 Notes on Using UART .................................................................. 396 13.9 Sample Program for UART........................................................... 398 13.1 Overview of UART UART is a general-purpose serial data communication interface for performing synchronous or asynchronous (start-stop synchronization) communication with external devices. The UART has a normal bidirectional communication function (normal mode), additionally the master-slave communication function (multiprocessor mode) is only available for the master system. s UART Functions q UART functions UART is a general-purpose serial data communication interface for transmitting serial data to and receiving data from another CPU and peripheral devices. It has the functions listed in Table 13.1-1. Table 13.1-1UART functions Function Data buffer Transfer mode Full-duplex, double buffering * Clock synchronous (using start and stop bits) * Clock asynchronous (start-stop synchronization) * A dedicated baud rate generator is provided. Eight settings can be selected. * An external clock can be input. * Internal clock (internal clocks supplied from 16-bit reload timer 0 can be used.) * 7 bits (in asynchronous normal mode only) * 8 bits Non-return to zero (NRZ) * Framing error * Overrun error * Parity error (cannot be detected in multiprocessor mode.) * Reception interrupt (reception completion and reception error detection) * Transmission interrupt (transmission completion) * Extended intelligent I/O service (EI20S) is available for both transmission and reception interrupts. One-to-n communication (one master to n slaves) can be performed. (This function is supported only for the master system.) Baud rate Data length Signal mode Reception error detection Interrupt request Master-slave communication function (multiprocessor mode) During clock synchronous transfer, start and stop bits are not added so only data is transferred in UART. 352 CHAPTER 13 UART MB90560 series Figure 13.1-1 UART operation mode Data length Operation mode When parity is disabled When parity is enabled Synchronization mode Stop bit length 0 1 2 - *1 *2 Normal mode Multiprocessor Normal mode : Setting not possible 8+1* 8 1 7 or 8 bits - - Asynchronous Asynchronous Synchronous 1 or 2 bits *2 None : "+1" indicates the address/data selection bit (A/D) for communication control. : During reception, only one stop bit can be detected. s UART Interrupt and EIOS Table 13.1-2 UART interrupt and EIOS Interrupt control register Register name Address Lower Vector table address EIOS Upper Bank Interrupt cause Interrupt number UART1 reception interrupt UART1 transmission interrupt UART0 reception interrupt UART0 transmission interrupt #37(25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH #38(26H) ICR13 0000BDH FFFF64H FFFF65H FFFF66H #39(27H) ICR14 0000BEH FFFF60H FFFF61H FFFF62H #40(28H) ICR14 0000BEH FFFF5CH FFFF5DH FFFF5EH : Provided with a function that detects a UART reception error and stops EIOS : Usable when ICR13 and ICR14 or interrupt causes that share an interrupt vector are not used MB90560 series CHAPTER 13 UART 353 13.2 Configuration of UART UART consists of the following 11 blocks: * Clock Selector * Reception Control Circuit * Transmission Control Circuit * Reception Status Detection Circuit * Reception Shift Register * Transmission Shift Register * Serial Mode Control Register (SMR0/1) * Serial Control Register (SCR0/1) * Serial Status Register (SSR0/1) * Serial Input Data Register (SIDR0/1) * Serial Output Data Register (SODR0/1) s Block Diagram of UART Control bus Reception interrupt signal #39 (28H)(*1) <#37 (25H)> Transmission interrupt signal #40 (28H)(*1) <#38 (26H)> Reception control circuit Transmission control circuit Dedicated baud rate generator 16-bit reload timer Transmission clock Clock selector Reception clock Pin P40/SCK0 Start bit detection circuit Received bit counter Received parity counter Transmission start circuit Transmission bit counter Transmission parity counter Pin P37/SOT1 Pin P36/SIN0 Reception shift register Completion of reception Transmission shift register Start of transmission SIDR0/1 Reception status detection circuit SODR0/1 Reception error reception signal for EIOS (to CPU) Internal data bus SMR0/1 register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0/1 register PEN P SBL CL A/D REC RXE TXE SSR0/1 register PE ORE FRE RDRF TDRE BDS RIE TIE *1: Interrupt number Figure 13.2-1 Block diagram of UART 354 CHAPTER 13 UART MB90560 series q Clock Selector The clock selector selects the dedicated baud rate generator, external input clock, or internal clock (clock supplied from the 16-bit reload timer) as the transmitting and receiving clocks. q Reception Control Circuit The reception control circuit consists of a received bit counter, start bit detection circuit, and received parity counter.The received bit counter counts receive data bits. When reception of one data item for the specified data length is complete, the received bit counter generates a reception interrupt request. The start bit detection circuit detects start bits from the serial input signal. When the circuit detects a start bit, it writes data in the SIDR1 register by shifting at the specified transfer rate. The received parity counter calculates the parity of the receive data. q Transmission Control Circuit The transmission control circuit consists of a transmission bit counter, transmission start circuit, and transmission parity counter.The transmission bit counter counts transmission data bits. When transmission of one data item of the specified data length is complete, the transmission bit counter generates a transmission interrupt request. The transmission start circuit starts transmission when data is written to SODR0/1. The transmission parity counter generates a parity bit for data to be transmitted when parity is enabled. q Reception Shift Register The reception shift register fetches receive data input from the SIN pin, shifting the data bit by bit. When reception is complete, the reception shift register transfers receive data to the SIDR0/1 register. q Transmission Shift Register The transmission shift register transfers data written to the SODR0/1 register to itself and outputs the data to the SOT pin, shifting the data bit by bit. q Serial Mode Control Register 1 (SMC0/1) This register performs the following operations: * * * * * * Selecting a UART operation mode Selecting a clock input source Setting up the dedicated baud rate generator Selecting a clock rate (clock division value) when using the dedicated baud rate generator Specifying whether to enable serial data output to the corresponding pin Specifying whether to enable clock output to the corresponding pin MB90560 series CHAPTER 13 UART 355 q Serial Control Register 1 (SCR0/1) This register performs the following operations: * * * * * * * * Specifying whether to provide parity bits Selecting parity bits Specifying a stop bit length Specifying a data length Selecting a frame data format in mode 1 Clearing a flag Specifying whether to enable transmission Specifying whether to enable reception q Serial Status Register 1 (SSR0/1) This register checks the transmission and reception status and error status, and enables and disables transmission and reception interrupt requests. q Serial Input Data Register 1 (SIDR0/1) This register retains receive data. Serial input data is converted and stored in this register. q Serial Output Data Register 1 (SODR0/1) This register retains transmission data. Data written to this register is converted to serial data and output. 356 CHAPTER 13 UART MB90560 series Memo MB90560 series CHAPTER 13 UART 13.3 UART Pins This section describes the UART pins and provides a pin block diagram. s UART Pins The UART pins also serve as general ports. Table 13.3-1 lists the pin functions, I/O formats, and settings required to use UART. Table 13.3-1UART pins Pin name Pin function Port 3 I/O or serial data input Port 3 I/O or serial data output CMOS output and CMOS hysteresis input P40/SCK0 Port 4 I/O or serial clock input/output Not Available Provided I/O format Pull-up Standby control Setting required to use pin Set as an input port (DDR3: bit6 = 0) Set to output enable mode (SMR0: SOE = 1) Set as an input port when a clock is input (DDR4: bit 0=0) Set to output enable mode when a clock is output (SMR0: SCKE = 1) Set the pin as an input port (DDR6: bit0 = 0) Set the pin as an input port (SMR1: SOE = 1) CMOS output and CMOS hysteresis input P62/SCK1 Port 6 I/O or serial clock input/output Not Available Provided Set as an input port when a clock is input (DDR6: bit2 = 0) Set to output enable mode when a clock is output (SMR1:SCKE = 1) P36/SIN0 P37/SOT0 P60/SIN1 P61/SOT1 Port 6 I/O or serial data input Port 6 I/O or serial data output 358 CHAPTER 13 UART MB90560 series s Block Diagram of UART Pins Peripheral input (*1) Port data register (PDR) Internal data bus Peripheral output (*1) Peripheral output enable (*1) PDR read Output latch Pch P36/SIN0 P37/SOT0 P40/SCK0 Pin PDR write Port direction register (DDR) Direction latch Nch DDR write Standby control (SPL=1) P60/SIN1 P61/SOT1 P62/SCK1 DDR read Standby control: Stop mode, timebase timer mode and SPL=1 *1: Peripheral are input or output to or from pins having peripheral functions. Figure 13.3-1 Block Diagram of UART Pins MB90560 series CHAPTER 13 UART 359 13.4 UART Registers The following figure shows the UART registers. s UART Registers Address ch0:000021H,20H ch0:000025H,24H ch0:000023H,22H ch0:000027H,26H ch0:000029H ch1:00002BH bit15 SCR (Serial control register) SSR (Serial status register) bit8 bit7 SMR (Serial mode control register) bit0 SIDR/SODR (Serial input/output data register) Reserved CDCR (communication prescaler control register) Figure 13.4-1 UART registers 360 CHAPTER 13 UART MB90560 series Memo MB90560 series CHAPTER 13 UART 361 13.4 UART Registers 13.4.1 Serial Control Register 1 (SCR0/1) This register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error flag, and specifies whether to enable transmission and reception. s Serial Control Register (SCR0/1) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 P SBL CL A/D bit8 bit7 (SMR) bit0 Initial value ch0:000021 H c h 1 : 0 0 0 0 2 5 H PEN REC RXE TXE W R/W R/W 0 0 0 0 0 1 0 0B R/W R/W R/W R/W R/W TXE 0 1 RXE 0 1 REC 0 1 AD 0 1 CL 0 1 SBL 0 1 7 bits 8 bits Transmission enable bit Disables transmission. Enables transmission. Reception enable bit Disables reception. Enables reception. Reception error flag clear bit Clears the FRE, ORE, and PE flags. Has no effect on the others. Address/data selection bit Data frame Address frame Data length selection bit Stop bit length selection bit 1-bit length 2-bit length Parity selection bit Enabled only when parity is provided (PEN=1) P 0 1 PEN R/W : Read/Write W : Write only y : Initial value 0 1 Even parity Odd parity Parity enable bit Provides no parity bit. Provides a parity bit. Figure 13.4-2 Serial Control register (SCR0/1) 362 CHAPTER 13 UART MB90560 series Table 13.4-1 Functions of each bit of serial control register (SCR0/1) Bit name Function This bit selects whether to add a parity bit during transmission in serial data input-output mode or to detect it during reception. bit15 PEN: Parity enable bit bit14 P: Parity selection bit When parity is provided (PEN=1), this bit selects an even or odd parity. This bit selects the length of the stop bits or the frame end mark of send data in asynchronous transfer mode. bit13 SBL: Stop bit length selection bit This bit specifies the length of send and receive data. bit12 CL: Data length selection bit bit11 A/D: Address/data selection bit * Specify the data format of a frame to be sent or received in multi* Select normal data when this bit is "0", and select address data when the bit is "1". processor mode (mode 1). * This bit clears the FRE, ORE, and PE flags of the status register bit10 REC: Reception error flag clear bit * Write "0" to this bit to clear the FRE, ORE, and PE flag. Writing "1" to this bit has no effect on the others. * This bit controls UART reception. * When this bit is "0", reception is disabled. When it is "1", reception is bit9 RXE: Reception enable bit enabled. bit8 TXE: Transmission enable bit * This bit controls UART transmission. * When this bit is "0", transmission is disabled. * When the bit is "1", transmission is enabled. MB90560 series CHAPTER 13 UART 363 13.4 UART Registers 13.4.2 Serial Mode Control Register (SMR0/1) This register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin. s Serial Mode Control Register (SMR0/1) Address bit15 (SCR) bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value ch0:000020H ch1:000024H MD1 MD0 CS2 CS1 CS0 BCH SCKE SOE 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W R/W SOE 0 1 SCKE 0 1 BCH 0 1 Serial data output enable bit (P37/SOT0, P61/SOT1 pin) Uses the pin as a general I/O port. Uses the pin as the serial data output pin of UART1. Serial clock output enable bit (P50SCK1, P63/SCK1 pin) Uses the pin as a general I/O port or clock input pin of UART1 Uses the pin as the clock output pin of UART1. CS2~0 "000B"~"100B" "101B" "110B" "111B" Clock selection bit Baud rate by dedicated baud rate generator Disables setting. Baud rate by internal timer (16-bit reload timer 0) Baud rate by external clock Operation mode selection bit Mode # Operation mode MD1 MD0 0 0 1 0 1 0 1 2 - Asynchronous (normal mode) Asynchronous (multiprocessor mode) Synchronous (normal mode) Disables setting. R/W : Enables read and write. : Initial value - : Not used 0 1 1 Figure 13.4-3 Serial Mode control register (SMR0/1) 364 CHAPTER 13 UART MB90560 series Table 13.4-2 Functions of each bit of serial mode control register (SMR0/1) Bit name Function These bits select an operation mode. bit7 bit6 MD1 and MD0: Operation mode selection bits * This bit selects a baud rate clock source. When the dedicated baud bit5 bit4 bit3 CS2 to CS0: Clock selection bits * * bit2 BCH: * This bit controls the serial clock input-output ports. * When this bit is "0", the P40/SCK0 and P62/SCK1 pins operate as general input-output ports (P40 and P62) or serial clock input pins. When this bit is "1", the pins operate as serial clock output pins. bit1 SCKE: Serial clock output enable bit * This bit enables or disables the output of serial data. * When this bit is "0", the P37/SOT0 and P61/SOT1 pins operate as bit0 SOE: Serial data output enable bit general input-output ports (P37 and P61). When this bit is 1, the P37/SOT0 and P61/SOT1 pins operate as serial data output pins (SOT0/1). MB90560 series CHAPTER 13 UART 365 13.4 UART Registers 13.4.3 Serial Status Register (SSR0/1) This register checks the transmission and reception status and error status, and enables and disables the transmission and reception interrupts. s Serial Status Register (SSR0/1) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 PE R ORE FRE RDRF TDRE BDS RIE R R R R bit8 bit7 TIE bit0 Initial value ch0:000023H ch1:000027H (SIDR/SODR) 00001000B R/W R/W R/W TIE 0 1 RIE 0 1 BDS 0 1 TDRE 0 1 Transmission interrupt request enable bit Disables transmission interrupt request. Enables transmission interrupt request. Reception enable bit Disables reception interrupt request. Enables reception interrupt request. Transfer direction selection bit LSB first (transfer from the least significant bit) MSB first (transfer from the most significant bit) Transmission data empty flag bit Transmission data exists. (Writing transmission data is not allowed.) Transmission data does not exist. (Writing transmission data is allowed.) RDRF 0 1 Receive data full flag bit No receive data exists. Receive data exists. Framing error flag bit FRE 0 No framing error occurred. 1 ORE 0 1 PE R/W : Read/Write R : Read only 0 1 A framing error occurred. Overrun error flag bit No overrun error occurred. An overrun error occurred. Parity error flag bit No parity error occurred. A parity error occurred. : Initial value Figure 13.4-4 Status register (SSR0/1) 366 CHAPTER 13 UART MB90560 series Table 13.4-3 NO. Functions of each bit of serial status register (SSR0/1) Bit name Function * This bit is set to "1" when a parity error occurs during reception and is cleared * A reception interrupt request is generated when this bit and the RIE bit are "1". * Data in serial input data register (SIDR0/1) is invalid when this flag is set. * This bit is set to "1" when an overrun error occurs during reception and is cleared * A reception interrupt request is generated when this bit and the RIE bit are "1". * Data in the serial input data register (SIDR0/1) is invalid when this flag is set. * This bit is set to "1" when a framing error occurs during reception and is cleared * A reception interrupt request is generated when this bit and the RIE bit are "1". * Data in the serial input data register (SIDR0/1) is invalid when this flag is set. * This flag indicates the status of the input data register (SIDR0/1). * This bit is set to "1" when receive data is loaded into SIDR0/1 and is cleared to "0" * A reception interrupt request is generated when this bit and the RIE bit are "1". * This flag indicates the status of output data register (SODR0/1). * This bit is cleared to "0" when transmission data is written to SODR0/1 and is set when serial input data register SIDR0/1 is read. when "0" is written to the REC bit of the serial control register (SCR0/1). when "0" is written to the REC bit of the serial control register (SCR0/1). when "0" is written to the REC bit of the serial control register (SCR0/1). bit15 PE: Parity error flag bit bit14 ORE: Overrun error flag bit bit13 FRE: Framing error flag bit bit12 RDRF: Receive data full flag bit bit11 TDRE: Transmission data empty flag bit to "1" when data is loaded into the transmission shift register and transmission starts. * A transmission interrupt request is output when this bit and the RIE bit are "1". * This bit selects whether to transfer serial data from the least significant bit (LSB bit10 BDS: Transfer direction selection bit first, BDS=0) or the most significant bit (MSB first, BDS=1). bit9 RIE: Reception interrupt request enable bit TIE: Transmission interrupt request enable bit * This bit enables or disables reception interrupt request to the CPU. * A reception interrupt request is generated when this bit and the receive data flag bit (RDRF) are "1" or this bit and one or more error flag bits (PE, ORE, and FRE) are "1". bit8 * This bit enables or disables transmission interrupt request o the CPU. * A transmission interrupt request is generated when this bit and the TDRE bit are "1". MB90560 series CHAPTER 13 UART 367 13.4 UART Registers 13.4.4 Serial Input Data Register (SIDR0/1) and Serial Output Data Register (SOR0/1) The serial input data register (SIDR0/1) is a serial data reception register. The serial output data register (SODR0/1) is a serial data transmission register. Both SIDR0/1 and SODR0/1 registers are located in the same address. s Serial Input Data Register (SIDR0/1) Figure 13.4-5 shows the bit configuration of serial input data register 1. Address ch0:000022 H ch1:000026 H bit7 D7 R bit6 D6 R bit5 D5 R bit4 D4 R bit3 D3 R bit2 D2 R bit1 D1 R bit0 D0 R Initial value XXXXXXXX B R : Read only X : Indefinite Figure 13.4-5 Serial input data register (SIDR0/1) SIDR0/1 is a register that contains receive data. After the serial data signal transmitted from the SIN0/1 pin to the shift register, the data is stored there. When the data length is 7 bits, the uppermost bit (D7) contains invalid data. When receive data is stored in this register, the receive data full flag bit (SSR0/1: RDRF) is set to "1". If a reception interrupt request is enabled at this point, a reception interrupt request is generated. Read SIDR0/1 when the RDRF bit of the status register (SSR0/1) is "1". The RDRF bit is cleared automatically to "0" when SIDR01/1 is read. Data in SIDR0/1 is invalid when a reception error occurs (SSR0/1: PE, ORE, or FRE = 1). s Serial Output Data Register (SODR0/1) Figure 13.4-6 shows the bit configuration of the serial output data register. Address ch0:000022 H ch1:000026 H bit7 D7 W bit6 D6 W bit5 D5 W bit4 D4 W bit3 D3 W bit2 D2 W bit1 D1 W bit0 D0 W Initial value XXXXXXXX B R : Write only X : Indefinite Figure 13.4-6 Output data register (SODR0/1) When data to be transmitted is written to this register in transmission enable state, it is transferred to the transmission shift register, then converted to serial data, and transmitted to the serial data output terminal (SOT0/1 pin). When the data length is 7 bits, the uppermost bit (D7) contains invalid data. 368 CHAPTER 13 UART MB90560 series When transmission data is written to this register, the transmission data empty flag bit (SS0/1: TDRE) is cleared to "0". When transfer to the transmission shift register is complete, the bit is set to "1". When the TDRE bit is "1", the next transmission data can be written. If output transmission interrupt requests have been enabled, a transmission interrupt request is generated. Write the next transmission data when a transmission interrupt is generated or the TDRE bit is "1". MB90560 series CHAPTER 13 UART 369 13.4 UART Registers 13.4.5 Communication Prescaler Control Register (CDCR0/1) This register controls the division of machine clocks. s Communication Prescaler Control Register (CDCR0/1) The operation clocks of UART can be obtained by dividing machine clocks. UART is designed to obtain certain baud rates for various machine cycles. Output from the communication prescaler is used for the operation clocks of extended I/O serial interfaces. The CDCR bit configuration is shown below. CDCR Address ch0:000029 H ch1:00002BH 15 MD R/W 14 - 13 - 12 - 11 10 9 8 Initial value 0---0000H DIV3 DIV2 DIV1 DIV0 R/W R/W R/W R/W [Bit 15] MD(Machine clock divide mode select) Operation enable bit of the communication prescaler 0: Stops the communication prescaler. 1: Operates the communication prescaler. [Bit 11,10,9,8] DIV30(DIVide30) Machine clock division ratios are determined according to the table in Table 13.4-4. Table 13.4-4Communication prescaler MD DIV3 DIV2 DIV1 DIV0 Divided by 0 1 1 1 1 1 1 1 1 - 0 0 0 0 0 0 0 0 - 0 0 0 0 1 1 1 1 - 0 0 1 1 0 0 1 1 - 0 1 0 1 0 1 0 1 Stop 1 2 3 4 5 6 7 8 If a division ratio is changed, wait two time cycles as clock stabilization time before starting communication. 370 CHAPTER 13 UART MB90560 series Memo MB90560 series CHAPTER 13 UART 371 13.5 UART Interrupts UART uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: * Receive data is transferred to the serial input register (SIDR0/1), or a reception error occurs. * Transmission data is transferred from the serial output data register 1 (SODR0/1) to the transmission shift register. The extended intelligent I-O service (EIOS) is available for these interrupts. s UART Interrupts Table 13.5-1 lists the interrupt control bits and causes of UART. Table 13.5-1 Interrupt control bits and interrupt causes of UART Operation mode Interrupt cause 0 1 2 When interrupt request flag is cleared Reception/ transmission Interrupt request flag bit Interrupt cause enable bit RDRF Reception ORE FRE PE Transmission o : Used x : Not used q Reception Interrupt TDRE o o o o o o o o x o o o x x o Loading receive data into buffers (SIDR0/1) Overrun error Framing error Parity error Empty transmission buffer (SODR0/1) Receive data is read. SSR0/1:RIE 0 is written to the reception error flag clear bit (SSR1: REC). Transmission data is written. SSR0/1:TIE If one of the following events occurs in reception mode, the corresponding flag bit of the status register is set to "1": * * * * Data reception is complete (SSR0/1: RDRF) Overrun error (SSR0/1: ORE) Framing error (SSR0/1; FRE) Parity error (SSR0/1: PE) When at least one of the flag bits is "1" and the reception interrupts are enabled (SSR0/1: RIE=1), a reception interrupt request is generated to the interrupt controller. When the serial input data register (SIDR0/1) is read, the receive data full flag (SSR0/1: RDRF) is automatically cleared to "0". When "0" is written to the REC bit of the serial control register (SCR0/1), all the reception error flags (SSR0/1: PE, ORE, and FRE) are cleared to "0". 372 CHAPTER 13 UART MB90560 series q Transmission Interrupt When transmission data is transferred from the serial output data register (SODR0/1) to the transfer shift register, the TDRE bit of the serial status register (SSR0/1) is set to "1". When the transmission interrupts have been enabled (SSR0/1: TIE=1), a transmission interrupt request is generated to the interrupt controller. s UART Interrupts and EIOS Table 13.5.2 UART interrupts and EIOS Interrupt control register Register name Address Lower Vector table address EIOS Upper Bank Interrupt cause Interrupt number UART1 reception interrupt UART1 transmission interrupt UART0 reception interrupt UART0 transmission interrupt #37(25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH #38(26H) ICR13 0000BDH FFFF64H FFFF65H FFFF66H #39(27H) ICR14 0000BEH FFFF60H FFFF61H FFFF62H #40(28H) ICR14 0000BEH FFFF5CH FFFF5DH FFFF5EH : Provided with a function that detects a UART reception error and stops EIOS : Usable when interrupt causes that share the ICR13 and ICR14 or the interrupt vectors are not used s UART EIOS Functions UART has a circuit for operating EIOS, which can be started up for either reception or transmission interrupts. q For Reception EIOS can be used regardless of the status of other resources. q For Transmission UART shares the interrupt registers (ICR13 and ICR14) with the UART reception interrupts. Therefore, EIOS can be started up only when no UART reception interrupts are used. MB90560 series CHAPTER 13 UART 373 13.5 UART Interrupts 13.5.1 Reception Interrupt Generation and Flag Set Timing The following are the reception interrupt causes: completion of reception (SSR0/1: RDRF) and occurrence of a reception error (SSR0/1: PE, ORE, or FRE). s Reception Interrupt Generation and Flag Set Timing Receive data is stored in the serial input data register 1 (SIDR0/1) if a stop bit is detected (in operation mode 0 or 1) or the last bit of data is detected (in operation mode 2) during reception. If a reception error is detected, the error flags (SSR0/1: PE, ORE, and FRE) are set, then the receive data flag (SSR0/1: RDRF) is set to "1". If one of the error flags is "1" in each mode, the SIDR0/1 register contains invalid data. q Operation Mode 0 (Asynchronous, Normal Mode) The RDRF bit is set to "1" when a stop bit is detected. If a reception error is detected, the error flags (PE, ORE, and FRE) are set. q Operation Mode 1 (Asynchronous, Multiprocessor Mode) The RDRF bit is set to "1" when a stop bit is detected. If a reception error is detected, the error flags (ORE and FRE) are set. Parity errors cannot be detected. q Operation Mode 2 (Synchronous, Normal Mode) The RDRF bit is set when the last bit of receive data (D7) is detected. If a reception error is detected, the error flag (ORE) is set. Parity and framing errors cannot be detected. The figure below shows the reception operation and flag set timing. Receive data (operation mode 0) Receive data (operation mode 1) Receive data (operation mode 2) PE, ORE, FRE* RDRF ST D0 D1 D5 D6 D7/P SP ST D0 D1 D6 D7 A/D SP D0 D1 D4 D5 D6 D7 A reception interrupt occurs. * : The PE flag cannot be used in mode 1. The PE and PRE flags cannot be used in mode 2. ST : Start bit SP : Stop bit A/D : Mode 2 (multiprocessor mode) address/data selection bit Figure 13.5-1 Reception operation and flag set timing q Reception Interrupt Generation Timing When the RDRF, PE, ORE, or FRE flag is set to "1" in the reception interrupt enable state (SSR0/1: RIE=1), reception interrupt requests (#37 and #39) are generated. 374 CHAPTER 13 UART MB90560 series 13.5 UART Interrupts 13.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the next piece of data is ready to be written to the output data register (SODR0/1). s Transmission Interrupt Generation and Flag Set Timing The transmission data empty flag bit (SSR0/1: TDRE) is set to "1" when data written to the output data register (SODR0/1) is transferred to the transmission shift register, and the next data is ready to be written. TDRE is cleared to "0" when transmission data is written to SODR0/1. Figure 13.5-2 shows the transmission operation and flag set timing. A transmission interrupt occurs. [Operation modes 0 and 1] SODR writing TDRE ST D0 D1 D2 D3 D4 D5 D6 A transmission interrupt occurs. SOT output SP D7 A/D SP ST D0 D1 D2 D3 A transmission interrupt occurs. [Operation modes 2] SODR writing TDRE D0 D1 D2 D3 A transmission interrupt occurs. SOT output ST D0~D7 SP A/D D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 : Start bit : Data bit : Stop bit : Address/data selection bit Figure 13.5-2 Transmission operation and flag set timing q Transmission Interrupt Request Generation Timing If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR0/1: TIE=1), transmission interrupt requests (#38 and #40) are generated. MB90560 series CHAPTER 13 UART 13.6 UART Baud Rates One of the following can be selected as the UART transmitting/receiving block: * Dedicated baud rate generator * Internal clock (16-bit reload timer 0) * External clock (clock input to the SCK pin) s UART Baud Rate Selection The baud rate selection circuit is designed as shown below. One of the following three types of baud rates can be selected: q Baud Rates Determined Using the Dedicated Baud Rate Generator UART has an internal dedicated baud rate generator. One of eight baud rates can be selected using the communication prescaler control register (CDCR0/1). An asynchronous or clock synchronous baud rate is selected using the machine clock frequency and the BCH and CS2 to CS0 bits of the mode control register (SMR0/1). q Baud Rates Determined Using the Internal Timer The internal clock supplied from 16-bit reload timer 0 is used as it is (synchronous) or by dividing it by 16 (asynchronous) for the baud rate. Any baud rate can be set by setting the reload value of 16-bit reload register (TMRLR0). q Baud Rates Determined Using the External Clock The clock input from the UART clock pulse input pins (SCK0/P40 and SCK1/P62) is used as it is (synchronous) or by dividing it by 16 (asynchronous) for the baud rate. Any baud rate can be set externally. 376 CHAPTER 13 UART MB90560 series SMR0/1:CS2~0 (clock selection bits) [Dedicated baud rate generator] SMR1:BCH 4 Clock selector When the bits are 000B to 100B 16/10MHz 0 1 /4 /5 Prescaler Frequency divider (Synchronous) Selects 1/2, 1/4, or 1/8. (Asynchronous) Selects the internal fixed division ratio. [Internal timer] TMCSR0/1 CSL1, CSL0 2 Clock selector Down counter When the bits are 110B UF 1/1 (synchronous) 1/16 (asynchronous) Baud rate /21 /2 3 /2 5 Prescaler 16-bit reload timer 0 [External clock] SCK0/P40,SCK1/P62 [Pin] When the bits are 111B 1/1 (synchronous) 1/16 (asynchronous) SMR0/1 MD1, MD0 (Clock synchronous/asynchronous selection) : Machine clock frequency Figure 13.6-1 baud rate selection circuit MB90560 series CHAPTER 13 UART 377 13.6 UART Baud Rates 13.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator This section describes the baud rates that can be set when the clock from the dedicated baud rate generator is selected as the UART transfer clock. s Baud Rates Determined Using the Dedicated Baud Rate Generator When the transfer clock is generated using the dedicated baud rate generator, the machine clock is divided with the machine clock prescaler. The divided machine clock is divided by the transfer clock division ratio selected with the clock selector again.The machine clock division ratios are common to the asynchronous and synchronous baud rates, but different values set internally are selected as the transfer clock division ratio for the asynchronous and synchronous baud rates. The actual transfer rate can be calculated using the following formulas: asynchronous baud rate = division ratio) x (prescaler division ratio) x (asynchronous transfer clock synchronous baud rate = x (prescaler division ratio) x (synchronous transfer clock division ratio) : Machine clock frequency q Division Ratios for the Prescaler (Common to Asynchronous and Synchronous Baud Rates) Each machine clock division ratio is selected using the DIV3 to DIV0 bits of the CDCR register as listed in Table 13.6-1. Table 13.6-1 Selection of each division ratio for the machine clock prescaler Divided by (div) MD DIV3 DIV2 DIV1 DIV0 0 1 1 1 1 1 1 1 1 - 0 0 0 0 0 0 0 0 - 0 0 0 0 1 1 1 1 - 0 0 1 1 0 0 1 1 - 0 1 0 1 0 1 0 1 stop 1 2 3 4 5 6 7 8 378 CHAPTER 13 UART MB90560 series q Synchronous Transfer Clock Division Ratios A division ratio for synchronous baud rates is selected using the CS2 to CS0 bits of the mode control register (SMR0/1) as listed in Table 13.6-2. Table 13.6-2 Selection of synchronous baud rate division ratios Division ratio for CLK synchronization CS2 CS1 CS0 Calculation formula SCKI 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 16M 8M 4M 2M 1M 500K ( / div)/1 ( / div)/2 ( / div)/4 ( / div)/8 ( / div)/16 ( / div)/32 ( / div)/1 ( / div)/2 ( / div)/4 ( / div)/8 ( / div)/16 ( / div)/32 The division ratio is calculated supposing that machine cycle = 16 MHz and div = 4. q Asynchronous Transfer Clock Division Ratios A division ratio for asynchronous baud rates is selected using the CS2 to CS0 bits of the mode control register (SMR0/1) as listed in Table 13.6-3. Table 13.6-3 Selection of synchronous baud rate division ratios Asynchronus (startstop synchronization) CS2 CS1 CS0 Calculation formula SCKI 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 76923 38461 19230 9615 500K 250K ( / div)/(8x13x2) ( / div)/(8x13x4) ( / div)/(8x13x8) ( / div)/(8x13x16) ( / div)/(8x2x2) ( / div)/(8x13x4) ( / div)/(13x1) ( / div)/(13x2) ( / div)/(13x4) ( / div)/(13x8) ( / div)/2 ( / div)/4 The division ratio is calculated supposing that machine cycle = 16 MHz and div = 1. MB90560 series CHAPTER 13 UART 379 q Internal Timer When CS2 to CS0 are set to 110 and the internal timer is selected, the formulas for calculating baud rates (when using the reload timer) are as follows: Asynchronous (start-stop synchronization): ( / N)/(16 x 2 x (n + 1)) CLK synchronization: ( / N)/(2 x (n + 1)) N: Timer count clock sourcen: Timer reload value 380 CHAPTER 13 UART MB90560 series Memo MB90560 series CHAPTER 13 UART 13.6 UART Baud Rates 13.6.2 Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0) This section describes the settings used when the internal clock supplied from 16-bit reload timer 0 is selected as the UART transfer clock. It also shows the baud rate calculation formulas. s Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0) Writing 110B to the CS2 to CS0 bits of the mode control register (SMR0/1) selects the baud rate determined using the internal timer. Any baud rate can be set by specifying a prescaler division ratio and reload value for 16-bit reload timer 0. Figure 13.6-2 shows the baud rate selection circuit for the internal timer. SMR1 : CS2~0="110B" (Selects the internal timer.) Clock selector 16-bit reload timer output (the frequency is specified with a prescaler division ratio and reload value.) 1/1 (synchronous) 1/16 (asynchronous) Baud rate SMR1 : MD1, MD0 (Clock synchronous/asynchronous selection) Figure 13.6-2 Baud rate selection circuit for the internal timer (16-bit reload timer 0) q Baud Rate Calculation Formulas X (n + 1) x 2 x 16 Synchronous baud rate = X (n + 1) x 2 : Machine clock frequency X: Division ratio for the prescaler of 16-bit reload timer 0 (21, 23, or 25) n: Reload value for 16-bit reload timer 0 (0 to 65535) bps Asynchronous baud rate = bps 382 CHAPTER 13 UART MB90560 series q Examples of Setting Reload Values (Machine Clock: 7.3728 MHz) Table 13.6-4 Baud rates and reload values Reload value Clock asynchronous (start-stop synchronization) X=21(machine cycle divided by 2) X=23 (machine cycle divided by 8) Clock synchronous X=21(machine cycle divided by 2) X=23 (machine cycle divided by 8) Baud rate 38400 19200 9600 4800 2400 1200 600 300 X - 2 5 11 23 47 95 191 383 - - 2 5 11 23 47 95 47 95 191 383 767 1535 9071 6143 11 23 47 95 191 383 767 1535 : Division ratio for the prescaler of 16-bit reload timer 0 : Setting not allowed MB90560 series CHAPTER 13 UART 383 13.6 UART Baud Rates 13.6.3 Baud Rates Determined Using the External Clock This section describes the settings used when the external clock is selected as the UART transfer clock. It also shows the baud rate calculation formulas. s Baud Rates Determined Using the External Clock The following three settings are required to select the baud rate determined by using the external clock: * * * Write "111B" to the CS2 to CS0 bits of the serial mode control register (SMR0/1) to select the baud rate determined by using the external clock input. Set the SCK0/P40 and SCK1/P62 pins as input ports (DDR4: bit 0 = 0 and DDR6: bit 2 = 0). Write "0" to the SCKE bit of the serial mode control register (SMR0/1) to set the pin as an external clock input pin. As shown in Figure 13.6-3, a baud rate is selected using the external clock input from the SCK1 pin. To change the baud rate, the external input clock cycle must be changed because the internal division ratio is fixed. SMR1 : CS2~0="111B" (Select the external clock.) Clock selector SCK1/P62 Pin 1/1 (synchronous) 1/16 (asynchronous) Baud rate (Synchronous/asynchronous selection) SMR1 MD1, MD0 Figure 13.6-3 Baud rate selection circuit for the external clock q Baud Rate Calculation Formulas asynchronous baud rate = f/16 synchronous baud rate = f f: External clock frequency (up to 2 MHz) 384 CHAPTER 13 UART MB90560 series Memo MB90560 series CHAPTER 13 UART 385 13.7 Operation of UART UART operates in operation modes 0 and 2 for normal bidirectional serial communication and in operation mode 1 for master-slave communication. s Operation of UART q Operation modes There are three UART operation modes: modes 0 to 2. As listed in Table 13.7-1, an operation mode can be selected according to the inter-CPU connection method and data transfer mode. Table 13.7-1UART operation mode Data length Operation mode When parity is disabled When parity is enabled Synchronizati on mode Stop bit length 0 1 2 - *1 *2 Normal mode Multiprocessor Normal mode : Setting not possible 8+1* 8 1 7 or 8 bits - - Asynchronous Asynchronous Synchronous 1 or 2 bits *2 None : "+1" indicates the address/data selection bit (A/D) for communication control. :During reception, only one stop bit can be detected. * q 386 CHAPTER 13 UART MB90560 series q Operation Enable Bit UART controls both transmission and reception using the operation enable bit for TXE (transmission) and that for RXE (reception). If each of the operations is disabled, stop it as follows: * If reception operation is disabled during reception (data is input to the reception shift register), finish frame reception and store the received data in the serial input data register (SIDRI). Then stop the reception operation. If the transmission operation is disabled during transmission (data is output from the transmission shift register), wait until there is no data in the serial output data register (SODR0/1) before stopping the transmission operation. * MB90560 series CHAPTER 13 UART 387 13.7 Operation of UART 13.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) When UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. s Operation in Asynchronous Mode q Transfer data format Transfer data begins with the start bit (level "L") and ends with the stop bit (level "H"). The data of the specified data bit length is transferred in LSB first mode. * * In operation mode 0, the length of data with no parity is fixed to 7 bits, and that of data with parity is fixed to 8 bits. In operation mode 1, the length of data is fixed to 8 bits with an address/data (A/D) selection bit added instead of parity. Figure 13.7-1 shows the data format in asynchronous mode. [Operation mode 0] [Operation mode 1] ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 * D7/P SP A/D SP D7 * : D7 (bit 7) when parity is not provided P (parity) when parity is provided ST : Start bit SP : Stop bit A/D : Address/data selection bit in operation mode 1 (multiprocessor mode) Figure 13.7-1 Transfer data format (operation modes 0 and 1) q Transmission Operation Transmission data is written to the serial output data register (SODR0/1) when the transmission data empty flag bit (SSR1: TDRE) is "1". This data is transmitted if the transmission operation is enabled (SCR0/1: TXE=1). The TDRE flag is again set to "1" when the transmission data is transferred to the transmission shift register and its transmission starts. Then, the next transmission data gets ready to be set. At this point, a transmission interrupt request is generated that the next transmission data can be set in the SODR0/1 register if that request is enabled (SSR0/1: TIE=1). The TDRE flag is cleared to "0" when the transmission data is written to SODR0/1. q Reception Operation Reception operation is performed every time it is enabled (SCR0/1: RXE=1). When a start bit is detected, a frame of data is received according to the data format specified by the serial control register (SCR0/1). After the frame has been received, the receive data full flag bit (SSR0/1: RDRF) is set to "1". However, the error flag is set if an error occurs. At this point, a reception interrupt request is output if it is enabled (SSR1: TIE=1). Check each flag of the serial status reister(SSR0/1). If the reception is normal, read the serial input data register (SIDR0/1). If an error is found, proceed to error handling. The RDRF flag is cleared to 0 every time receive data is read from SIDR0/1. 388 CHAPTER 13 UART MB90560 series q Stop Bit For transmission, 1 or 2 bits can be selected. During reception however, the first bit is the only one that is always checked. q Error Detection * * In mode 0, parity, overrun, and framing errors can be detected. In mode 1, overrun and framing errors can be detected but parity errors cannot be detected. q Parity 0 Parity can only be used in operation mode 0 (asynchronous, normal mode). Whether to provide parity can be specified using the PEN bit of the serial control register (SCR0/1). Even or odd parity can also be specified using the P bit of the serial control register (SCR0/1). In operation mode 1 (asynchronous, multiprocessor mode) and operation mode 2 (synchronous, normal mode), parity cannot be used. Figure 13.7-2 shows both transmission and receive data when parity is enabled. SIN1 ST SP A parity error occurs during reception with even parity. (SCR1: P=0) 1011000 Transmission with even parity (SCR1: P=0) SOT1 ST SP 1011001 Transmission with odd parity (SCR1: P=1) SOT1 ST SP 1011000 Data ST : Start bit SP : Stop bit Note : Parity is disabled in operation modes 1 and 2. Parity Figure 13.7-2 Transmission data when parity is enabled MB90560 series CHAPTER 13 UART 389 13.7 Operation of UART 13.7.2 Operation in Synchronous Mode (Operation Mode 2) The clock synchronous transfer method is used for UART operation mode 2 (normal mode). s Operation in Synchronous Mode (Operation Mode 2) q Transfer data format In synchronous mode, 8-bit data is transferred using the LSB first method, in which start and stop bits are not added. Figure 13.7-3 shows the data format in clock synchronous mode. Transmission data writing Transmitting and receiving clocks Mark level RXE, TXE Transmission and receive data 1 LSB 0 1 1 0 0 1 0 MSB Data Figure 13.7-3 Transfer data format (operation mode 2) q Clock Supply In clock synchronous mode (I/O extended serial), as same number of clock as the number of transmission and reception bits must be supplied. * * When the internal clock (dedicated baud rate generator or internal timer) is selected, the data receiving synchronous clocks is generated automatically if data is transmitted. When the external clock is selected, confirm that the transmission side UART serial output data register (SODR0/1) contains data (SSR0/1: TDRE=0). Then, clocks for just "1" byte must be supplied from outside. The mark level ("H") must be retained before transmission starts and after it is complete. q Error Detection Only overrun errors can be detected; parity and framing errors cannot be detected. 390 CHAPTER 13 UART MB90560 series q Initialization The following shows the set values of each control register using the synchronous mode: [Serial mode control register (SMR0/1)] MD1,MD0: "10B" CS2,CS1,CS0: Specify clock input using the clock selector. SCKE: "1" for dedicated baud rate generator or internal timer "0" for clock output and external clock (clock input) SOE: "1" for transmission; "0" for reception only [Serial control register (SCR0/1)] PEN: "0" P,SBL,A/D: These bits make no sense. CL: "1" (8-bit data) REC: "0" (the error flag is cleared for initialization.) RXE,TXE: At least one of the two bits is set to "1". [Serial status register (SSR0/1)] RIE: "1" when using interrupts; "0" when using no interrupts. TIE: "0" q Starting Communication Write data to the serial output data register (SODR0/1) to start communication. Temporary data must be written to SODR0/1 to start communication for reception. q Ending Communication The RDRF flag of the serial status register (SSR0/1) is set to "1" when transmission or reception of a data frame is complete. During reception, check the overrun error flag bit (SSR0/1) to see if communication is performing normally. MB90560 series CHAPTER 13 UART 391 13.7 Operation of UART 13.7.3 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication (one-to-one connection) is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. s Bidirectional Communication Function The settings shown in Figure 13.7-4 are required to operate UART in normal mode (operation mode 0 or 2). bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCR1, SMR1 Mode 0 Mode 2 PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 BCH SCKE SOE x 0 00 0xx 1x 0 10 PE ORE FRE RDRF TDRE RIE TIE Set transmit data (during writing). Retain receive data (during reading). SSR1, SIDR1/SODR1 Mode 0 Mode 2 x x DDR6*1 *1 : Set bit 7 of DDR2 and bit 0 of DDR4 to use UART0. : Bit used x : Bit not used 1 : Set "1". 0 : Set "0". : Set "0" to use an input pin. Figure 13.7-4 Settings for UART1 operation mode 0 q Inter-CPU Connection As shown in Figure 13.7-5, interconnect two CPUs. SOT1 SIN1 Output Input SOT1 SIN1 SCK1 CPU-2 SCK1 CPU-1 Figure 13.7-5 Connection example of UART1 bidirectional communication 392 CHAPTER 13 UART MB90560 series q Communication Procedure Communication starts from the transmitting system at an optional timing when transmission data has been prepared. An ANS is returned periodically (byte by byte in this example) when the receiving system receives transmission data. Figure 13.7-6 shows an example of a bidirectional communication flowchart. (Transmitting system) Start (Receiving system) Start Set operation mode (0 or 2) Set 1-byte data in SODR and perform communication Data transmission Set operation mode(same mode as that for the transmitting side) Any received data? NO YES Any received data? NO YES Data transmission Read and process received data. Read and process received data. (ANS) Transmit 1-byte data Figure 13.7-6 Example of bidirectional communication flowchart MB90560 series CHAPTER 13 UART 393 13.7 Operation of UART 13.7.4 Master-slave Communication Function (Multiprocessor Mode) With UART, communication with multiple CPUs connected in master-slave mode is available. However, UART can be used only from the master system. s Master-slave Communication Function The settings shown in Figure 13.7-7 are required to operate UART in multiprocessor mode (operation mode 1). bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCR1, SMR1 PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 BCH SCKE SOE 0 SSR1, SIDR1/SODR1 x 1 0 0 1 0 PE ORE FRE RDRF TDRE - RIE TIE Set transmission data (during writing). Retain receive data (during reading). x DDR6 (*1) *1 : Set bit 6 of DDR3 and bit 0 of DDR4 to use UART0. : Bit used x : Bit not used 1 : Set "1". 0 : Set "0". : Set "0" to use an input pin. Figure 13.7-7 Settings for UART operation mode 1 q Inter-CPU Connection As shown in Figure 13.7-8, a communication system consists of one master CPU and multiple slave CPUs connected to two communication lines. UART1 can be used only from the master CPU. SOT1 SIN1 Master CPU SOT SIN SOT SIN Slave CPU #0 Slave CPU #1 Figure 13.7-8 Connection example of UART master-slave communication 394 CHAPTER 13 UART MB90560 series q Function Selection Select the operation mode and data transfer mode for master-slave communication as shown in Table 13.7-2. Table 13.7-2 Selection of the master-slave communication function Operation mode Data Master CPU Slave CPU Parity Synchronizati on method Stop bit Address transmiss ion and reception Data transmiss ion and reception A/D="1" + 8-bit address Mode 1 - A/D="0" + 8-bit data None Asynchronous 1 or 2 bits q Communication Procedure When the master CPU transmits address data, communication starts. The A/D bit in the address data is set to 1, and the communication destination slave CPU is selected. Each slave CPU checks the address data using a program. When the address data indicates the address assigned to a slave CPU, the slave CPU communicates with the master CPU (ordinary data). Figure 13.7-9 shows a flowchart of master-slave communication (multiprocessor mode). (Master CPU) Start Set operation mode to 1 Set SIN pin as the serial data input pin Set 1-byte data for selecting the slave CPU (address data) in D0 to D7,and transmit data (A/D=1) Set 0 in A/D Enable reception operation Communicate with slave CPU Is communication complete? YES NO Communicating with another slave CPU? YES NO Disable reception operation End MB90560 series Figure 13.7-9 Master-slave communication flowchart CHAPTER 13 UART 395 13.8 Notes on Using UART Notes on using UART are given below. s Notes on Using UART q Enabling Operations In UART, the serial control register (SCR0/1) has both TXE (transmission) and RXE (reception) operation enable bits. Both transmission and reception operations must be enabled before the transfer starts because they have been disabled as the default value (initial value). The transfer can also be canceled by disabling its operation as required. q Communication Mode Setting Set the communication mode while the system is not operating. If the mode is set during transmission or reception, the transmission or reception data is not guaranteed. q Synchronous Mode UART clock synchronous mode (operation mode 2) uses clock control (I/O extended serial) mode, in which start and stop bits are not added to the data. q Transmission Interrupt Enabling Timing The default (initial value) of the transmission data empty flag bit (SSR0/1: TRE) is "1" (no transmission data and transmission data write enable state). A transmission interrupt request is generated as soon as the transmission interrupt requests are enabled (SSR0/1: TIE=1). Be sure to set the TIE flag to "1" after setting the transmission data. 396 CHAPTER 13 UART MB90560 series Memo MB90560 series CHAPTER 13 UART 397 13.9 Sample Program for UART This section contains a sample program for UART. s Sample Program for UART q Processing Specifications The UART1 bidirectional communication function (normal mode) is used to perform serial transmission and reception. * * * * * Operation mode 0, asynchronous mode, eight data bits, two stop bits, and no parity are set. The P60/SIN1 and P61/SOT1 pins are used for communication. The dedicated baud rate generator is used and the baud rate is set to about 9600 bps. Character 13H is transmitted from the SOT1 pin and is received using an interrupt. The machine clock () is assumed to be 16 MHz. q Coding Example ICR13 EQU 0000BDH ; UART1 transmission interrupt control register ICR13 EQU 0000BDH ; UART1 reception interrupt control register DDR3 EQU 000013H ; Port-3 data direction register SMR1 EQU 000024H ; Mode control register 1 SCR1 EQU 000025H ; Control register 1 SIDR1 EQU 000026H ; Input data register 1 SSR1 EQU 000026H ; Output data register 1 SODR1 EQU 000027H ; Status register 1 REC EQU SCR1:2 ; Reception error flag clear bit ;-------Main program-----------------------------------------------------------------------------------------------CODE CSEG ABS = 0FFH START: ; : ; Assumes that stack pointer (SP) has already been ; initialized. AND CCR,#0BFH ; Disables interrupts. MOV I:ICR13,#00H ; Interrupt level 0 (highest) MOV I:DDR3,#00000000B ; Sets SIN0 pin as input pin MOV I:SMR1,#00000001B ; Operation mode 0 (asynchronous) ; Uses dedicated baud rate generator (9615 bps) ; Disables clock pulse output and enables data output. MOV I:SCR1,#00010011B ; No parity and two stop bits ; Clears eight data bits and reception error flag. ; Enables transmission and reception operations. MOV I:SSR1,#00000010B ; Disables transmission interrupts and enables reception ; interrupts. MOV I:SODR1,#13H ; Writes transmission data. MOV ILM,#07H ; Sets ILM in PS to level 7. OR CCR,#40H ; Enables interrupts. LOOP: MOV A,#00H ; Endless loop MOV A,#01H BRA LOOP ;-------Interrupt program------------------------------------------------------------------------------------------WARI: MOV A,SIDR1 ; Reads receive data. CLRB I:REC ; Clears reception interrupt request flag. ; : 398 CHAPTER 13 UART MB90560 series User processing : RETI ; Returns from the interrupt. CODE ENDS ;-------Vector setting-----------------------------------------------------------------------------------------------VECT CSEG ABS=0FFH ORG 0FF68H ; Sets vector for interrupt #37 (25H). DSL WARI ORG 0FFDCH ; Sets reset vector. DSL START DB 00H ; Sets single-chip mode. VECT ENDS ; ; MB90560 series CHAPTER 13 UART 399 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT This chapter describes the functions and operation of the DTP/external interrupt circuit. 14.1 Overview of the DTP/External Interrupt Circuit............................. 402 14.2 Configuration of the DTP/External Interrupt Circuit ...................... 404 14.3 DTP/External Interrupt Circuit Pins............................................... 406 14.4 DTP/External Interrupt Circuit Registers....................................... 408 14.5 Operation of the DTP/External Interrupt Circuit ............................ 414 14.6 Usage Notes on the DTP/External Interrupt Circuit ...................... 420 14.7 Sample Programs for the DTP/External Interrupt Circuit.............. 422 14.1 Overview of the DTP/External Interrupt Circuit The data transfer peripheral, DTP/external interrupt circuit is located between external peripherals and the F2MC-16LX CPU. It receives interrupt requests and data transfer requests from peripherals and passes them to the CPU to generate external interrupt requests or activate the extended intelligent I/O service (EI2OS). s DTP/external interrupt functions The DTP/external interrupt circuit is activated by the signal supplied to a DTP/external interrupt pin. The CPU accepts the signal using the same procedure it uses for normal hardware interrupts and generates external interrupts or activates the extended intelligent I/O service (EI2OS). If the extended intelligent I/O service (EI2OS) is disabled when an interrupt request is accepted by the CPU, the circuit executes its external interrupt function and branches to an interrupt routine. If EI2OS is enabled, the circuit executes its DTP function, which performs automatic data transfer using EI2OS and branches to an interrupt processing routine after the data transfer has been performed a specified number of times. Table 14.1-1 provides an overview of the DTP/external interrupt circuit. Table 14.1-1 Overview of the DTP/external interrupt circuit External interrupt function Input pins Eight(P10/INT0 to P16/INT6 and P63/INT7) By using the request level setting register (ELVR), the level or edge to be detected can be selected for each pin. Interrupt cause Input of "H" level or "L" level or rising edge or falling edge Interrupt number Interrupt control Interrupt flag Processing selection #25 (19H) to #28 (1CH) The output of interrupt requests is enabled and disabled using the DTP/ interrupt enable register (ENIR). Interrupt causes are stored in the DTP/interrupt cause register (EIRR). EI2OS is disabled (ICR: ISE = 0). The circuit branches to an external interrupt processing routine. EI2OS is enabled (ICR: ISE = 1). The circuit performs automatic data transfer using EI2OS for a specified number of times and then branches to an interrupt routine. Input of H level or L level DTP function Processing ICR: Interrupt control register 402 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series s Interrupt of the DTP/external interrupt circuit and EI2OS Table 14.1-2 Interrupt of the DTP/external interrupt circuit and EI 2OS Interrupt control register Register name ICR07 INT2/INT3 INT4/INT5 INT6/INT7 #26 (1AH) #27 (1BH) ICR08 #28 (1CH) 0000B7H FFFF8CH FFFF8DH FFFF8EH Address Vector table address EI2OS Lower FFFF98H 0000B6H FFFF94H FFFF90H FFFF95H FFFF91HH FFFF96H FFFF92H Upper FFFF99H Bank FFFF9AH Channel Interrupt number INT0/INT1 #25 (19H) : Available when not using an interrupt request that shares the ICR07 and ICR08 registers. MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT 14.2 Configuration of the DTP/External Interrupt Circuit The DTP/external interrupt circuit consists of four blocks: * DTP/interrupt input detection circuit * Request level setting register (ELVR) * DTP/interrupt cause register (EIRR) * DTP/interrupt enable register (ENIR) s Block diagram of the DTP/external interrupt circuit Request level setting register (ELVR) LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Pin P63/INT7 Selector Selector Pin P10/INT0 Pin P16/INT6 Selector Selector Pin P11/INT1 Pin Selector Selector Pin P12/INT2 Internal data bus P15/INT5 Pin P14/INT4 Selector Selector Pin P13/INT3 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 DTP/Interrupt cause register (EIRR) Interrupt request number #25(19H) #26(1AH) #27(1BH) #28(1CH) EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 DTP/Interrupt enable register (ENIR) Figure 14.2-1 Block diagram of the DTP/external interrupt circuit 404 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series q DTP/external interrupt input detection circuit Upon detecting the level or edge selected for each pin by the interrupt request level setting register (ELVR), this circuit sets to "1" the ER bit of the DTP/external interrupt cause register (EIRR) that corresponds to the pin. q Request level setting register (ELVR) This register selects the effective level or edge for each pin. q DTP/interrupt cause register (EIRR) This register stores DTP/external interrupt causes. It contains an external interrupt request flag bit for each pin. The bit is set to "1" if a valid signal is input to the corresponding pin. q DTP/interrupt enable register (ENIR) This register enables and disables external interrupts for each pin. MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT 14.3 DTP/External Interrupt Circuit Pins This section describes the DTP/external interrupt circuit pins and provides a pin block diagram. s DTP/external interrupt circuit pins The DTP/external interrupt circuit pins are also used as general ports. Table 14.3-1 lists the pin functions, I/O formats, and settings required to use the DTP/external interrupt circuit. Table 14.3-1 DTP/external interrupt circuit pins Pin name Function I/O format Pull-up resistor Standby control Setting required to use pins Set the pin as an input port (DDR1: bit0 = 0) P10/INT0 P11/INT1 Set the pin as an input port (DDR1: bit1 = 0) P12/INT2 Set the pin as an input port (DDR1: bit2 = 0) P13/INT3 Port 1 inputoutput/external interrupt input CMOS output/ CMOS hysteresis input Selectable Not provided Set the pin as an input port (DDR1: bit3 = 0) P14/INT4 Set the pin as an input port (DDR1: bit4 = 0) P15/INT5 Set the pin as an input port (DDR1: bit5 = 0) P16/INT6 Set the pin as an input port (DDR1: bit6 = 0) P41/INT7 Port 1 inputoutput/external interrupt input Not provided Set the pin as an input port (DDR6: bit3 = 0) 406 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series s Block diagram of the DTP/external interrupt circuit pins RDR Peripherial input (INT) PDR (port data register) Pull-up resistor Internal data bus PDR read Output latch About 50K PDR write DDR (port direction register) Direction latch Pin P10/INT0 to P16/INT6 DDR write DDR read Standby control (SPL = 1) Figure 14.3-1 Block diagram of the DTP/external interrupt circuit pins (For P10/INT0 ~ P16/INT6 only) Peripherial input (INT) PDR (port data register) PDR read Figure 14.3.2 Block diagram of the DTP/external interrupt circuit pins (For P63/ INT7 only) Internal data bus Output latch PDR write DDR (port direction register) Direction latch Pin P63/INT7 DDR write DDR read Standby control (SPL = 1) MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT 14.4 DTP/External Interrupt Circuit Registers This section describes DTP/external interrupt circuit registers. Address 0 0 0 0 3 1 H , 30H 0 0 0 0 3 3 H , 32H bit15 bit8 bit7 bit0 DTP/interrupt cause register (EIRR) DTP/interrupt enable register (EINR) Request level setting register (ELVR) Figure 14.4-2 DTP/external interrupt circuit registers 408 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series 14.4 DTP/External Interrupt Circuit Registers 14.4.1 DTP/interrupt cause register (EIRR) The DTP/interrupt cause register (EIRR) stores and clears interrupt causes. s DTP/interrupt cause register (EIRR) Address 000031H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 (ENIR) bit0 Initial value 00000000B ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 R/W R/W R/W R/W R/W R/W R/W R/W ER7 R/W : Read/write enabled : Initial value ER0 0 1 External interrupt request flag bit Reading A DTP/external interrupt is input. Writing No change, no effect on other bus No DTP/external interrupt is input. This bit is cleared. Figure 14.4-2 DTP/interrupt cause register (EIRR) Table 14.4-1 Function description of each bit of the DTP/interrupt cause register (EIRR) Bit name Function bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ER7 to ER0: External interrupt request flag bits * Each of these bits is set to "1" if a signal with the edge or level selected by the request level setting register (ELVR) is input to the DTP/external interrupt pin (stores an interrupt cause). * If these bits and corresponding bits EN7 to EN0 of the DTP/ interrupt enable register (ENIR) are "1", an interrupt request is output to the CPU. * Writing "0" to this bit clears the bit. Writing "1" to this bit does not change the bit value and has no effect on other bits. When the extended intelligent I/O service (EIOS) is activated, the corresponding external interrupt request flag bit is automatically cleared when the transfer of one data ends. MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT 409 14.4 DTP/External Interrupt Circuit Registers 14.4.2 DTP/interrupt enable register (ENIR) The DTP/interrupt enable register (ENIR) enables and disables the output of interrupt requests to the CPU. s DTP/interrupt enable register (ENIR) Address 000030H bit15 (EIRR) bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 0 0 0 0 0 0 0 0 B R/W R/W R/W R/W R/W R/W R/W R/W EN7 External interrupt request enable bits R/W : Read/write enabled : Initial value EN0 0 1 An external interrupt request is disabled. An external interrupt request is enabled. Figure 14.4-3 DTP/interrupt enable register (ENIR) Table 14.4-2 Function description of each bit of the DTP/interrupt enable register (ENIR) Bit name Function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 EN7 to EN0: External interrupt request enable bits Each of these bits enables and disables interrupt requests to the CPU. If these bits and corresponding bits ER7 to ER0 of the DTP/interrupt cause register (EIRR) are "1", an interrupt request is output to the CPU. [Reference] * To use a DTP/external interrupt pin, write "0" to the corresponding bit of the port direction register to set the pin as an input port. * The states of the DTP/external interrupt pins can be read directly using the port data register regardless of the states of external interrupt request enable bits. * Bits ER7 to ER0 of the DTP/interrupt cause register (EIRR) are set to "1" if an interrupt cause is detected regardless of the values of external interrupt request enable bits. 410 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series Table 14.4-3 Correspondence between the DTP/interrupt control registers (EIRR and ENIR) and each channel DTP/external interrupt pin P63/INT7 #28 (1CH) P16/INT6 P15/INT5 #27 (1BH) P14/INT4 P13/INT3 #26 (1AH) P12/INT2 P11/INT1 #25 (19H) P10/INT0 ER0 EN0 ER2 ER1 EN2 EN1 ER4 ER3 EN4 EN3 ER6 ER5 EN6 EN5 Interrupt number External interrupt request flag bit ER7 External interrupt request enable bit EN7 MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT 14.4 DTP/External Interrupt Circuit Registers 14.4.3 Request level setting register (ELVR) The request level setting register (ELVR) selects the level or edge of the signal input to each DTP/external interrupt pin that is to be detected as a DTP/external interrupt cause. s Request level setting register (ELVR) Address Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Initial value 000033H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B LB 7 LB 0 R/W: Read/write enabled : Initial value LA 7 LA 0 External interrupt request detection selection bits 0 0 1 1 0 1 0 1 The L level is to be detected. The H level is to be detected. A rising edge is to be detected. A falling edge is to be detected. Figure 14.4-4 Request level setting register (ELVR) Table 14.4-4 Function description of each bit of the request level setting register (ELVR) Bit name Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function LB7 to LB0 and LA7 to LA0: Request detection selection bits * Each of these bits selects the level or edge of the signal input to the DTP/external interrupt pin to be detected as a DTP/external interrupt cause. * Two bits are assigned to each pin. [Reference] If the selected detection signal is input to a DTP/external interrupt pin, the external interrupt request flag bit is set to "1" regardless of the settings of the DTP/interrupt enable register (ENIR). 412 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series Table 14.4-5 Correspondence between request level setting register (ELVR) and each channel DTP/external interrupt pin P63/INT7 #28 (1CH) P16/INT6 P15/INT5 #27 (1BH) P14/INT4 P13/INT3 #26 (1AH) P12/INT2 P11/INT1 #25 (19H) P10/INT0 LB0, LA0 LB2, LA2 LB1, LA1 LB4, LA4 LB3, LA3 LB6, LA6 LB5, LA5 Interrupt number Bit name LB7, LA7 MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT 14.5 Operation of the DTP/External Interrupt Circuit The DTP/external interrupt circuit provides the external interrupt function and the DTP function. This section describes the settings required for each function and the operation of the circuit. s Setting the DTP/external interrupt circuit Figure 14.5-1 shows the settings required to operate the DTP/external interrupt circuit. Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ICR08 ICS3 ICS2 ICS1 ICS0 ISE / ICR07 IL2 IL1 IL0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 For the external interrupt function For the DTP function EIRR / ENIR ELVR ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 DDR6/1 : Used P63 P16 P15 P14 P13 P12 P11 P10 : Set the bit to "1" when this is used. : Set the bit to "0" when this is used. 0 : Specifies "0". 1 : Specifies "1". Figure 14.5-1 DTP/external interrupt circuit Set the DTP/external interrupt circuit registers with the following procedure: 1. Clear the target bit of the DTP/interrupt enable register (ENIR) to disable interrupts. 2. Set the target bit of the request level setting register (ELVR). 3. Clear the target bit of the DTP/interrupt cause register (EIRR). 4. Set the target bit of the DTP/interrupt enable register (ENIR) to enable interrupts. The procedure for setting the DTP/external interrupt circuit registers must start with disabling the output of external interrupt requests (ENIR: EN7 to EN0 = 0). Before the output of external interrupt requests can be enabled (ENIR: EN7 to EN0 = 1), the corresponding interrupt request flag bits must be cleared (EIRR: ER7 to ER0 = 0). This is in order to avoid interrupt requests from being generated accidentally while the registers are being set. 414 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series q Switching between the external interrupt function and the DTP function Switching between the external interrupt function and the DTP function is accomplished by the ISE bit of the corresponding interrupt control register (ICR). If the ISE bit is 1, the extended intelligent I/O service (EI2OS) is enabled and the circuit executes its DTP function. If it is "0", EI2OS is disabled and the circuit executes the its external interrupt function. DTP/external interrupt circuit Interrupt request flag bit Interrupt request enable bit Interrupt cause EIRR: ER7 to ER0 ENIR: EN7 to EN0 Input of an effective edge or level to pin INT7 to INT0 When DTP/external input requests are set, an interrupt request will be generated to the interrupt controller whenever an interrupt cause indicated in the request level setting register (ELVR) is received at the corresponding pin. If the ISE bit is "0", the interrupt processing microprogram is executed. If it is "1", the extended intelligent I/O service handling (DTP handling) microprogram is executed. MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT Figure 14.5-2 shows the operation of the DTP/external interrupt circuit. DTP/external interrupt circuit Another request Interrupt controller ELVR EIRR ENRR Cause DTP handling routine (EI2OS is started) Generation of DTP/ external interrupt request Transfer data between memory and peripheral ICRYY CMP ICRXX ILM IL CMP CPU Interrupt processing microprogram Accepted by interrupt controller? Update descriptor Descriptor data counter Accepted by CPU? 0 Return from DTP handling routine Start interrupt processing microprogram 0 Interrupt processing routine Set again or stop Return to CPU processing ICR: ISE 0 Start external interrupt flag. 1 Processing. Clear interrupt flag. Return from external interrupt Figure 14.5-2 Operation of the DTP/external interrupt circuit 416 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series 14.5 Operation of the DTP/External Interrupt Circuit 14.5.1 External interrupt function The DTP/external interrupt circuit has an external interrupt function that generates an interrupt request when a selected signal level is input to a DTP/external interrupt pin. s External interrupt function If the edge or level selected for a DTP/external interrupt pin by the request level setting register (ELVR) is detected at that pin, the corresponding external interrupt flag bit of the DTP/interrupt cause register (EIRR:ER7 to ER0) is set to "1". If, in this state, the corresponding interrupt request enable bit of the DTP/interrupt enable register is set to "1" to enable interrupts (ENIR: EN7 to EN0 = 1), the interrupt cause is reported to the interrupt controller. The interrupt controller checks the value of the interrupt level (ICR: IL2 to IL0) in relation to those of the interrupt requests from other peripheral functions, the interrupt priority, etc. The CPU checks the value of the interrupt level mask register (PS: ILM2 to ILM0) and the interrupt level, the interrupt enable bit (PS: CCR: 1), etc. When the interrupt request is accepted by the CPU, the CPU executes an internal interrupt processing routine (microprogram) and branches to the interrupt processing routine. In the interrupt processing routine, 0 must be written to the corresponding interrupt request flag bit to clear the interrupt request. MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT 417 14.5 Operation of the DTP/External Interrupt Circuit 14.5.2 DTP function The DTP/external interrupt circuit has a DTP function that detects a signal supplied to a DTP/external interrupt pin from an external peripheral and activates the extended intelligent I/O service. s Operation of the DTP function The DTP function detects a data transfer request signal from an external peripheral to automatically transfer data between memory and the peripheral. The extended intelligent I/O service (EI2OS) is activated by the external interrupt function using level detection. The operation of the DTP function is the same as that of the external interrupt function up to the point that the CPU accepts an interrupt request. If the operation of EI2OS is enabled (ICR: ISE = 1), EI2OS is activated to start data transfer when an interrupt request is accepted. When the transfer of one data unit ends, the descriptor is updated and the interrupt request flag bit is cleared to wait for the next request from the pin. When the entire transfer using EI2OS is completed, control is transferred to the interrupt processing routine. The external peripheral signal must be removed only the level of the data transfer request signal (DTP external interrupt cause) within three cycles of the first transfer. H-level request (ELVR: LB0, LA0 = 01B) Input to the INT0 pin (DTP external interrupt cause) Internal operation of the CPU (microprogram) Address bus pin Data bus pin Read signal Write signal Descriptor selection and reading Read address Read data Descriptor updating Write address Write data External peripheral (external memory) External peripheral Register Data, address bus Read operation(*1) DTP external interrupt cause (*2) Internal data bus Write operation (*3) Data transfer request DTP/external interrupt circuit Interrupt request Internal memory *1, *2 Must be removed within three machine cycles of transfer. *3 If the extended intelligent I/O service is in periphera memory transfer mode. Figure 14.5-3 Example of interfacing to the external peripheral 418 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series Memo MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT 14.6 Usage Notes on the DTP/External Interrupt Circuit Notes on the signal to be input to the DTP/external interrupt circuit, release from standby mode, and interrupts are given below. s Usage notes on the DTP/external interrupt circuit q Conditions for external peripherals using the DTP function To support the DTP function, external peripherals must be able to clear data transfer requests automatically in response to transfer operations. If a transfer request is not removed within three machine cycles of the start of transfer, the DTP/external interrupt circuit interprets the request as another transfer request. q Input polarities of external interrupts * * If the request level setting register (ELVR) is set so that an edge is detected, the pulse width must be at least three machine cycles for the edge to be detected. If the register is set for level detection, and the level to be detected as an interrupt cause is input, cause F/F in the DTP/interrupt cause register (EIRR) is set to "1" to store the cause, as shown in Figure 14.6-1. Even if the cause is removed, the request to the interrupt controller remains active provided the output of interrupt requests is enabled. Thus, to cancel the request to the interrupt controller, clear the external interrupt request flag bit and cause F/F, as shown in Figure 14.6-2. DTP/external interrupt cause DTP/interrupt input detection circuit Cause F/F (in the EIRR register) Enable gate To the interrupt controller (interrupt request) The cause is stored until the register is cleared. Figure 14.6-1 Clearing the cause retention circuit when a level is specified DTP/external interrupt cause (when the H level is detected) Removal of the interrupt cause Interrupt request to the interrupt controller Becomes inactive by clearing cause F/F. Figure 14.6-2 DTP/external interrupt cause and interrupt request when the output of interrupt requests is enabled 420 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series q Notes about interrupts When the external interrupt function is used, control cannot return from the interrupt processing routine if the external interrupt request flag bit is "1" and the output of interrupt requests is enabled. In the interrupt processing routine, the external interrupt request flag bit must be cleared. (When the DTP function is used, EI2OS automatically clears the bit.) For level detection, the external interrupt request flag bit is set again as soon as it is cleared if the level assumed as an interrupt cause continues to be input. Either disable the output of interrupt requests or remove the interrupt cause, if required. MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT 14.7 Sample Programs for the DTP/External Interrupt Circuit This section contains sample programs for the external interrupt function and the DTP function. s Sample program for the external interrupt function q Processing * The rising edge of the pulse input to the INT0 pin is detected, and an external interrupt is generate. q Coding example ; Interrupt control register for the DTP/external ; interrupt circuit DDR1 EQU 000011H ; Port 1 direction register ENIR EQU 000030H ; DTP/interrupt enable register EIRR EQU 000031H ; DTP/interrupt cause register ELVRL EQU 000032H ; Request level setting register ELVRH EQU 000033H ; Request level setting register ER0 EQU EIRR:0 ; INT0 interrupt flag bit EN0 EQU ENIR:0 ; INT0 interrupt enable bit ;-------Main program-----------------------------------------------------------------------------------------------------CODE CSEG START: ; : ; Assumes that stack pointer (SP) has already been ; initialized. MOV I:DDR1,#00000000B ; Sets DDR1 as an input port. AND CCR,#0BFH ; Disables interrupts. MOV I:ICR07,#00H ; Interrupt level: 0 (highest). Disables EI2OS. CLRB EN0 ; Disables INT0, using ENIR. MOV I:ELVR,#00000010B ; Selects the rising edge for INT0. CLRB I:ER0 ; Clears the cause for INT0 using EIRR. SETB I:EN0 ; Enables INT0 using ENIR. MOV ILM,#07H ; Sets ILM in PS to level 7. OR CCR,#40H ; Enables interrupts. LOOP: MOV A,#00H ; Endless loop MOV A,#01H BRA LOOP ;-------Interrupt program------------------------------------------------------------------------------------------------WARI CLRB ERP ; Clears the interrupt request flag. ; : ; User processing ; : RETI ; Returns from interrupt. CODE ENDS 422 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series ICR07 EQU 0000B6H ;-------Vector setting----------------------------------------------------------------------------------------------------VECT CSEG ABS=0FFH ORG 0FF98H ; Sets vector for interrupt #25 (19H). DSL WARI ORG 0FFDCH ; Sets reset vector. DSL START DB 00H ; Sets single-chip mode. VECT ENDS END START s Sample program for the DTP function q Processing * * The H level of the signal input to the INT0 pin is detected, and channel 0 of the extended intelligent I/O service (EI2OS) is activated. Data is output from RAM to port 0 by DTP processing (EI2OS). q Coding example ICR07 ; Interrupt control register for the DTP/external ; interrupt circuit DDR0 EQU 000010H ; Port 0 direction register DDR1 EQU 000011H ; Port 1 direction register ENIR EQU 000030H ; DTP/interrupt enable register EIRR EQU 000031H ; DTP/interrupt cause register ELVRL EQU 000032H ; Request level setting register ELVRH EQU 000033H ; Request level setting register ER0 EQU EIRR:0 ; INT0 interrupt flag bit EN0 EQU ENIR:0 ; INT0 interrupt enable bit BAPL EQU 000100H ; Buffer address pointer, lower BAPM EQU 000101H ; Buffer address pointer, middle BAPH EQU 000102H ; Buffer address pointer, upper ISCS EQU 000103H ; EI2OS status register IOAL EQU 000104H ; I/O address register, lower IOAH EQU 000105H ; I/O address register, upper DCTL EQU 000106H ; Data counter, lower DCTH EQU 000107H ; Data counter, upper ;-------Main program--------------------------------------------------------------------------------------------------------------CODE CSEG START: ; : ; Assumes that stack pointer (SP) has already been initialized. MOV I:DDR0,#11111111B ; Sets DDR0 as an output port. MOV I:DDR1,#00000000B ; Sets DDR1 as an input port. AND CCR,#0BFH ; Disables interrupts. MOV I:ICR07,#08H ; Interrupt level: 0 (highest) ; Enables EI2OS. Channel 0 MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT EQU 0000B6H ; Sets the address of the output data ; ; ; Byte transfer. I/O address fixed. Buffer address + 1. Transfer from memory to I/O MOV IOAL,#00H ; Specifies port 0 (PDR0) as the transfer destination MOV IOAH,#00H ; address pointer. MOV DCTL,#0AH ; Number of transfers: 10 MOV DCTH,#00H ; CLRB I:EN0 ; Disables INT0 using ENIR. MOV I:ELVR,#00000001B ; Selects H level for INT0. CLRB I:ER0 ; Clears the cause of INT0 using EIRR. SETB I:EN0 ; Enables INT0 using ENIR. MOV ILM,#07H ; Sets ILM in PS to level 7. OR CCR,#40H ; Enables interrupts. LOOP: MOV A,#00H ; Endless loop MOV A,#01H ; BRA LOOP ; ;-------Interrupt program------------------------------------------------------------------------------------------------WARI: CLRB I:ER0 ; Clears the interrupt request flag. ; : ; ; Switches the channel and changes the transfer address, if required. ; User processing ; Specifies processing again, such as the termination of EI2OS. To terminate the processing, interrupts must be disabled. ; : RETI ; Returns from the interrupt. CODE ENDS ;-------Vector setting-----------------------------------------------------------------------------------------------------VECT CSEG ABS=0FFH ORG 0FF98H ; Sets vector for interrupt #11 (0BH). DSL WARI ORG 0FFDCH ; Sets reset vector. DSL START DB 00H ; Sets single-chip mode. VECT ENDS END START MOV MOV MOV MOV BAPL,#00H BAPM,#06H BAPH,#00H ISCS,#12H 424 CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT MB90560 series Memo MB90560 series CHAPTER 14 DTP/EXTERNAL INTERRUPT CIRCUIT 425 CHAPTER 15 DELAYED INTERRUPT GENERATOR MODULE This chapter describes the functions and operation of the MB90560 series delayed interrupt generator module. 15.1 Overview of the Delayed Interrupt Generator Module .................. 428 15.2 Operation of the Delayed Interrupt Generator Module ................. 429 15.1 Overview of the Delayed Interrupt Generator Module The delayed interrupt generator module generates interrupts for task switching. By using this module, software can issue and cancel interrupt requests for the FMC-16LX CPU. s Block diagram of the delayed interrupt generator module Figure 15.1-1 shows the block diagram of the delayed interrupt generator module. F 2 MC-16 bus Delayed interrupt request register/ Interrupt cause latch Figure 15.1-1 Block diagram of the delayed interrupt generator module s Delayed interrupt generator module register The configuration of the delayed interrupt generator module (delayed interrupt request register [DIRR]) is as follows: bit DIRR address :00009FH 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 R0 R/W Initial value 0R The cause is cleared at reset. The DIRR controls the generation or clearing of a delayed interrupt request. Writing "1" to this register generates a delayed interrupt request. Writing "0" to this register clears the delayed interrupt request. The cause is cleared at reset. Both "0" and "1" may be written to the reserved bit area. However, the set bit and clear bit instructions should be used to access this register to prepare for future expansion. 428 CHAPTER 15 Delayed Interrupt Generator Module MB90620 series 15.2 Operation of the Delayed Interrupt Generator Module When software causes the CPU to write "1" to the relevant bit of DIRR, the request latch in the delayed interrupt generator module is set and an interrupt request is generated to the interrupt controller. s Operation of the Delayed Interrupt Generator Module When software causes the CPU to write "1" to the relevant bit of DIRR, the request latch in the delayed interrupt generator module is set and an interrupt request is generated to the interrupt controller. If the priority of other interrupt requests is lower than that of this interrupt or no other interrupt request is generated, the interrupt controller generates an interrupt request to the FMC-16LX CPU. The FMC-16LX CPU compares the ILM bit of the internal CCR register and the interrupt request. When the request level is higher than that of the ILM bit, the CPU starts the hardware interrupt processing microprogram immediately after execution of the current instruction ends. As a result, the interrupt processing routine for this interrupt is executed. This interrupt cause is cleared and task switching is done by writing "0" to the relevant bit of DIRR in the interrupt processing routine. Figure 15.2-1 shows the operation of the delayed interrupt generator module. Delayed interrupt generator module Other request Delayed interrupt controller WRITE F 2 MC-16LX CPU ICR vv CMP DDIR ICR xx NTA ICR vv CMP ICR xx Figure 15.2-1 Operation of the delayed interrupt generator module s Note on using the delayed interrupt generator module q Delayed interrupt request latch This latch is set by writing "1" to the relevant bit of DIRR and cleared by writing "0" to the same bit. Note that interrupt processing is restarted the moment control returns from interrupt processing unless software is created to clear the cause in the interrupt processing routine. MB90620 series CHAPTER 15 Delayed Interrupt Generator Module 429 CHAPTER 16 8/10-BIT A/D CONVERTER This chapter describes the functions and operation of the 8/10-bit A/D converter. 16.1 Overview of the 8/10-Bit A/D Converter.............................................. 432 16.2 Configuration of the 8/10-Bit A/D Converter ....................................... 434 16.3 8/10-Bit A/D Converter Pins................................................................ 436 16.4 8/10-Bit A/D Converter Registers ....................................................... 438 16.5 8/10-Bit A/D Converter Interrupts ....................................................... 446 16.6 Operation of the 8/10-Bit A/D Converter............................................. 447 16.7 Usage Notes on the 8/10-Bit A/D Converter....................................... 454 16.8 Sample Program 1 for Single Conversion Mode Using EIOS ........... 456 16.9 Sample Program 2 for Continuous Conversion Mode Using EIOS ... 458 16.10 Sample Program 3 for Stop Conversion Mode Using EIOS .............. 461 16.1 Overview of the 8/10-Bit A/D Converter Using the RC-type successive approximation conversion method, the 8/10-bit A/D converter converts an analog input voltage into a 10-bit or 8-bit digital value. An input signal is selected from eight channels for analog input pins. The conversion can be activated by software, an internal clock, and 16-bit free-running timer zero detection. s Functions of the 8/10-bit A/D converter The converter converts the analog voltage at an analog input pin (input voltage) to a digital value. The converter has the following features: * * * * * * * * The minimum conversion time is 6.13 s (for a machine clock of 16 MHz; includes the sampling time). The minimum sampling time is 3.75 s (for a machine clock of 16 MHz). The converter uses the RC-type successive approximation conversion method with a sample hold circuit. A resolution of 10 bits or 8 bits can be selected. Up to eight channels for analog input pins can be selected by a program. At the end of A/D conversion, an interrupt request can be generated and EIOS can be activated. In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being lost through continuous conversion. The conversion can be activated by software, 16-bit reload timer 1 (rising edge), and 16-bit free-running timer zero detection edge. Table 16.1-1 lists three types of conversion modes. Table 16.1-1 8/10-bit A/D converter conversion modes Single conversion Converts the input of a specified channel (single channel) just once. Converts the input of a specified channel (single channel) repeatedly. Scan conversion Converts the inputs of two or more consecutive channels (up to eight channels) just once. Converts the inputs of two or more consecutive channels (up to eight channels) repeatedly. Converts the inputs of two or more consecutive channels (up to eight channels). When a channel has been converted, the converter is put on standby for the next activation. Single conversion mode Continuous conversion mode Stop conversion mode Converts the input of a specified channel (single channel), after which it is on standby for the next activation. 432 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series s 8/10-bit A/D converter interrupts and EIOS Table 16.1-2 8/10-bit A/D converter interrupts and EIOS Interrupt control register Interrupt No. Register name #11 (0BH) ICR00 Address 0000B0H Lower FFFFD0H Upper FFFFD1H Bank FFFFD2H Vector table address EIOS o: Available MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 433 16.2 Configuration of the 8/10-Bit A/D Converter The 8/10-bit A/D converter has nine blocks: * A/D control status register (ADCS1, 2) * A/D data register (ADCR1, 2) * Clock selector (Input clock selector for activating A/D conversion) * Decoder * Analog channel selector * Sample hold circuit * D/A converter * Comparator * Control circuit s Block diagram of the 8/10-bit A/D converter AV cc AV R + Avss MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Sample hold circuit D/A converter F 16-bit reload timer 1 16-bit free-running timer zero detection Prescaler Figure 16.2-1 Block diagram of the 8/10-bit A/D converter 434 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series Input circuit Decoder Sequential comparison register Comparator M C - 1 6 L X bus Data register ADCR1,2 A/D control register 1 A/D control register 1 ADCS1,2 Operating clock q A/D control status register (ADCS1, 2) This register selects activation by software or another activation trigger, the conversion mode, and the A/D conversion channel. It also enables or disables interrupt requests, checks the interrupt request status, and indicates whether the conversion has halted or is in progress. q A/D data register (ADCR1,2) This register holds the result of A/D conversion and selects the resolution for A/D conversion. q Clock selector The clock selector selects the clock for activating A/D conversion. Either 16-bit reload timer channel 1 output or 16-bit free-running timer zero detection can be used as the activation clock. q Decoder This circuit selects the analog input pin to be used based on the settings of the ANE0 to ANE2 bits and ANS0 to ANS2 bits of the A/D control status register (ADCS1). q Analog channel selector This circuit selects the pin to be used from eight analog input pins. q Sample hold circuit This circuit holds the input voltage of the channel selected by the analog channel selector. It samples and holds the input voltage obtained immediately after the activation of A/D conversion. This circuit protects the A/D conversion from any variations in the input voltage during approximation. q D/A converter This circuit generates a reference voltage for comparison with the input voltage maintained by the sample hold circuit. q Comparator This circuit compares the input voltage held by the sample hold circuit with the output voltage of the D/A converter to determine which is greater. q Control circuit This circuit determines the A/D conversion value based on the decision signal generated by the comparator. When the A/D conversion has been completed, the circuit sets the conversion result in the A/D data register (ADCR1, 2) and generates an interrupt request. MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 435 16.3 8/10-Bit A/D Converter Pins This section describes the 8/10-bit A/D converter pins and provides pin block diagrams. s 8/10-bit A/D converter pins The A/D converter pins are also used as general ports. Table 16.3-1 lists the pin functions, I/O formats, and settings required to use the 8/10-bit A/D converter. Table 16.3-1 8/10-bit A/D converter pins Pin function Input-output signal type Pull-up option Standby control I/O port setting for using the pin Function Pin name Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 Port 5 input-output or analog input CMOS output/CMOS hysteresis input or analog input Set port 5 as an input port (DDR5: bits 0 to 7 = 0). Set port 5 as an analog input port (ADER: bits 0 to 7 = 1) Not selectable Not selectable 436 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series s Block diagrams of the 8/10-bit A/D converter pins ADER Port data register (PDR) Analog input MB90560 series Internal data bus * * PDR read Output latch PDR write Port data direction register (DDR) Direction latch Pin DDR write DDR read Standby control (SPL = 1) Figure 16.3-1 Block diagram of the P50/AN0 to P57/AN7 pins CHAPTER 16 8/10-BIT A/D CONVERTER 437 16.4 8/10-Bit A/D Converter Registers This section lists the 8/10-bit A/D converter registers. s 8/10-bit A/D converter registers 15 0017h 14 13 12 ADER 11 10 9 8 7 6 5 4 3 2 1 0 0035h 0037h ADCS1 ADCR1 ADCS0 ADCR0 Figure 16.4-1 8/10-bit A/D converter registers 438 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series 16.4 8/10-Bit A/D Converter Registers 16.4.1 A/D control status register 1 (ADCS1) A/D control status register 1 (ADCS1) selects activation by software or activation trigger, enables or disables interrupt requests, and indicates interrupt request status and whether conversion is halted or in progress. s Upper bits of the A/D control status register (ADCS1) Address 000035H bit15 BUSY R/W bit14 INT R/W bit13 bit12 bit11 bit10 bit9 bit8 bit7 (ADCS0) bit0 Initial value 00000000B INTE PAUS STS1 STS0 STRT RESV R/W R/W R/W R/W W R/W RESV Reserved bit Always write 0 to this bit. A/D conversion activation bit (valid only when activated by software (ADC2: EXT= 0)) Does not activate the A/D conversion. Activate the A/D conversion function. A/D activation select bit Activation by software. Activation by external trigger or software. Activation by timer or software. Activation by external trigger, timer, or software. Halt flag bit (valid only when EI2OS is used) A/D conversion is not halted. A/D conversion is halted. Interrupt request enable bit Disables interrupt request output. Enables interrupt request output. Interrupt request flag bit Reading A/D conversion has not been completed. A/D conversion has been completed. STRT 0 1 STS1 STS0 0 0 1 1 0 1 0 1 PAUS 0 1 INTE 0 1 INT 0 1 Writing Clears this bit. No change,no effect on other bits. BUSY 0 R/W : Read/write W : Write only - : Undefined : Initial value 1 Busy bit Reading A/D conveision is halted. A/D conversion is in progress. Writing Stops the A/D conversion. No change,no effect on other bits. Figure 16.4-2 A/D control status register 1 (ADCS1) MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER Table 16.4-1 Function description of each bit of A/D control status register 1 (ADCS1) Bit name Function * This bit indicates the operating status of the A/D converter. * If the value read from this bit is "0", A/D conversion has halted. If bit15 BUSY: Busy bit * Writing "0" to this bit forces the A/D conversion to stop. Writing "1" to this bit does not change the bit value and has no effect on other bits. the read value is "1", A/D conversion is in progress. * When A/D conversion data is stored in the A/D data register, this * When both this bit and the interrupt request enable bit (ADCS: bit14 INT: Interrupt request flag bit INTE) are "1", an interrupt request is generated. If EIOS has been enabled, it is activated. * Writing "0" to this bit clears the bit. Writing "1" to this bit does not change the bit value and has no effect on other bits. * When EIOS is activated, this bit is cleared. INTE: bit13 Interrupt request enable bit * This bit enables or disables interrupt output to the CPU. * When both this bit and the interrupt request flag bit (ADCS: INT) * When EIOS is used, set this bit to "1". are set to "1", an interrupt request is generated. * When A/D conversion stops temporarily, this bit is set to "1". * This A/D converter has just one A/D data register. In continuous conversion mode, if a conversion result were written before the previous conversion result was read by the CPU, the previous result would be lost. When continuous conversion mode is selected, the program must be written so that the conversion result is automatically transferred to memory by EIOS each time a conversion is completed. This bit also protects against multiple interrupts preventing the completion of conversion data transfer before the next conversion . When a conversion is completed, this bit is set to "1". This status is maintained until EIOS finishes transferring the contents of the data register. Meanwhile, the A/D conversion is halted so that no conversion data can be stored. When EIOS completes the transfer, the A/D converter automatically resumes the conversion. bit12 PAUS: Halt flag bit 440 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series (continued) Bit name Function * These bits select how A/D conversion is to be activated. * When two or more activation causes are shared, activation is the bit11 bit10 STS1, STS0: A/D activation select bit result of the cause that occurs first. bit9 STRT: A/D conversion activation bit * This bit allows software to start A/D conversion. * Writing "1" to this bit activates A/D conversion. * In stop conversion mode, conversion cannot be reactivated with this bit. bit8 RESV: Reserved bit MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 441 16.4 8/10-Bit A/D Converter Registers 16.4.2 A/D control status register 0 (ADCS0) A/D control status register 0 (ADCS0) selects the conversion mode and A/D conversion channel. s A/D control status register 0 (ADCS0) bit15 Address 000034H (ADCS: H) bit8 bit7 MD1 R/W bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value 00000000B MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 R/W R/W R/W R/W R/W R/W R/W ANE2 ANE1 ANE0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 A/D conversion end channel select bit AN0 pin AN1 pin AN2 pin AN3 pin AN4 pin AN5 pin AN6 pin AN7 pin A/D conversion start channel select bit ANS2 ANS1 ANS0 Halt 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Read during conversion Read during a pause in stop conversion mode AN0 pin AN1 pin AN2 pin AN3 pin AN4 pin AN5 pin AN6 pin AN7 pin A/D conversion mode select bit Single conversion mode 1 (reactivation allowed during operation) Single conversion mode 2 (reactivation not allowed during operation) Continuous conversion mode (reactivation not allowed during operation) Stop conversion mode (reactivation not allowed during operation) The current conversion channel number The last conversion channel number MD1 0 0 R/W: Read/write : Initial value 1 1 MD0 0 1 0 1 Figure 16.4-3 A/D control status register 0 (ADCS0) 442 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series Table 16.4-2 Function description of each bit of A/D control status register 0 (ADCS0) Bit name Function * These bits select the conversion mode of the A/D conversion * The two-bit value of the MD1 and MD0 bits determines the mode that is selected from among four modes: single conversion mode 1, single conversion mode 2, continuous conversion mode, and stop conversion mode. * The operation in each mode is described below: Single conversion mode 1: Just a single A/D conversion from the channel set by ANS2 to ANS0 to the channel specified by ANE2 to ANE0 is performed. Reactivation during operation is allowed. Single conversion mode 2: Just a single A/D conversion from the channel set by ANS2 to ANS0 to the channel specified by ANE2 to ANE0 is performed. Reactivation during operation is not allowed. Continuous conversion mode: A/D conversion from the channel set by ANS2 to ANS0 to the channel specified by ANE2 to ANE0 is performed repeatedly. The repeated conversion continues until it is stopped by the BUSY bit. Reactivation during operation is not allowed. Stop conversion mode: A/D conversion from the channel set by ANS2 to ANS0 to the channel specified by ANE2 to ANE0 is performed repeatedly with a pause after the conversion of each channel. The repeated conversion continues until it is stopped by the BUSY bit. Reactivation during operation is not allowed. In the pause state, the conversion is reactivated when an activation cause selected by the STS1 and STS0 bits of ADCS1 is generated. bit7 bit6 MD1, MD0: A/D conversion mode select bit * These bits set the A/D conversion start channel and indicate the bit5 bit4 bit3 ANS2, ANS1, ANS0: A/D conversion start channel select bit * When activated, A/D conversion starts from the channel specified * During A/D conversion, the bits indicate the number of the current conversion channel. During a pause in stop conversion mode, the bits indicate the number of the last conversion channel. by these bits. number of the current conversion channel. * These bits set the A/D conversion end channel. * When activated, A/D conversion is performed up to the channel bit2 bit1 bit0 ANE2, ANE1, ANE0: A/D conversion end channel select bit * When these bits specify the channel specified by ANS2 to ANS0, just that channel is converted. In continuous or stop conversion mode, the start channel specified by ANS2 to ANS0 is converted after the channel specified by these bits. If the start channel is greater than the end channel, the start channel to AN7 and AN0 to the end channel are converted in that order in a single series of conversions. specified by these bits. MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 443 16.4 8/10-Bit A/D Converter Registers 16.4.3 A/D data register (ADCR0, 1) The A/D data register (ADCR0, 1) holds the result of A/D conversion and selects the resolution of A/D conversion. s A/D data register (ADCR0,1) Bit15 Bit14 Bit13 Bit12 000037h S10 R/W ST1 W ST0 W CT1 W Bit1 CT0 W Bit0 - Bit9 D9 R Bit8 D8 R Bit7 D7 R Bit6 D6 R Bit5 D5 R Bit4 D4 R Bit3 D3 R Bit2 D2 R Bit1 D1 R Bit0 D0 R Initial value 00101 -XX XXXXXXXXB D0 to D9 Conversion data AD data bit CT1 0 0 1 1 CT0 0 1 0 1 Comparison time setting bit 44 machine cycles (5.50s@8MHz) 66 machine cycles (4.12s@16MHz) 88 machine cycles (5.50s@16MHz) 176 machine cycles (11.0s@16MHz) ST1 0 0 1 1 ST0 0 1 0 1 Sampling time setting bit 20 machine cycles (2.5s@8MHz) 32 machine cycles (2.0s@16MHz) 48 machine cycles (3.0s@16MHz) 128 machine cycles (8.0s@16MHz) R W X : Not used : Read only : Write only : Undefined : Initial value S10 0 1 AD data bit 10-bit resolution mode (D9 to D0) 8-bit resolution mode (D7 to D0) Figure 16.4-4 A/D data register (ADCR0, 1) 444 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series Table 16.4-3 Function description of each bit of A/D control status register 0 (ADCS0) Bit name Function bit15 S10: A/D conversion resolution selection bit * This bit selects an A/D conversion resolution. * Writing "0" to this bit selects a resolution of 10 bits, and writing "1" to this bit selects a resolution of 8 bits. * These bits select the sampling time for A/D conversion. * When A/D conversion is activated, analog input is fetched during bit14 bit13 ST1, ST0: Sampling time setting bit the time set in this bit. * These bits select the comparison time for A/D conversion. * After analog input is fetched (i.e., sampling time elapses), converbit12 bit11 CT1, CT0: Comparison time setting bit sion result data is defined and stored in bits 9 to 0 of this register after the time set in these bits. bit10 Free bit * The A/D conversion results are stored and the register is rewritten bit9 ~ bit0 ANE2, ANE1, ANE0: A/D conversion end channel selection bit * Usually, the last conversion value is stored. * The initial value of this register is undefined. each time conversion ends. MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 445 16.5 8/10-Bit A/D Converter Interrupts The 8/10-bit A/D converter can generate an interrupt request when the data for the A/D conversion is stored in the A/D data register. This function supports the extended intelligent I/O service (EIOS). s 8/10-bit A/D converter interrupts Table 16.5-1 indicates the interrupt control bits of the 8/10-bit A/D converter and the interrupt cause. Table 16.5-1 Interrupt control bits of the 8/10-bit A/D converter and the interrupt cause 8/10-bit A/D converter Interrupt request flag bit Interrupt request enable bit Interrupt cause ADCS: INT ADCS: INTE Writing the A/D conversion result to the A/D data register When A/D conversion is performed and its result is stored in the A/D data register (ADCR), the INT bit of the A/D control status register (ADCS1) is set to "1". If the interrupt request is enabled (ADCS1: INTE = 1), an interrupt request is output to the interrupt controller. s 8/10-bit A/D converter interrupts and EIOS Table 16.5-2 8/10-bit A/D converter interrupts and EIOS Interrupt control register Interrupt No. Register name #11 (0BH) ICR00 Address 0000B0H Lower FFFFD0H Upper FFFFD1H Bank FFFFD2H Vector table address EIOS o o: Available s EIOS function of the 8/10-bit A/D converter Using the EIOS function, the 10-bit A/D converter can transfer the A/D conversion result to memory. When the transfer is performed, a conversion data protection function halts the A/D conversion until the A/D conversion data is transferred to memory, and clears the INT bit. The function prevents any part of the data from being lost. 446 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series 16.6 Operation of the 8/10-Bit A/D Converter The 8/10-bit A/D converter has three conversion modes: single conversion mode, continuous conversion mode, and stop conversion mode. This section describes operation in each mode. s Operation in single conversion mode In single conversion mode, the analog inputs from the channel specified by the ANS bits to the channel specified by the ANE bits are sequentially converted. When the channels up to the end channel specified by the ANE bits have been converted, A/D conversion stops. If the start and end channels are the same (ANS = ANE), just the channel specified by the ANS bits is converted. Figure 16.6-1 shows the settings required for operation in single conversion mode. Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADCS BUSY INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCR S10 ST1 ST0 CT1 CT0 - Holds the conversion data. ADER : Used : Set to 1 the bit corresponding to the pin used. 0 : Set 0. Figure 16.6-1 Settings for single conversion mode MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 447 s Operation in continuous conversion mode In continuous conversion mode, the analog inputs from the channel specified by the ANS bits to the channel specified by the ANE bits are sequentially converted. When the end channel specified by the ANE bits has been processed, A/D conversion starts again from the channel specified by the ANS bits. If the start and end channels are the same (ANS = ANE), the conversion of the channel specified by the ANS bits is repeated. Figure 16.6-2 shows the settings required for operation in continuous conversion mode. Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 ADCS BUSY INT Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCR S10 ST1 ST0 CT1 CT0 - Holds the conversion data. : Used : Set to 1 the bit corresponding to the pin used. 1 : Set 1. 0 : Set 0. ADER Figure 16.6-2 Settings for continuous conversion mode 448 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series s Operation in stop conversion mode In stop conversion mode, the analog inputs from the channel specified by the ANS bits to the channel specified by the ANE bits are sequentially converted with a pause after the conversion of each channel. When the end channel specified by the ANE bits has been processed, A/D conversion, with pauses, starts again with the channel specified by the ANS bits. If the start and end channels are the same (ANS = ANE), the conversion of the channel specified by the ANS bits is repeated. To reactivate conversion during a pause, generate the activation cause specified by the STS1 and STS0 bits. Figure 16.6-3 shows the settings required for operation in stop conversion mode. Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 ADCS Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BUSY INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCR S10 ST1 ST0 CT1 CT0 - Holds the conversion data. : Used : Set to 1 the bit corresponding to the pin used. 1 : Set 1. 0 : Set 0. ADER Figure 16.6-3 Settings for stop conversion mode MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 449 16.6 Operation of the 8/10-Bit A/D Converter 16.6.1 Conversion using EIOS The 8/10-bit A/D converter can use EIOS transfer the A/D conversion result to memory. s Conversion using EIOS Figure 16.6-4 shows the operation flow when EIOS is used. Start A/D conversion Sample and hold EI2OS started Conversion Transfer data End conversion Generate an interrupt Has the data transfer been repeated for the specified number of times? (*1) YES Interrupt processing NO Interrupt cleared *1 The number of times is determined by an EI2OS setting. Figure 16.6-4 Sample operation flowchart when EIOS is used When EIOS is used, the conversion data protection function prevents any part of the data from being lost even in continuous conversion. Multiple data items can be safely transferred to memory. 450 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series Memo MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 451 16.6 Operation of the 8/10-Bit A/D Converter 16.6.2 A/D conversion data protection function When A/D conversion is performed in the interrupt enabled state, the conversion data protection function operates. s A/D conversion data protection function The A/D converter has just one data register that holds conversion data. When a single A/D conversion is completed, the data in the data register is rewritten. If the conversion data were not transferred to memory before the next conversion data was stored, part of the conversion data would be lost. The data protection function operates in the interrupt enabled state (INTE = 1), as described below, to prevent loss of data. q Data protection function when EIOS is not used When conversion data is stored in the A/D data register (ADCR), the INT bit of the A/D control status register 1 (ADCS1) is set to "1". While the INT bit is "1", A/D conversion is halted. Halt status is released when the INT bit is cleared after data in the A/D data register (ADCR) has been transferred to memory by the interrupt routine. q Data protection function when EIOS is used In continuous conversion using EIOS, the PAUS bit of the A/D control status register1 (ADCS1) is kept at "1" when a conversion ends. This status continues until EIOS finishes transferring the conversion data from the data register to memory. In the meantime, the A/D conversion is halted, and the next conversion data is not stored. When the data transfer to memory is completed, the PAUS bit is cleared to "0", conversion and conversion resumes. Figure 16.6-5 shows the operation flow of the data protection function when EIOS is used. 452 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series Set EI2OS Start continuous A/D conversion End first conversion Store data in the data register End second conversion Activate EI2OS Has EI2OS ended? YES Store data in the data register NO Halt A/D Third conversion Continue Terminate all conversions Continue Store data in the data register Activate EI2OS Activate EI2OS Interrupt processing routine Initialize or stop A/D End Figure 16.6-5 Operation flowchart of the data protection function when EIOS is used * MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 453 16.7 Usage Notes on the 8/10-Bit A/D Converter Notes on using the 8/10-bit A/D converter. s Usage notes on the 8/10-bit A/D converter q Analog input pin The A/D input pins are also used as the I/O pins of port 5. The port 5 data register (DDR5) and analog input enable register (ADER) determine which pin is used for which purpose. To use a pin as analog input, write "0" to the corresponding bit of DDR5 and change the port setting to input. Then, set the analog input mode (ADEx = 1) in the ADER register and determine the input gate of the port. If an intermediate-level signal is input in the port input mode (ADEx = 0), a leakage current flows through the gate. q Note on using an internal timer To start the A/D converter with an internal timer, set the STS1 and STS0 bits of A/D control status register 1 (ADCS1) accordingly. Set the input value of the internal timer at the inactive level (L for the internal timer). Otherwise, operation may start concurrently with writing to the ADCS register. q Sequence of turning on the A/D converter and analog input Do not turn on power to the A/D converter (AVcc, AVR+, AVR-) and to the analog inputs (AN0 to AN7) before the digital power supply (Vcc) has been turned on. Do not turn off the digital power supply (Vcc) before power to the A/D converter and the analog inputs has been turned off. q Supply voltage to the A/D converter The supply voltage to the A/D converter (AVcc) must not exceed the digital power supply (Vcc); otherwise, latchup may occur. 454 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series Memo MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 455 16.8 Sample Program 1 for Single Conversion Mode Using EIOS This section contains a sample program for A/D conversion in single conversion mode using EIOS. s Sample program for single conversion mode using EIOS q Processing * * * * Analog inputs AN1 to AN3 are converted once. The conversion data is sequentially transferred to addresses 200H to 205H. A resolution of 10 bits is selected. The conversion is activated by software. Figure 16.8-1 shows a flowchart of the program using EIOS (single conversion mode). Start conversion AN1 AN1 AN1 End Interrupt Interrupt Interrupt Transfer by EI2OS Transfer by EI2OS Transfer by EI2OS Interrupt sequence Parallel processing Figure 16.8-1 Flowchart of program using EIOS (single conversion mode) q Coding example BAPL BAPM BAPH ISCS IOAL IOAH DCTL DCTH DDR5 ADER ICR00 ADCS0 ADCS1 ADCR0 ADCR1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 000100H 000101H 000102H 000103H 000104H 000105H 000106H 000107H 000015H 000017H 0000B0H 000034H 000035H 000036H 000037H ; Lower buffer address pointer ; Intermediate buffer address pointer ; Upper buffer address pointer ; EIOS status register ; Lower I/O address register ; Upper I/O address register ; Lower data counter ; Upper data counter ; Port 5 direction register ; Analog input enable register ; Interrupt control register for A/DC ; A/D control status register ; ; A/D data register ; 456 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series ;-------Main program--------------------------------------------------------------------------------------------------------------CODE START: AND MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV OR LOOP: MOV MOV BRA ED_INT1: MOV RETI CODE VECT ENDS CSEG ORG DSL ORG DSL DB VECT ENDS END START ABS=0FFH 0FFD0H ED_INT1 0FFDCH START 00H ; Sets single-chip mode. ; Sets reset vector. ; Sets vector for interrupt #31 (1FH) I:ADCS1,#00H ; Stops A/D conversion. Clears and disables the interrupt flag. ; Returns from interrupt. CCR,#0BFH ICR00,#00H BAPL,#00H BAPM,#02H BAPH,#00H ISCS,#18H IOAL,#36H IOAH,#00H DCTL,#03H DDR5,#11110001B ADER,#00001110B CTH,#00H ADCS0,#0BH ADCS1,#0A2H ILM,#07H CCR,#40H A,#00H A,#01H LOOP CSEG ; Assumes that the stack pointer (SP) has already been initialized. ; Disables interrupts. ; Interrupt level: 0 (highest priority) ; Sets the address to which the conversion data is transferred and stored. ; (Uses 200H to 205H.) ; ; Transfers word data, adds 1 to the address, then transfers the data from I/O to memory. ; Sets the address of the analog data register as the ; transfer source address pointer. ; Sets the EIOS transfer count to three, which is the same value as the conversion count. ; Sets P51 to P53 as input. ; Sets P51/AN1 to P53/AN3 as analog inputs. ; ; Single activation. Converts AN1 to AN3. ; Software activation. Begins A/D conversion. Enables interrupts. ; Sets ILM in PS to level 7. ; Enables interrupts. ; Endless loop ;-------Interrupt program---------------------------------------------------------------------------------------------------------- ;-------Vector setting--------------------------------------------------------------------------------------------------------------- MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 457 16.9 Sample Program 2 for Continuous Conversion Mode Using EIOS This section contains a sample program for A/D conversion in continuous conversion mode using EIOS. s Sample program for continuous conversion mode using EIOS q Processing * * * * Analog inputs AN3 to AN5 are converted twice. Two conversion data items are obtained for each channel. The conversion data is sequentially transferred to addresses 600H to 60BH. A resolution of 10 bits is selected. The conversion is activated by 16-bit reload timer 1. Figure 16.9-1 shows a flowchart of the program using EIOS (continuous conversion mode). Start conversion AN3 AN4 AN5 Interrupt Interrupt Interrupt Transfer by EI2OS Transfer by EI2OS Transfer by EI2OS End After a total of six transfers Interrupt sequence Figure 16.9-1 Flowchart of program using EIOS (continuous conversion mode) q Coding example BAPL BAPM BAPH ISCS IOAL IOAH DCTL DCTH DDR5 ADER ICR00 ADCS0 ADCS1 ADCR0 ADCR1 TMCRL1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 000100H 000101H 000102H 000103H 000104H 000105H 000106H 000107H 000015H 000017H 0000B0H 000034H 000035H 000036H 000037H 000086H ; Lower buffer address pointer ; Middle buffer address pointer ; Upper buffer address pointer ; EIOS status register ; Lower I/O address register ; Upper I/O address register ; Lower data counter ; Upper data counter ; Port 5 direction register ; Analog input enable register ; Interrupt control register for A/DC ; A/D control status register ; ; A/D data register ; ;Lower control status register 1 458 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series TMCRH1 EQU RLDRL1 RLDRH1 --------CODE START: AND MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVW MOV MOV MOV MOV OR LOOP: MOV MOV BRA ED_INT1: MOV RETI CODE ENDS CSEG EQU EQU 000087H 000088H 000089H ; ;16-bit reload register ; ;-------Main program------------------------------------------------------------------------------------------------ ; Assumes that the stack pointer (SP) has already been initialized. CCR,#0BFH ICR10,#08H BAPL,#00H BAPM,#06H BAPH,#00H ISCS,#18H IOAL,#36H IOAH,#00H DCTL,#06H DDR5,#00000000B ADER,#00111000B DCTH,#00H ADCS0,#9DH ADCS1,#0A8H TMRLR1,#0320H TMCRH1,#00H TMCRL1,#12H TMCRL1,#13H ILM,#07H CCR,#40H A,#00H A,#01H LOOP ; Disables interrupts. ; Interrupt level; 0 (highest priority). Enables interrupts. ; Sets the address to which conversion data is stored. ; (Uses 600H to 60BH.) ; ; Transfers word data, adds 1 to the address, then ; transfers from I/O to memory. ; Sets the address of the analog data register as the ; transfer source address pointer. ; Six transfers by EIOS (two transfers each for three channels) ; Sets P50 to P57 as input. ; Sets P53/AN3 to P55/AN5 as analog input. ; ; Continuous conversion mode. Converts AN3 to AN5 CH. ; Activates the 16-bit timer, starts A/D conversion, and enables interrupts. ; Sets the timer value to 800 (320h), 100 s. ; Sets the clock source to 125 ns and disables external trigger. ; Disables timer output, disables interrupts, and enables reload. ; Activates the 16-bit timer. ; Sets ILM in PS to level 7. ; Enables interrupts. ; Endless loop ;-------Interrupt program---------------------------------------------------------------------------------------------------------I:ADCS1,#80H ; Does not stop A/D conversion. Clears and disables the interrupt flag. ; Returns from interrupt. ;-------Vector setting---------------------------------------------------------------------------------------------------------------- MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 459 VECT CSEG ORG DSL ORG DSL DB ABS=0FFH 0FFD0H ED_INT1 0FFDCH START 00H START ; Sets single-chip mode. ; Sets reset vector. ; Sets vector for interrupt #11 (0BH). VECT ENDS END 460 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series 16.10 Sample Program 3 for Stop Conversion Mode Using EIOS This section contains a sample program for A/D conversion in stop conversion mode using EIOS. s Sample program for stop conversion mode using EIOS q Processing * * * * Analog input AN3 is converted 12 times at regular intervals. The conversion data is sequentially transferred to addresses 600H to 617H. A resolution of 10 bits is selected. The conversion is activated by 16-bit reload timer. Figure 16.10-1 shows a flowchart of the program using EIOS (stop conversion mode). Start conversion AN3 Stop Interrupt Transfer by EI2OS After 12 transfers Interrupt sequence End Activation by 16-bit reload timer 1 Figure 16.10-1 Flowchart of program using EIOS (stop conversion mode) q Coding example BAPL BAPM BAPH ISCS IOAL IOAH DCTL DCTH DDR5 ADER ICR00 ADCS0 ADCS1 ADCR0 ADCR1 TMCRL1 RLDRL1 RLDRH1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 000100H 000101H 000102H 000103H 000104H 000105H 000106H 000107H 000015H 000017H 0000B0H 000034H 000035H 000036H 000037H 000086H 000087H 000088H 000089H ; Lower buffer address pointer ; Middle buffer address pointer ; Upper buffer address pointer ; EIOS status register ; Lower I/O address register ; Upper I/O address register ; Lower data counter ; Upper data counter ; Port 5 direction register ; Analog input enable register ; Interrupt control register for A/DC ; A/D control status register ; ; A/D data register ; ;Lower control status register 1 ; ;16-bit reload register ; TMCRH1 EQU ;-------Main program------------------------------------------------------------------------------------------------ MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 461 --------CODE START: AND MOV MOV MOV MOV MOV CCR,#0BFH ICR00,#08H BAPL,#00H BAPM,#06H BAPH,#00H ISCS,#19H CSEG ; Assumes that the stack pointer (SP) has already been initialized. ; Disables interrupts. ; Interrupt level: 0 (highest priority). ; Sets the address to which conversion data is stored. ; (Uses 600H to 617H.) ; ; Transfers word data, adds 1 to the address, ; transfers from I/O to memory, then ends by a ; resource request. ; Sets the address of the analog data register as the ; transfer source address pointer. ; Transfers only channel 3 twelve times by EIOS ; Sets P50 to P57 as input. ; Sets P53/AN3 as analog input. ; Stop conversion mode. Converts AN3 CH. ; Activates the 16-bit timer, starts A/D conversion, and enables interrupts. ; Sets the timer value to 800 (320h), 100 s. ; Sets the clock source to 125 ns and disables external trigger. ; Disables timer output, disables interrupts, and enables reload. ; Activates the 16-bit timer. ; Sets ILM in PS to level 7. ; Enables interrupts. ; Endless loop MOV MOV MOV MOV MOV MOV MOV MOVW MOV MOV MOV MOV OR LOOP: MOV MOV BRA ED_INT1: MOV RETI CODE VECT ENDS CSEG ORG DSL ORG DSL DB VECT ENDS END IOAL,#36H IOAH,#00H DCTL,#0CH DDR5,#00000000B ADER,#00001000B ADCS0,#0DBH ADCS1,#0A8H TMRLR1,#0320H TMCRH1,#00H TMCRL1,#12H TMCRL1,#13H ILM,#07H CCR,#40H A,#00H A,#01H LOOP ;-------Interrupt program---------------------------------------------------------------------------------------------------------I:ADCS1,#80H ; Does not stop A/D conversion. Clears and disables the interrupt flag. ; Returns from interrupt. ;-------Vector setting---------------------------------------------------------------------------------------------------------------ABS=0FFH 0FFD0H ED_INT1 0FFDCH START 00H START ; Sets single-chip mode. ; Sets reset vector. ; Sets vector for interrupt #11 (0BH). 462 CHAPTER 16 8/10-BIT A/D CONVERTER MB90560 series Memo MB90560 series CHAPTER 16 8/10-BIT A/D CONVERTER 463 CHAPTER 17 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and operation of the MB90506 series. 17.1 Overview of the Address Match Detection Function..................... 466 17.2 Example of Using the Address Match Detection Function............ 469 17.1 Overview of the Address Match Detection Function An instruction code to be read by the CPU is replaced forcibly with an INT9 instruction code (01H) when the corresponding address is equal to the value set in an address detection register. Therefore, the CPU executes the INT9 instruction when executing the set instruction. A program patch application function can be implemented by processing with the INT #9 interrupt routine.There are two address detection registers, of which each is provided with an interrupt enable bit and interrupt flag. When the address is equal to the value set in the address detection register, and the interrupt enable bit is "1", assume the following: the interrupt flag is set to "1", and the instruction code to be read by the CPU is replaced forcibly with the INT9 instruction code. The interrupt flag is cleared to "0" by writing "0" to it using an instruction. s Registers Byte PADR0 address :1FE2H / 1FE1H / 1FE0H Byte Byte Access R/W Initial value Undefined PADR1 address :1FE5H / 1FE4H / 1FE3H Bit No. PACSR address :00009EH 7 Reserved R/W 6 Reserved Undefined 5 4 3 2 1 0 Initial value Reserved Reserved AD1F AD1D AD1F AD0D 00000000B - - - - R/W R/W R/W R/W s Block Diagram Address latch Address detection Compare F2MC-16LX bus Reset F2MC-16LX Enable bit CPU core Detection bit Set Figure 17.1-1 Block diagram 466 CHAPTER 17 ADDRESS MATCH DETECTION FUNCTION MB90560 series s Register Details q Program address detect register 0/1: PADR0/PADR1: The value written to each register is compared with a target address. If the value matches the address, and the corresponding interrupt enable bit of the PACSR register is "1", the corresponding interrupt bit is set to "1" to request the CPU to generate an INT9 instruction. If the corresponding interrupt enable bit is "0", no operation is performed. Byte PADR0 address :1FF2 H /1FF1H /1FF0 H PADR1 address :1FF5 H /1FF4 H /1FF3 H Byte Byte Access R/W R/W Initial value Indefinite Indefinite The following lists the correspondence between the program address detection register and PACSR: Address detection register PADR0 PADR1 AD0E AD1E Interrupt enable bit AD0D AD1D Interrupt bit q Program address detect control or status register: PACSR Bit No. PACSR address:00009E H 7 Reserved 6 5 4 Reserved 3 2 1 0 Initial value 0000000 Reserved Reserved AD1E AD1D AD0E AD0D - - - - R/W R/W R/W R/W This register controls the operation of the address detection function and indicates its status. [bit 7 to bit 4]: Reserved bits Reserved bits. Be sure to write 0 to these bits. [bit 3]: Address Detect Register 1 Enable (AD1E) ADR1 operation enable bit. When this bit is "1", the value set in the PADR1 register is compared with the address. If the two values are equal, an INT9 instruction is generated and the AD1D bit is set to "1". [bit 2]: Address Detect Register1's is Detected (AD1D) ADR1 address match detection bit. This bit is set to "1" to indicate that the value set in the PADR1 register matches the address. It is cleared to "0" by writing "0" to it. It is left unchanged by writing "1" to it. [bit 1]: Address Detect Register 0 Enable (AD0E) ADR0 operation enable bit. When this bit is "1", the value set in the PADR0 register is compared to the address. If they match, an INT9 instruction is generated, and the AD0D bit is set to "1". MB90560 series CHAPTER 17 ADDRESS MATCH DETECTION FUNCTION 467 [bit0]: Address Detect Register0's is Detected (AD0D) ADR0 address match detection bit. This bit is set to "1" to indicate that the value set in the PADR0 register is equal to the address. It is cleared to "0" by writing "0" to it. It is left unchanged by writing "1" to it. s Operation of the Address Match Detection Function An instruction code to be read by the CPU is replaced forcibly with an INT9 instruction code (01H) when the corresponding address is equal to the value set in an address detection register. Therefore, the CPU executes the INT9 instruction when executing the set instruction. A program patch application function can be implemented by processing with the INT #9 interrupt routine. There are two address detection registers, of which each is provided with an interrupt enable bit and interrupt flag. When the address is equal to the value set in the address detection register, and the interrupt enable bit is "1", assume the following: the interrupt flag is set to "1", and the instruction code to be read by the CPU is replaced forcibly with the INT9 instruction code. The interrupt flag is cleared to "0" by writing "0" to it using an instruction. s Notes on the Address Match Detection Function The address match detection function fails if an address later than the first byte of the instruction is set in the address detection register. The value in the set address is replaced with 01H so a wrong instruction is executed or an invalid address is accessed. Before changing the value set in the address detection register, set the interrupt enable bit to "0". If data is written while the interrupt enable bit is "1", the address may be wrongly detected during writing, causing a malfunction. 468 CHAPTER 17 ADDRESS MATCH DETECTION FUNCTION MB90560 series 17.2 Example of Using the Address Match Detection Function This section contains example of Using the Address Match Detection Function. s System Configuration MCU F 2 MC-16LX E2 PROM SIN Pull-up resistor Connector (UART) Figure 17.2-1 System configuration example s EEPROM Memory Map Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0010H+ Number of bytes of patch program No. 0 Meaning Number of bytes of patch program No. 0 ("0" for no program error) Bit 7 to bit 0 of program address No. 0 Bit 15 to bit 8 of program address No. 0 Bit 24 to bit 26 of program address No. 0 Number of bytes of patch program No. 1 ("0" for no program error) Bit 7 to bit 0 of program address No. 1 Bit 15 to bit 8 of program address No. 1 Bit 24 to bit 16 of program address No. 1 Original of patch program No. 0 s Initial State The contents of EEPROM are all "0"s. s If a Program Error Occurs The original of a patch program and its address are transferred to the MCU via the connector (UART). The MCU writes the information to EEPROM. MB90560 series CHAPTER 17 ADDRESS MATCH DETECTION FUNCTION 469 s Reset Sequence After the reset sequence is completed, the MCU reads the value of EEPROM. If the number of bytes of the patch program is not "0", the MCU reads the original patch program and writes it to RAM. Then, the MCU sets the program address to PADR0 or ADR1 and enables the program to run. The first address of the program written to RAM is saved in RAM as specified for each address detection register. s INT9 Interrupt During execution of an interrupt routine, control checks the interrupt flag for an address in which an interrupt was enabled, and branches to the corresponding program. The information stacked by the interrupt is deleted. The interrupt flag is also cleared. MB90560 Abnormal program ROM PC = generated address Interrupt-generated address External E 2 PROM Register set for program patch -Number of program bytes -Interrupt-generated address - Modification program ddress Data transfer using UART Modification program RAM 000000h Figure 17.2-2 System configuration example 470 CHAPTER 17 ADDRESS MATCH DETECTION FUNCTION MB90560 series Reset INT9 Read 00b of E PROM 2 YES 000h( E PROM)=0 NO 2 Clear interrupt program To patch program Read address 2 0001h 0003h (E PROM) MOV Execute patch program Read patch program 0010h 0090h ( E2PROM) MOV End patch program Enable patch processing Executes the normal program NO PC-PAD0 YES INT9 MB90562 FFFFFFh FFC050h ROM E PROM FFFFh 0090h Patch program 0010h 000900h Stack area Lower program address: 00 2 Abnormal program FFC000h FF0000h RAM area 000480h RAM 000400h 000100h I/O area 000000h 0003h Medium program address: 00 Patch program RAM/register area 0002h Upper program address: 00 0001h 0000h Number of bytes of patch program: 80 Figure 17.2-3 Flowchart of program patch processing MB90560 series CHAPTER 17 ADDRESS MATCH DETECTION FUNCTION 471 CHAPTER 18 ROM MIRRORING FUNCTION SELECTION MODULE This chapter explains the function and operation of the MB90560 series ROM mirroring function selection module. 18.1 Overview of the ROM Mirroring Function Selection Module......... 474 18.1 Overview of the ROM Mirroring Function Selection Module The ROM mirroring function selection module can access bank FF located in ROM from bank 00 by setting the register. s Registers bit ROMM address :00006FH 15 14 13 12 11 10 9 - 8 MI W Initial value - - - - - - ------- 1 B s Block Diagram ROM mirroring function selection Address area Bank FF Bank 00 F MC-16LX bus 2 ROM Figure 18.1-1 Block diagram s Register Details q ROMM (ROM mirroring function selection register) bit ROMM address :00006FH 15 14 13 12 11 10 9 - 8 MI W Initial value - - - - - - ------- 1 B FFFFFFh Address 1 ROM area ROM area 010000h 004000h ROM area Address 2 000100h 0000C0h 000000h I/O area When MI=1 I/O area When MI=0 RAM area RAM area Internal area MB90561 Address 1 Address 2 FF8000h 000500h MB90562 FF0000h 000900h MB90F562 FF0000f 000900h MB90V560 FF0000h 001100h Figure 18.1-2 Memory space MB90560 series CHAPTER 18 ROM MIRRORING FUNCTION SELECTION MODULE 475 APPENDIX The appendixes contain an I/O map and other information and describe instructions. APPENDIX A APPENDIX B APPENDIX C APPENDIX D I/O MAP ......................................................................... 479 INSTRUCTIONS............................................................ 485 512K-BIT FLASH MEMORY.......................................... 545 EXAMPLE OF FMC-16LX MB90F562 CONNECTION FOR SERIAL WRITING................................................. 551 478 APPENDIX A I/O MAP Table A lists the addresses assigned to the registers for peripheral functions in the MB90560 series. s I/O map Table A I/O map Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H ~0FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H ~1FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H SMR0 SCR0 SIDR0/ SODR0 SSR0 SMR1 SCR1 SIDR1 SODR1 SSR1 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 ADER Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Analog input enable register Port 6 direction register Analog input enable register Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Access R/W R/W R/W R/W R/W R/W R/W Prohibited area R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 5, A/D 00000000B 00000000B 00000000B 00000000B *0000000B 00000000B ****0000B 11111111B Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB *XXXXXXXB XXXXXXXXB ****XXXXB Prohibited area Serial mode control register 0 Serial control register 0 Serial Input data register 0/ Serial output data register 0 Serial status register 0 Serial mode control register 1 Serial control register 1 Serial Input data register 1/ Serial output data register 1 Status register 1 R/W R/W UART0 R/W R/W R/W R/W UART1 R/W R/W Prohibited area XXXXXXXXB 00001000B XXXXXXXXB 00001000B 00000000B 00000100B 00000000B 00000100B Table A I/O map (continued) Address Abbreviation Register Communication prescaler control register 0 Access Resource name Communication prescaler (UART0) Initial value 000029H 00002AH 00002BH 00002CH ~2FH 000030H 000031H 000032H ODCR0 R/W 0***0000B Prohibited area CDCR1 Co0mmunication prescaler control register 1 R/W Communication prescaler (UART1) 0***0000B Prohibited area ENIR ENRR ELVR Interrupt/DTP enable register Interrupt/DTP cause register Request level setting register R/W ADCS0 A/D control status register ADCS1 ADCR0 A/D data register ADCR1 PRLL0 PPG0 reload register PRLH0 PRLL1 PPG1 reload register PRLH0 PPGC0 PPGC1 PCS01 PPG0 operation mode register PPG1 operation mode register PPG0/PPG1 clock control register R/W R/W R R or W R/W R/W R/W R/W R/W R/W R/W 8-/16-bit PPG timer (CH0, CH1) 00000000B 00000000B 00000000B XXXXXXXXB 00101*XXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000001B 00000001B 000000**B R/W R/W R/W DTP/external interrupt 00000000B 00000000B 00000000B 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H PRLL2 PPG2 reload register PRLH2 PRLL3 PPG3 reload register PRLH3 PPGC2 PPGC3 PCS23 IPPG2 operation mode register PPG3 operation mode register PPG2/PPG3 clock control register Prohibited area R/W R/W R/W R/W R/W R/W R/W 8-/16-bit PPG timer (CH2, CH3) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000001B 00000001B 000000**B Prohibited area 480 APPENDIX A I/O MAP MB90560 series Table A I/O map (continued) Address 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H CPCLR 000059H 00005AH TCDT 00005BH 00005CH TCCS 00005DH 00005EH Prohibited area 00005FH 000060H IPCP0 000061H 000062H IPCP1 000063H 000064H IPCP2 000065H 000066H IPCP3 000067H 000068H 000069H ICS01 ICS23 Input capture data register CH4 Input capture control register 01 Input capture control register 23 R R/W R/W XXXXXXXXB 00000000B 00000000B Input capture data register CH2 Input capture data register CH3 R R Input capture data register CH1 Input capture data register CH2 R R 16-bit input capture (CH00 to CH3) XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Input capture data register CH0 Input capture data register CH1 R R XXXXXXXXB XXXXXXXXB Input capture data register CH0 R XXXXXXXXB Timer control status register (upper) R/W 00000000B Timer data register (upper) Timer control status register (lower) R/W R/W Compare clear register (upper) Timer data register (lower) R/W R/W 16-bit freerunning timer XXXXXXXXB 00000000B 00000000B 0**00000B TMRR0 DTCR0 TMRR1 DTCR1 TMRR2 DTCR2 SIGCR 8-bit reload register CH0 8-bit timer control register CH0 8-bit reload register CH1 8-bit timer control register CH1 8-bit reload register CH2 8-bit timer control register CH2 Waveform control register Abbreviation PRLL4 PPG4 reload register PRLH4 PRLL5 PPG5 reload register PRLH5 PPGC4 PPGC5 PCS45 PPG4 operation mode register PPG5 operation mode register PPG4/PPG5 clock control register R/W R/W R/W R/W R/W R/W 8-/16-bit PPG timer (CH4, CH5) XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000001B 00000001B 000000**B Register Access R/W Resource name Initial value XXXXXXXXB Prohibited area R/W R/W R/W R/W R/W R/W R/W Waveform generator XXXXXXXXB 00000000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B 00000000B Prohibited area Compare clear register (lower) R/W XXXXXXXXB MB90560 series APPENDIX A I/O MAP 481 Table A I/O map (continued) Address 00006AH ~6EH 00006FH 000070H OCCP0 000071H 000072H OCCP1 000073H 000074H OCCP2 000075H 000076H OCCP3 000077H 000078H OCCP4 000079H 00007AH OCCP5 00007BH 00007CH 00007DH 00007EH 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH ~8BH OCS0 OCS1 OCS2 OCS3 OCS4 OCS5 TMCR0:L TMCR0:H TMR0:L/ TMRLR0:L TMR0:H TMRLR0:H TMCR1:L TMCR1:H TMR1:L/ TMRLR1:L TMR1:H TMRLR1:H Compare register CH5 (upper) Compare control register CH0 Compare control register CH1 Compare control register CH2 Compare control register CH3 Compare control register CH4 Compare control register CH5 Timer control status register CH0 (lower) Timer control status register CH0 (upper) 16-bit timer register CH0 (lower)/ 16-bit reload register CH0 (lower) 16-bit timer register CH0 (Upper)/ 16-bit reload register CH0 (upper) Timer control status register CH1 (lower) Timer control status register CH1 (upper) 16-bit timer register CH1 (lower)/ 16-bit reload register CH1 (lower) 16-bit timer register CH1 (Upper)/ 16-bit reload register CH1 (upper) R/W R/W R/W R/W R/W R/W R/W R/W R/W 16-bit reload timer CH0 R/W R/W R/W R/W 16-bit reload timer CH1 R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B ****0000B XXXXXXXXB 0000**00B ***00000B 0000**00B ***00000B 0000**00B ***00000B 00000000B ****0000B Compare register CH4 (upper) Compare register CH5 (lower) R/W R/W Compare register CH3 (upper) Compare register CH4 (lower) R/W R/W Output compare CH0 to CH5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Compare register CH2 (upper) Compare register CH3 (lower) R/W R/W XXXXXXXXB XXXXXXXXB Compare register CH1 (upper) Compare register CH2 (lower) R/W R/W XXXXXXXXB XXXXXXXXB Compare register CH0 (upper) Compare register CH1 (lower) R/W R/W XXXXXXXXB XXXXXXXXB ROMM Abbreviation Register Access Prohibited area ROM mirroring function selection register Compare register CH0 (lower) R/W R/W ROM mirroring function *******1B XXXXXXXXB Resource name Initial value Prohibited area 482 APPENDIX A I/O MAP MB90560 series Table A I/O map (continued) Address 00008CH 00008DH 00008EH ~ 9DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H ~ A7H 0000A8H 0000A9H 0000AAH~AD 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H ~ FFH ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 FMCS WDTC TBTC PACSR DIRR LPMCR CKSCR Abbreviation RDR0 RDR1 Register Port 0 pull-up resistor setting register Port 1 pull-up resistor setting register Access R/W R/W Resource name Port 0 Port 1 Initial value 00000000B 00000000B Prohibited area Program address detect control or status register Delayed interrupt cause/clear register Low-power consumption mode register Clock selection register R/W R/W R/W R/W Prohibited area Watchdog control register Timebase timer control register R/W R/W Watchdog timer Timebase timer *****111B 1**00100B Address match detection Delayed interrupt Low-power consumption control register 11000000B *******0B 00011000B 11111100B Prohibited area Flash memory control status register R/W Flash memory interface circuit 000X0XX0B Prohibited area Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B Unused area MB90560 series APPENDIX A I/O MAP 483 Table A I/O map (continued) Address 000100H ~ #H #H ~ 001FEFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 001FF6H ~ 1FFFH PADR1 PADR0 Abbreviation Register Access RAM area Reserved area Program address detection register 0 Program address detection register 1 Program address detection register 2 Program address detection register 3 Program address detection register 4 Program address detection register 5 R/W R/W R/W Address match detection R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Resource name Initial value Unused area q Meaning of abbreviations used for reading and writing R/W: Read and write enabled R: W: Read only Write only q Explanation of initial values 0: The bit is initialized to 0. 1: The bit is initialized to 1. X: The initial value of the bit is undefined. *: The bit is not used. Its initial value is undefined. 484 APPENDIX A I/O MAP MB90560 series APPENDIX B INSTRUCTIONS This appendix describes the instructions used by the F2MC-16LX. B.1 Instructions ..................................................................................... 486 B.2 Addressing ..................................................................................... 488 B.3 Direct Addressing ........................................................................... 490 B.4 Indirect Addressing......................................................................... 496 B.5 Number of Execution Cycles .......................................................... 503 B.6 Effective-address field .................................................................... 506 B.7 Reading the Instruction List............................................................ 507 B.8 List of F2MC-16LX Instructions ...................................................... 510 B.9 Instruction Maps ............................................................................. 523 B.1 Instructions The FMC-16LX uses the 351 instructions listed below. Addresses must be specified in the effective address field of an instruction or by an instruction code. s Overview of instructions The F2MC-16L uses the 351 instructions listed below. * * * * * * * * * * * * * * * * * Transfer (byte): Transfer (word, long-word): Addition/subtraction (byte, word, long-word): Increment/decrement (byte, word, long-word): Comparison (byte, word, long-word): Unsigned multiplication/division (word, long-word) Signed multiplication/division (word, long-word) Logical operation (byte, word): Logical operation (long-word): Sign inversion (byte, word): Normalization (long-word): Shift (byte, word, long-word,): Branching: Accumulator operation (byte, word): Other types of control (byte, word, long-word): Bit operation: String: 41 instructions 38 instructions 42 instructions 12 instructions 11 instructions 11 instructions 11 instructions 39 instructions 6 instructions 6 instructions 1 instruction 18 instructions 50 instructions 6 instructions 28 instructions 21 instructions 10 instructions 486 APPENDIX B INSTRUCTIONS MB90560 series Memo MB90560 series APPENDIX B INSTRUCTIONS 487 B.2 Addressing The F2MC-16LX determines the address format according to the instruction's effectiveaddress field or from the instruction code (the address format is implied). When the address format is determined from the instruction code, the address format that matches the instruction code is used. More than one type of address format can be specified for some instructions. s Addressing The F2MC-16LX uses the following 23 types of addressing: * * * * * * * * * * * * * * * * * * * * * * * * Immediate (#imm) Register direct Direct branch (addr16) Physical direct branch (addr24) I/O direct (io) Condensed direct (dir) Direct (addr16) I/O direct bit (io:bp) Condensed direct bit (dir:bp) Direct bit (addr16:bp) Vector (#vct) Register indirect (@RWj j = 0 to 3) Register indirect with post-incrementing (@RWj+ j = 0 to 3) Register indirect with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3) Long-word register indirect with displacement (@RLi+disp8 i = 0 to 3) Program counter indirect with displacement (@PC+disp16) Register indirect with base index (@RW0+RW7, @RW1+RW7) Program counter relative branch (rel) Register list (rlst) Accumulator indirect (@A) Accumulator indirect branch (@A) Indirect designation branch (@ear) Indirect designation branch (@eam) 488 APPENDIX B INSTRUCTIONS MB90560 series s Effective-address field Table B.2-1 lists the address formats specified by the effective-address field. Table B.2-1 Effective-address field Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 @RW0 @RW1 @RW2 @RW3 @RW0+ @RW1+ @RW2+ @RW3+ @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 WRW0+RW7 @RW1+RW7 @PC+disp16 addr16 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RLL1) RL2 (RL2) RL3 (RL3) Address format Default bank Register direct ea corresponds to byte, word, and long-word formats in order from the left. None Register indirect DTB DTB ADB SPB DTB DTB ADB SPB DTB DTB ADB SPB DTB DTB ADB SPB DTB DTB ADB SPB DTB DTB SPB ADB Register indirect with post-incrementing Register indirect with 8-bit displacement Register indirect with 8-bit displacement Register indirect with 16-bit displacement Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address MB90560 series APPENDIX B INSTRUCTIONS 489 B.3 Direct Addressing In direct addressing, operand values, registers, and addresses are specified directly. s Direct addressing q Immediate addressing (#imm) Operand values are specified directly (#imm4/#imm8/#imm16/#imm32). Figure B.3-1 shows an example. MOVW A, #01212H (Instruction that stores the operand value in A) Before execution After execution (Some instructions transfer data from AL to AH.) Figure B.3-1 Example of immediate addressing (#imm) q Register direct addressing Operand values specify registers directly. The following registers can be specified: General-purpose register Byte Word Long-word Dedicated registers Accumulator Pointer Bank Page Control R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RL0, RL1, RL2, RL3 A, AL SP (*1) PCB, DTB, USB, SSB, ADB DPR PS, CCR, RP, ILM *1 The SP register functions as a user stack pointer (USP) or system stack pointer (SSP) depending on the S flag bit value indicated in the condition code register (CCR). For branching instructions, the program counter (PC) is not specified as an operand, but is implicitly specified. Figure B.3-2 shows an example. 490 APPENDIX B INSTRUCTIONS MB90560 series MOV R0, A (Instruction that transfers lower 8 bits of A to general-purpose register R0) Before execution Memory space After execution Memory space Figure B.3-2 Example of register direct addressing q Direct branch addressing (addr16) Branch destination addresses are specified directly by displacement. The displacement is 16 bits and is used to specify a branch destination within the logical space. This method is used for unconditional branching instructions, subroutine call instructions, and software interrupt instructions. Address bits 16 to 23 are specified by the program bank register (PCB). Figure B.3-3 shows an example of direct branch addressing (addr16). JMP 3B20H (Unconditional branch instruction with direct branch address specified in the bank) Before execution Memory space After execution Next instruction Figure B.3-3 Example of direct branch addressing (addr16) q Physical direct branch addressing (addr24) Branch destination addresses are specified directly by displacement. The displacement is 24 bits. This method is used for unconditional branching instructions, subroutine call instructions, and software interrupt instructions. Figure B.3-4 shows an example of physical direct branch addressing (addr24). MB90560 series APPENDIX B INSTRUCTIONS 491 JMPP 333B20H (Unconditional branch instruction with 24-bit direct branch address specified) Before execution Memory space After execution Next instruction Figure B.3-4 Example of physical direct branch addressing (addr24) q I/O direct addressing (io) This method specifies memory addresses of the operand directly using an 8-bit displacement. Regardless of the values of the data bank register (DTB) and direct page register (DPR), the I/O space at physical addresses 000000H to 0000FFH is accessed. Prefix instructions designating banks specified before instructions using this addressing method are invalid. Figure B.3-5 shows an example of I/O direct addressing (io). MOVW A, i:0C0H (Instruction that reads data by I/O direct addressing and stores it in A) Before execution Memory space After execution Figure B.3-5 Example of I/O direct addressing (io) q Condensed direct addressing (dir) This method uses the operand to specify the lower eight bits of a memory address directly. Address bits 8 to 15 are specified by the DPR register. Address bits 16 to 23 are specified by the DTB register. Figure B.3-6 shows an example of condensed direct addressing (dir). MOV S:20H, A (Instruction that writes the lower eight bits of A by condensed direct addressing) Before execution Memory space Memory space After execution Figure B.3-6 Example of condensed direct addressing (dir) 492 APPENDIX B INSTRUCTIONS MB90560 series q Direct addressing (addr16) Operand values specify lower 16 bits of an memory address directly. Address bits 16 to 23 are specified by the DTB register. Prefixed instructions that specify the access space are invalid for this type of addressing. Figure B.3-7 shows an example of direct addressing (addr16). Figure B.3-7 Example of direct addressing (addr16) q I/O direct bit addressing (io:bp) This method directly specifies bits within the physical address range from 000000H to 0000FFH. The bit location is expressed as :bp, with higher values representing a more significant bit (MSB) and lower values representing a less significant bit (LSB). Figure B.3-8 shows an example of I/O direct bit addressing (io:bp). SETB i:0C1H:0 (Instruction that sets a bit using I/O direct bit addressing) Memory space Before execution Memory space After execution Figure B.3-8 Example of I/O direct bit addressing (io:bp) q Condensed direct bit addressing (dir:bp) This method uses the operand to specify the lower eight bits of the memory address. Address bits 8 to 15 are specified by the DPR register and address bits 16 to 23 are specified by the DTB register. The bit location is expressed as :bp, with a higher value representing an MSB and a lower value representing a, LSB. Figure B.3-9 shows an example of condensed direct bit addressing (dir:bd). MB90560 series APPENDIX B INSTRUCTIONS 493 SETB S:10H:0 (Instruction that sets a bit using condensed direct bit addressing) Memory space Before execution Memory space After execution Figure B.3-9 Example of condensed direct bit addressing (dir:bp) q Direct bit addressing (addr16:bp) This method directly specifies any bit within the 64-kilobyte area. Address bits 16 to 23 are specified by the DTB register. The bit location is expressed as :bp, with a higher value representing an MSB and a lower value representing an LSB. Figure B.3-10 shows an example of direct bit addressing (addr16:bp). SETB 2222H:0 (Instruction sets a bit using direct bit addressing) Memory space Before execution Memory space After execution Figure B.3-10 Example of direct bit addressing (addr16:bp) q Vector addressing (#vct) In this method, the contents of the specified vector indicates the branch destination address. The data length of the vector number may be either four bits or eight bits. This method is used for subroutine call instructions and software interrupt instructions. Figure B.3-11 shows an example of vector addressing (#vct). CALLV #15 (Instruction that branches to the address specified by the interrupt vector specified by the operand) Before execution Memory space After execution Figure B.3-11 Example of vector addressing (#vct) 494 APPENDIX B INSTRUCTIONS MB90560 series Table B.3-1 CALLV vectors Instruction CALLV #0 CALLV #1 CALLV #2 CALLV #3 CALLV #4 CALLV #5 CALLV #6 CALLV #7 CALLV #8 CALLV #9 CALLV #10 CALLV #11 CALLV #12 CALLV #13 CALLV #14 CALLV #15 Vector address (low) XXFFFeH XXFFFCH XXFFFAH XXFFF8H XXFFF6H XXFFF4H XXFFF2H XXFFF0H XXFFEEH XXFFECH XXFFEAH XXFFE8H XXFFE6H XXFFE4H XXFFE2H XXFFE0H Vector address (high) XXFFFFH XXFFFDH XXFFFBH XXFFF9H XXFFF7H XXFFF5H XXFFF3H XXFFF1H XXFFEFH XXFFEDH XXFFEBH XXFFE9H XXFFE7H XXFFE5H XXFFE3H XXFFE1H MB90560 series APPENDIX B INSTRUCTIONS 495 B.4 Indirect Addressing In indirect addressing, the operand specifies indirectly the address of the data. s Indirect addressing q Register indirect addressing (@RWj j = 0 to 3) This type of addressing accesses memory at the address indicated by the contents of generalpurpose register RWj. Address bits 16 to 23 are specified by the DTB register if RW0 or RW1 is used, by the system stack bank register (SSB) or user stack bank register (USB) if RW3 is used, and by the additional data bank register (ADB) if RW2 is used. Figure B.4-1 shows an example of register indirect addressing (@RWj, j= 0 to 3). MOVW A, @RW1 (Instruction that reads data using register indirect addressing and stores it in A) Before execution Memory space After execution Figure B.4-1 Example of register indirect addressing (@RWj j = 0 to 3) q Register indirect addressing with post-incrementing (@RWj+ j = 0 to 3) This type of addressing accesses memory at the address indicated by the contents of generalpurpose register RWj. After the operand has been operated on, register RWj is incremented by the length of the operand data (one for byte length, two for word length, four for long-word length). Address bits 16 to 23 are specified by the DTB register if RW0 or RW1 is used, by the SSB or USB register if RW3 is used, and by the ADB register if RW2 is used. Note that if the results of post-incrementing are the address of the same register that specified the increment, the value to be referenced after incrementing will be the incremented value. Also, if a write instruction is used, the write operation will have priority, so that the register that is supposed to be incremented receives the write data. Figure B.4-2 shows an example of register indirect addressing with post-incrementing (@RWj+, j = 0 to 3). MOVW A, @RW1+ (Instruction that reads data by register indirect addressing with post-incrementing and stores it in A) Before execution Memory space After execution 496 Figure B.4-2 Example of register indirect addressing with post-incrementing (@RWj+ j = 0 to 3) APPENDIX B INSTRUCTIONS MB90560 series q Register indirect addressing with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3) This type of addressing accesses memory at an address derived from the contents of the general-purpose register RWj with a displacement added. Displacements may be either byte or word length, and are added as signed numerical values. Address bits 16 to 23 are specified by the DTB register if RW0, RW1, RW4, or RW5 is used, by the SSB or USB register if RW3 or RW7 is used, and by the ADB register if RW2 or RW6 is used. Figure B.4-3 shows an example of register indirect addressing with displacement (@RWi+disp8, i = 0 to 7; @RWj+disp16, j = 0 to 3). MOVW A, @RW1+10H (Instruction that reads data by register indirect addressing with displacement and stores it in A) Before execution Memory space After execution Figure B.4-3 Example of register indirect addressing with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3) q Long-register indirect addressing with displacement (@RLi+disp8 i = 0 to 3) This type of addressing accesses memory at an address derived by using the lower 24 bits of the sum of the contents of general-purpose register RLi plus a displacement. The displacement is 8 bits, and is added as a signed numerical value to the RLi contents. Figure B.4-4 shows an example of long-register indirect addressing with displacement (@RLi+disp8, i = 0 to 3). MOVW A, @RL2+25H (Instruction that reads data by long-word register indirect addressing with displacement and stores it in a) Before execution Memory space After execution Figure B.4-4 Example of long-word register indirect addressing with displacement(@RLi+disp8 i = 0 to 3) MB90560 series APPENDIX B INSTRUCTIONS 497 q Program counter indirect addressing with displacement (@PC+disp16) This type of addressing accesses memory at an address determined by the formula (instruction address+4+disp16). The displacement is word-length data. Address bits 16 to 23 are specified by the PCB register. Note that the operand addresses of the following instructions are not considered to be (next instruction address+disp16): * * * * * * DBNZ eam,rel DWBNZ eam,rel CBNE eam,#imm8,rel CWBNE eam,#imm16,rel MOV eam,#imm8 MOVW eam,#imm16 Figure B.4-5 shows an example of program counter indirect addressing with displacement (@PC+disp16). MOVW A, @PC+20H (Instruction that reads data with PC indirect addressing with displacement and stores it in A) Memory space Before execution After execution Figure B.4-5 Example of program counter indirect addressing with displacement (@PC+disp16) 498 APPENDIX B INSTRUCTIONS MB90560 series q Register indirect addressing with base index (@RW0+RW7, @RW1+RW7) This type of addressing accesses memory at an address determined by adding the contents of general-purpose register RW7 to RW0 or RW1. Address bits 16 to 23 are specified by the DTB register. Figure B.4-6 shows an example of register indirect addressing with a base index (@RW0+RW7, @RW1+RW7). MOVW A, @RW1+RW7 (Instruction that reads data by register indirect addressing with base index and stores it in A) Before execution Memory space After execution Figure B.4-6 Example of register indirect addressing with base index (@RW0+RW7, @RW1+RW7) q Program counter relative branch addressing (rel) A branch destination address is represented as the program counter (PC) value plus an 8-bit displacement. Because the bank register is not incremented or decremented and overflow is ignored if the result is over 16 bits, the result is an address within the 64-kilobyte bank. This addressing method is used for unconditional and conditional branch instructions. Address bits 16 to 23 are specified by the PCB register. Figure B.4-7 shows an example of program counter relative branch addressing (rel). BRA 3B20H (Unconditional relative branch instruction) Before execution Memory space After execution Next instruction Figure B.4-7 Example of program counter relative branch addressing (rel) MB90560 series APPENDIX B INSTRUCTIONS 499 q Register list (rlst) This addressing method specifies registers that are used by push/pop instructions for stack operations. Figure B.3h shows the register list configuration. Figure B.4-8 shows the register list configuration. Figure B.4-9 shows an example of the register list (list). Selected when the corresponding bit is set to 1 and not selected when it is set to 0. Figure B.4-8 Register list configuration POPW RW0, RW4 (Instruction that transfers data at the memory locations specified by the SP to the word registers in the register list) Memory space Memory space Before execution After execution Figure B.4-9 Example of register list (rlst) q Accumulator indirect addressing (@A) This addressing method accesses memory at the address indicated by the contents (16 bits) of the lower bytes of the accumulator (AL). Address bits 16 to 23 are specified by the DTB register as mnemonics. Figure B.4-10 shows an example of accumulator indirect addressing (@A). MOVW A, @A (Instruction that reads data by accumulator indirect addressing and stores it in A) Before execution Memory space After execution Figure B.4-10 Example of accumulator indirect addressing (@A) 500 APPENDIX B INSTRUCTIONS MB90560 series q Accumulator indirect branch addressing (@A) The 16-bit contents of the lower bytes of the accumulator (AL) indicate the branch destination address, which specifies a branch destination within the bank space. Address bits 16 to 23 are specified by the PCB register. If the Jump Context (JCTX) instruction is used, address bits 16 to 23 are specified by the DTB register. This addressing method is used for unconditional branching instructions. Figure B.4-11 shows an example of accumulator indirect branch addressing (@A). JMP @A (Unconditional branch instruction that uses accumulator indirect branch addressing) Before execution Memory space After execution Next instruction Figure B.4-11 Example of accumulator indirect branch addressing (@A) q Indirect designation branch addressing (@ear) In this type of addressing, the branch destination address is the word data at the address specified by the ear parameter. Figure B.4-12 shows an example of indirect designation branch addressing (@ear). JMP @RW0 (Unconditional branch instruction that uses register indirect addressing) Before execution After execution Figure B.4-12 Example of indirect designation branch addressing (@ear) MB90560 series APPENDIX B INSTRUCTIONS 501 q Indirect designation branch addressing (@eam) In this type of addressing, the branch destination address is the word data at the address specified by the eam parameter. Figure B.4-13 shows an example of indirect designation branch addressing (@eam). JMP @@RW0 (Unconditional branch instruction that uses register indirect addressing) Before execution After execution Figure B.4-13 Example of indirect designation branch addressing (@eam) 502 APPENDIX B INSTRUCTIONS MB90560 series B.5 Number of Execution Cycles The number of cycles required to execute an instruction is obtained by adding the number of cycles for the instruction, the compensation value determined by conditions, and the number of cycles for program fetch. s Number of execution cycles The number of cycles required to execute an instruction is obtained by adding the number of cycles for the instruction, the compensation value determined by conditions, and the number of cycles for program fetch. Because a program in memory connected to the 16-bit bus to the built-in ROM is fetched each time an executing instruction exceeds the word boundary, the number of execution cycles increases if data access is interfered with. Because a program in memory connected to the 8-bit external data bus is fetched for each byte of the instruction being executed, the number of execution cycles increases if data access is interfered with. If general-purpose registers, built-in ROM, built-in RAM, built-in I/O, and external data buses are accessed during intermittent operation of the CPU, clocks supplied to the CPU stop for the number of cycles specified by the CG0 and CG1 bits of the low-power consumption mode control register. To calculate the number of cycles needed to execute an instruction during intermittent operation of the CPU, add as a compensation value to the normal number of execution cycles the product of the number of accesses and the number of cycles for the temporary stop. s Calculation of the number of execution cycles Tables B.5-1~ B.5-3 list the number of execution cycles for each instruction and compensation values. Table B.5-1 Number of execution cycles for each type of addressing (a) (*1) Code Operand Number of execution cycles for type of addressing Number of register accesses for type of addressing 00 | 07 08 | 0B 0C | 0F 10 | 17 Ri RWi RLi @RWj Shown in instruction list. Shown in instruction list. 2 1 @RWj+ 4 2 @RWj+disp8 2 1 MB90560 series APPENDIX B INSTRUCTIONS 503 Table B.5-1 Number of execution cycles for each type of addressing (continued) (a) (*1) Code Operand Number of execution cycles for type of addressing Number of register accesses for type of addressing 18 | 1B 1C 1D 1E 1F @RWi+disp16 @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 2 4 4 2 1 1 2 2 0 0 *1 (a) is used for ~ (number of cycles) and B (compensation value) in Section B.7, "Reading the Instruction List." Table B.5-2 Compensation values for calculating the number of execution cycles (b) byte (*1) Operand Number of cycles +0 +0 +0 +1 +1 +1 Number of accesses 1 1 1 1 1 1 (c) word (*1) Number of cycles +0 +0 +2 +1 +4 +4 Number of accesses 1 1 2 1 2 2 (d) long-word (*1) Number of cycles +0 +0 +4 +2 +8 +8 Number of accesses 2 2 4 2 4 4 Internal register Internal memory, even address Internal memory, odd address External data bus 16-bit even address External data bus 16-bit odd address External data bus (*2) 8 bits *1 (b), (c), and (d) are used for ~ (number of cycles) and B (compensation value) in Section B.7, "Reading the Instruction List." *2 When the external data bus is used, the number of cycles for waiting due to ready input and automatic ready should be added. 504 APPENDIX B INSTRUCTIONS MB90560 series Table B.5-3 Compensation values for calculating number of cycles for program fetch Instruction Internal memory External data bus 16 bits External data bus 8 bits Byte boundary +3 Word boundary +2 +3 - MB90560 series APPENDIX B INSTRUCTIONS 505 B.6 Effective-address field Table B.6-1 lists the effective-address field for each code. s Effective-address field Table B.6-1 Effective-address field Number of bytes in address expansion part (*1) Code Notation Address format 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 @RW0 @RW1 @RW2 @RW3 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RLL1) RL2 (RL2) RL3 (RL3) Register direct ea corresponds to byte, word, and long-word formats in order from the left. - Register indirect 0 @RW0+ @RW1+ @RW2+ @RW3+ @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 Register indirect with post-incrementing 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address 2 0 0 2 2 *1 The number of bytes in the address expansion part is used for "+" in the # (number of bytes) column in Section B.7, "Reading the Instruction List." 506 APPENDIX B INSTRUCTIONS MB90560 series B.7 Reading the Instruction List This section explains the items (Table B.7-1) and codes (Table B.7-2) that appear in Section B.7, "List of F2MC-16L Instructions." s Explanation of items covered and instruction codes Table B.7-1 Items covered in instruction list Item Description Uppercase alphabetic characters, symbols: Shown as they appear in assembler. Lowercase alphabetic characters: Placeholders for assembler. Numerics following lowercase alphabetic characters: Indicates the bit length of instructions. Indicates the number of bytes. Indicates the number of cycles. For alphabetic characters in the items, see Table B.3-1. Indicates the number of register accesses during instruction execution. Used for calculating compensation values during intermittent operation of the CPU. Indicates compensation values for calculating the actual number of cycles during instruction execution. The actual number of cycles is the sum of the values in the column. Describes how the instruction operates. Indicates special operations with respect to accumulator bits 08 to 15. Z: Transfers zero. X: Transfers using sign extension. -: No transfer Indicates special operations with respect to the upper 16 bits of the accumulator. *: Transfers from AL to AH. -: No transfer Z: Transfers 00 to AH. X: Using AL sign extension, transfers 00H or FFH to AH. Mnemonic # ~ RG B Operation LH AH I S T N Z V C Indicates status of flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changed as a result of instruction execution. -: Not changed. Z: Set by instruction execution. X: Reset by instruction execution. MB90560 series APPENDIX B INSTRUCTIONS 507 Item Description Indicates a read-modify-write instruction (one which reads data from memory and writes the result in memory with the I instruction). *: Read-modify-write instruction -: Not a read-modify-write instruction RMW Table B.7-1 Symbols used in the instruction list (continued) Symbol A 2-bit accumulator Length in bits varies with the instruction. Byte: Lower 8 bits of AL Word: 16 bits of AL Long-word: 32 bits of AL and AH. Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Condensed direct addressing Direct addressing Physical direct addressing addr24 bits 0 to 15 addr24 bits 16 to 23 I/O area (000000H to 0000FFH) Meaning AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0-15 ad24 16-23 io 508 APPENDIX B INSTRUCTIONS MB90560 series Symbol #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp Meaning 8-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 48-bit immediate data extended to signed 16-bit data 8-bit displacement 16-bit displacement Bit offset value Table B.7-1 Symbols used in the instruction list (continued) Symbol vct4 vct8 ( )b rel ear eam rist Vector number (0 to 15) Vector number (0 to 255) Bit address PC relative branch addressing Effective address designation (codes 00 to 07) Effective address designation (codes 08 to 1F) Register list Meaning MB90560 series APPENDIX B INSTRUCTIONS 509 B.8 List of F2MC-16LX Instructions Tables B.8-1 to B.8-17 list instructions used by F2MC-16LX. Table B.8-1 Transfer instructions (byte): 41 instructions Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RLi+disp8 A,#imm4 A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A Ri,A ear,A eam,A io,A @RLi+disp8,A Ri,ear Ri,eam ear,Ri eam,Ri Ri,#imm8 io,#imm8 dir,#imm8 ear,#imm8 eam,#imm8 @AL,AH / MOV @A,T A,ear A,eam Ri,ear Ri,eam # ~ RG 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x(b) 0 2x(b) Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) (imm8) byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) (imm8) byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi)+disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam) LH Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X Z Z AH I S T N R Z V C RMW - 2 3 3 4 1 2 2 2 2+ 3+(a) 2 3 2 2 2 3 3 10 1 1 2 3 3 4 2 2 2 2 2+ 3+(a) 2 3 2 2 2 3 2 5 3 10 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+(a) 3 10 3 4+(a) 4 5+(a) 2 5 5 2 4+(a) 3 2 4 2+ 5+(a) 2 7 2+ 9+(a) 510 APPENDIX B INSTRUCTIONS MB90560 series Table B.8-2 Transfer instructions (word, long-word): 38 instructions Mnemonic MOVW A,dir MOVW A,addr16 MOVW A,SP MOVW A,RWi MOVW A,ear MOVW A,eam MOVW A,io MOVW A,@A MOVW A,#imm16 MOVW A,@RWi+disp8 MOVW A,@RLi+disp8 MOVW dir,A MOVW addr16,A MOVW SP,A MOVW RWi,A MOVW ear,A MOVW eam,A MOVW io,A MOVW @RWi+disp8,A MOVW @RLi+disp8,A MOVW RWi,ear MOVW RWi,eam MOVW ear,RWi MOVW eam,RWi MOVW RWi,#imm16 MOVW io,#imm16 MOVW ear,#imm16 MOVW eam,#imm16 MOVW @AL,AH / MOVW @A,T XCHW XCHW XCHW XCHW A,ear A,eam RWi,ear RWi,eam # ~ RG 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0 B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2x(c) 0 2x(c) 0 (d) 0 0 (d) Operation word (A) word (A) word (A) word (A) word (A) word (A) word (A) word (A) word (A) word (A) word (A) (dir) (addr16) (SP) (RWi) (ear) (eam) (io) ((A)) imm16 ((RWi)+disp8) ((RLi)+disp8) LH AH I S T N Z V C RMW - 2 3 3 4 1 1 1 2 2 2 2+ 3+(a) 2 3 2 3 3 2 2 5 3 10 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+(a) 3 5 10 3 4+(a) 4 5+(a) 2 5 2 4+(a) 3 word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) word ((RWi)+disp8) (A) word ((RLi)+disp8) (A) word (RWi) (ear) word (RWi) (eam) word (ear) (RWi) word (eam) (RWi) word (RWi) imm16 word (io) imm16 word (ear) imm16 word (eam) imm16 word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear1) (A) long (eam1) (A) 2 4 2+ 5+(a) 2 7 2+ 9+(a) 2 4 2+ 5+(a) 5 3 2 4 2+ 5+(a) MOVL A,ear MOVL A,eam MOVL A,#imm32 MOVL ear,A MOVL eam,A MB90560 series APPENDIX B INSTRUCTIONS 511 Table B.8-3 Addition/subtraction (byte, word, long-word): 42 instructions Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A,ear A,eam A,#imm32 A,ear A,eam A,#imm32 # ~ RG 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0 B 0 (b) 0 (b) 0 2x(b) 0 0 (b) 0 0 (b) 0 (b) 0 2x(b) 0 0 (b) 0 0 0 (c) 0 0 2x(c) 0 (c) 0 0 (c) 0 0 2x(c) 0 (c) 0 (d) 0 0 (d) 0 Operation byte (A) (A) + imm8 byte (A) (A) + (dir) byte (A) (A) + (ear) byte (A) (A) + (eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) byte (A) (AH) + (AL) + (C) (hexadecimal) byte (A) (A) - imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C) byte (A) (AH) - (AL) - (C) (hexadecimal) word (A) (AH) + (AL) word (A) (A) + (ear) word (A) (A) + (eam) word (A) (A) + imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) - imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) + imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) - imm32 LH Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z AH I S T N Z V C RMW - 2 2 2 5 2 3 2+ 4+(a) 2 3 2+ 5+(a) 1 2 2 3 2+ 4+(a) 1 3 2 2 2 5 2 3 2+ 4+(a) 2 3 2+ 5+(a) 1 2 2 3 2+ 4+(a) 1 3 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 6 2+ 7+(a) 5 4 2 6 2+ 7+(a) 5 4 512 APPENDIX B INSTRUCTIONS MB90560 series Table B.8-4 Increment/decrement (byte, word, long-word): 12 instructions Mnemonic INC INC DEC DEC INCW INCW DECW DECW INCL INCL DECL DECL ear eam ear eam ear eam ear eam ear eam ear eam # ~ RG 2 0 2 0 2 0 2 0 4 0 4 0 B 0 2x(b) 0 2x(b) 0 2x(c) 0 2x(c) 0 2x(d) 0 2x(d) Operation byte (ear) (ear) + 1 byte (eam) (eam) + 1 byte (ear) (ear) - 1 byte (eam) (eam) - 1 word (ear) (ear) + 1 word (eam) (eam) + 1 word (ear) (ear) - 1 word (eam) (eam) - 1 long (ear) (ear) + 1 long (eam) (eam) + 1 long (ear) (ear) - 1 long (eam) (eam) - 1 LH AH I S T N Z V C RMW * 2 3 2+ 5+(a) 2 3 2+ 5+(a) 2 3 2+ 5+(a) 2 3 2+ 5+(a) 2 7 2+ 9+(a) 2 7 2+ 9+(a) Table B.8-5 Comparison (byte, word, long-word): 11 instructions Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A,ear A,eam A,#imm8 A A,ear A,eam A,#imm16 A,ear A,eam A,#imm32 # ~ RG 0 1 0 0 0 1 0 0 2 0 0 B 0 0 (b) 0 0 0 (c) 0 0 (d) 0 Operation byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 long (A) - (ear) long (A) - (eam) long (A) - imm32 LH AH I S T N Z V C RMW - 1 1 2 2 2+ 3+(a) 2 2 1 1 2 2 2+ 3+(a) 2 3 6 2 2+ 7+(a) 3 5 MB90560 series APPENDIX B INSTRUCTIONS 513 Table B.8-6 Unsigned multiplication/division (word, long-word): 11 instructions Mnemonic DIVU A # 1 ~ *1 RG 0 B 0 Operation word (AH) / byte (AL) Quotient byte (AL) Remainder byte (AH) word (A) / byte (ear) Quotient byte (A) Remainder byte (ear) word (A) / byte (eam) Quotient byte (A) Remainder byte (ear) long (A) / word (ear) Quotient word (A) Remainder word (ear) long (A) / word (eam) Quotient word (A) Remainder word (eam) byte (AH) * byte (AL) word (A) byte (A) * byte (ear) word (A) byte (A) * byte (eam) word (A) word (AH) * word (AL) Long (A) word (A) * word (ear) Long (A) word (A) * word (eam) Long (A) LH AH I S T N Z V C RMW - DIVU A,ear 2 *2 1 0 - - - - - - - - DIVU A,eam 2+ *3 0 *6 - - - - - - - - DIVUW A,ear 2 *4 1 0 - - - - - - - - DIVUW A,eam 2+ *5 0 *7 - - - - - - - - MULU MULU MULU MULUW MULUW MULUW A A,ear A,eam A A,ear A,eam 1 2 2+ 1 2 2+ *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 0 0 (b) 0 0 (c) - - - - - - - - - - *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 *13 3 for division by zero, 7 for overflow, normally 15 4 for division by zero, 8 for overflow, normally 16 6 + (a) for division by zero, 9 + (a) for overflow, normally 19 + (a) 4 for division by zero, 7 for overflow, normally 22 6 + (a) for division by zero, 8 + (a) for overflow, normally 26 + (a) (b) for division by zero or overflow, normally 2 x (b) (c) for division by zero or overflow, normally 2 x (c) 3 when byte(AH) is zero, 7 otherwise 4 when byte(ear) is zero, 8 otherwise 5 + (a) when byte(eam) is zero, 9 + (a) otherwise 3 when word(AH) is zero, 11 otherwise 4 when word(ear) is zero, 12 otherwise 5 + (a) when word(eam) is zero, 13 + (a) otherwise 514 APPENDIX B INSTRUCTIONS MB90560 series Table B.8-7 Logical 1 (byte, word): 39 instructions Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A,#imm8 A,ear A,eam ear,A eam,A A,#imm8 A,ear A,eam ear,A eam,A A,#imm8 A,ear A,eam ear,A eam,A A ear eam A A,#imm16 A,ear A,eam ear,A eam,A A A,#imm16 A,ear A,eam ear,A eam,A A A,#imm16 A,ear A,eam ear,A eam,A A ear eam # ~ RG 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 B 0 0 (b) 0 2x(b) 0 0 (b) 0 2x(b) 0 0 (b) 0 2x(b) 0 0 2x(b) 0 0 0 (c) 0 2x(c) 0 0 0 (c) 0 2x(c) 0 0 0 (c) 0 2x(c) 0 0 2x(c) Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A) byte (A) not (A) byte (ear) not (ear) byte (eam) not (eam) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A) word (A) not (A) word (ear) not (ear) word (eam) not (eam) LH AH I S T N Z V R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R C RMW * 2 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 2 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 2 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 1 2 2 3 2+ 5+(a) 1 2 3 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 1 2 3 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 1 2 3 2 2 3 2+ 4+(a) 2 3 2+ 5+(a) 1 2 2 3 2+ 5+(a) MB90560 series APPENDIX B INSTRUCTIONS 515 Table A.2-1 Logical 2 (long-word): 6 instructions Mnemonic ANDL ANDL ORL ORL XORL XORL A,ear A,eam A,ear A,eam A,ear A,eam # ~ RG 2 0 2 0 2 0 B 0 (d) 0 (d) 0 (d) Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam) LH AH I S T N Z V R R R R R R C RMW - 2 6 2+ 7+(a) 2 6 2+ 7+(a) 2 6 2+ 7+(a) See Table B.5-1, "Number of execution cycles for each type of addressing," and Table B.5-2, "Compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. Table B.8-9 Sign inversion (byte, word): 6 instructions Mnemonic NEG NEG NEG NEGW NEGW NEGW A ear eam A ear eam # 1 ~ 2 RG 0 2 0 0 2 0 B 0 0 2+(b) 0 0 2+(c) Operation byte (A) 0 - (A) byte (ear) 0 - (ear) byte (eam) 0 - (eam) word (A) 0 - (A) word (ear) 0 - (ear) word (eam) 0 - (eam) LH X AH I S T N Z V C RMW 2 3 2+ 5+(a) 1 2 2 2 2+ 5+(a) Table B.8-10 Normalization (long-word): 1 instruction Mnemonic NRML A,R0 # 2 ~ *1 RG 1 B 0 Operation long (A) Shift to the position where 1 was formerly placed byte (R0) Number of shifts at that time LH AH I S T N Z V C RMW - *1 4 when all accumulators indicate 0, 6 + (R0) otherwise 516 APPENDIX B INSTRUCTIONS MB90560 series Table B.8-11 Shift instructions (byte, word, long-word): 18 instructions Mnemonic RORC A ROLC A RORC RORC ROLC ROLC ASR LSR LSL ear eam ear eam A,RO A,RO A,RO # 2 2 ~ 2 2 RG 0 0 2 0 2 0 1 1 1 0 0 0 1 1 1 B 0 0 0 2x(b) 0 2x(b) 0 0 0 0 0 0 0 0 0 Operation byte (A) Right rotate with carry byte (A) Left rotate with carry byte (ear) Right rotate with carry byte (eam) Right rotate with carry byte (ear) Left rotate with carry byte (eam) Left rotate with carry byte (A) Arithmetic right barrel shift (A,R0) byte (A) Logical right barrel shift (A,R0) byte (A) Logical left barrel shift (A,R0) word (A) Arithmetic right shift (A,1 bit) word (A) Logical right shift (A,1 bit) word (A) Logical left shift (A,1 bit) word (A) Arithmetic right barrel shift (A,R0) word (A) Logical right barrel shift (A,R0) word (A) Logical left barrel shift (A,R0) LH AH I S T N R Z V C RMW - 2 3 2+ 5+(a) 2 3 2+ 5+(a) 2 2 2 1 1 1 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 ASRW A LSRW A/ SHRW A LSLW A/ SHLW A ASRW LSRW LSLW ASRL LSRL LSLL A,R0 A,R0 A,R0 A,R0 A,R0 A,R0 2 2 2 *2 *2 *2 1 1 1 0 0 0 long (A) Arithmetic right barrel shift (A,R0) long (A) Logical right barrel shift (A,R0) long (A) Logical left barrel shift (A,R0) - - - - - - - *1 6 when R0 is zero, 5 + (R0) otherwise *2 6 when R0 is zero, 5 + (R0) otherwise MB90560 series APPENDIX B INSTRUCTIONS 517 Table B.8-12 Branching instructions (1): 31 instructions Mnemonic BZ / BEQ BNZ / BNE BC / BLO BNC / BHS BN BP BV BNV BT BNT BLT BGE BLE BGT BLS BHI BRA JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP CALLP CALLP rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ~ *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 RG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2x(c) (c) 2x(c) 2x(c) *2 2x(c) Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Unconditional branching word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) word (PC) (ear), (PCB) (ear+2) word (PC) (eam), (PCB) (eam+2) word (PC) ad24 0-15, (PCB) ad24 16-23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0-15, (PCB) (ear)16-23 word (PC) (eam) 0-15, (PCB) (eam)16-23 word (PC) addr0-15, (PCB) addr16-23 LH AH I S T N Z V C RMW - @A 1 2 addr16 3 3 @ear 2 3 @eam 2+ 4+(a) @ear *1 2 5 @eam *1 2+ 6+(a) addr24 4 4 @ear *2 2 6 @eam *2 2+ 7+(a) addr16 *3 3 6 #vct4 *3 1 7 @ear *4 2 10 @eam *4 2+ 11+(a) addr24 *5 4 10 *1 4 when branching occurs, 3 otherwise *2 3 x (c) + (b) *3 Reads a branch destination address (word). *4 Write: Saves to stack (word), Read: Reads a branch destination address (word). *5 Saves to stack (word). *6 Write: Saves to stack (long-word), Read: Reads a branch destination address (long-word). *7 Saves to stack (long-word). 518 APPENDIX B INSTRUCTIONS MB90560 series Table B.8-13 Branch instructions (2): 19 instructions Mnemonic CBNE A,#imm8,rel CWBNE A,#imm16,rel CBNE CBNE CWBNE CWBNE DBNZ DBNZ DWBNZ DWBNZ INT INT INTP INT9 RETI LINK # 3 4 ~ *1 *1 *2 *3 *4 *3 *5 *6 *5 *6 20 16 17 20 11 6 RG 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 B 0 0 0 (b) 0 (c) 0 2x(b) 0 2x(c) 8x(c) 6x(c) 6x(c) 8x(c) *7 (c) Operation Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16 Branch when byte (ear)=(ear)-1, (ear) 0 Branch when byte (eam)=(eam)-1, (eam) 0 Branch when word (ear)=(ear)-1, (ear) 0 Branch when word (eam)=(eam)-1, (eam) 0 Software interrupt Software interrupt Software interrupt Software interrupt Recovery from interrupt At the entrance of function, save old frame pointers into a stack, set up new frame pointers, reserve area for local pointers. At the exit of function, recover the old frame pointers from the stack. Recover from the subroutine. Recover from the subroutine. LH AH I R R R R S S S S S T N Z V C RMW - ear,#imm8,rel 4 eam,#imm8,rel 4+ ear,#imm16,rel 5 eam,#imm16,rel 5+ ear,rel eam,rel ear,rel eam,rel #vct8 addr16 addr24 3 3+ 3 3+ 2 3 4 1 1 2 #imm8 UNLINK 1 5 0 (c) - - - - - - - - - - RET RETP *1 *2 1 1 4 6 0 0 (c) (d) - - - - - - - - - - *1 5 when branching occurs, 4 otherwise *2 13 when branching occurs, 12 otherwise *3 7 + (a) when branching occurs, 6 + (a) otherwise *4 8 when branching occurs, 7 otherwise *5 7 when branching occurs, 6 otherwise *6 8 + (a) when branching occurs, 7 + (a) otherwise *7 Returns from stack (word) *8 Returns from stack (long-word) *9 Do not use the RWj + addressing mode for a CBNE/CWBNE instruction. MB90560 series APPENDIX B INSTRUCTIONS 519 Table B.8-14 Other control instructions (byte, word, long-word): 28 instructions Mnemonic PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR MOV MOV MOVEA MOVEA MOVEA MOVEA ADDSP ADDSP MOV MOV NOP ADB DTB PCB SPB NCC CMR A AH PS rlst A AH PS rlst @A CCR,#imm8 CCR,#imm8 RP,#imm8 ILM,#imm8 RWi,ear RWi,eam A,ear A,eam #imm8 #imm16 A,brgl brg2,A # 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2 3 2+(a) 1 1+(a) 3 3 *1 1 1 1 1 1 1 1 1 RG 0 0 0 +& 0 0 0 +& 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 B (c) (c) (c) *4 (c) (c) (c) *4 6x(c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Operation word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) - 2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) + 2 word (AH) ((SP)), (SP) (SP) + 2 word (PS) ((SP)), (SP) (SP) + 2 (rlst) ((SP)), (SP) (SP) Context switching instruction byte (CCR) (CCR) and imm8 byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word (A) ear word (A) eam word (SP) ext(imm8) word (SP) imm16 byte (A) (brg1) byte (brg2) (A) No operation Prefix code for AD space access Prefix code for DT space access Prefix code for PC space access Prefix code for SP space access Prefix code for flag unchange setting Prefix for common register banks LH AH Z I S T N Z V C RMW - *1 PCB,ADB,SSB,USB ------------1 DTB,DPR --------------------------2 *2 7 + 3 x (pop count) + 2 x (last register number popped), 7 when RLST = 0 (no transfer register) *3 29 + 3 x (push count) - 3 x (last register number pushed), 8 when RLST = 0 (no transfer register) *4 (Pop count) x (c) or (push count) x (c) *5 (Pop count) or (push count) 520 APPENDIX B INSTRUCTIONS MB90560 series Table B.8-15 Bit operation instructions: 21 instructions Mnemonic MOVB MOVB MOVB MOVB MOVB MOVB SETB SETB SETB CLRB CLRB CLRB BBC BBC BBC BBS BBS BBS SBBS WBTS WBTC A,dir:bp A,addr16:bp A,io:bp dir:bp,A addr16:bp,A io:bp,A dir:bp addr16:bp io:bp dir:bp addr16:bp io:bp dir:bp,rel addr16:bp,rel io:bp,rel dir:bp,rel addr16:bp,rel io:bp,rel addr16:bp,rel io:bp io:bp # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4 RG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B (b) (b) (b) 2x(b) 2x(b) 2x(b) 2x(b) 2x(b) 2x(b) 2x(b) 2x(b) 2x(b) (b) (b) (b) (b) (b) (b) 2x(b) *5 *5 Operation byte (A) ( dir:bp )b byte (A) ( addr16:bp )b byte (A) ( io:bp )b bit ( dir:bp )b (A) bit ( addr16:bp )b (A) bit ( io:bp )b (A) bit ( dir:bp )b 1 bit ( addr16:bp )b 1 bit ( io:bp )b 1 bit ( dir:bp )b 0 bit ( addr16:bp )b 0 bit ( io:bp )b 0 Branch when ( dir:bp )b = 0 Branch when ( addr16:bp )b = 0 Branch when ( io:bp)b = 0 Branch when ( dir:bp )b = 1 Branch when ( addr16:bp )b = 1 Branch when ( io:bp)b = 1 Branch when (addr16:bp) b = 1, bit = 1 Wait until (io:bp) b = 1 Wait until (io:bp) b = 0 LH AH I S T Z Z Z N Z V C RMW - *1 8 when branching occurs, 7 otherwise *2 7 when branching occurs, 6 otherwise *3 10 when conditions are met, 9 otherwise *4 Undefined number of cycles *5 Until conditions are met Table B.8-16 Accumulator operation instructions (byte, word): 6 instructions Mnemonic SWAP SWAPW / XCHW A,T EXT EXTW ZEXT ZEXTW # 1 1 1 1 1 1 ~ 3 2 1 2 1 1 RG 0 0 0 0 0 0 B 0 0 0 0 0 0 Operation byte (A)0-7 (A)8-15 word (AH) (AL) byte signed extension word signed extension byte zero extension word zero extension LH AH X Z X Z I S T N R R Z V C RMW - MB90560 series APPENDIX B INSTRUCTIONS 521 Table B.8-17 String instructions: 10 instructions Mnemonic MOVS / MOVSI MOVSD SCEQ / SCEQI SCEQD FILS / FILSI MOVSW / MOVSWI MOVSWD SCWEQ / SCWEQI SCWEQD FILSW / FILSWI # 2 2 2 2 2 2 2 2 2 2 ~ *2 *2 *1 *1 6m+6 *2 *2 *1 *1 6m+6 RG +& +& +& +& +& +) +) +) +) +) B *3 *3 *4 *4 *3 *6 *6 *7 *7 *6 Operation byte transfer @AH+ @AL+, counter = RW0 byte transfer @AH- @AL-, counter = RW0 byte search @AH+ AL, counter = RW0 byte search @AH- AL, counter = RW0 byte fill @AH+ AL, counter = RW0 word transfer @AH+ @AL+, counter = RW0 word transfer @AH- @AL-, counter = RW0 word search @AH+ AL, counter = RW0 word search @AH- AL, counter = RW0 word fill @AH+ AL, counter = RW0 LH AH I S T N Z V C RMW - *1 5 when RW0 is zero, 4 + 7 x (RW0) when counter limit reached, 7n + 5 for a match *2 5 when RW0 is zero, 4 + 8 x (RW0) otherwise *3 (b) x (RW0) + (b) x (RW0). When source and destination access different areas, calculate item (b) separately. *4 (b) x n *5 2 x (RW0) *6 (c) x (RW0) + (c) x (RW0). When source and destination access different areas, calculate item (c) separately. *7 (c) x n *8 2 x (RW0) Note: m: RW0 value (counter value) n: Loop count 522 APPENDIX B INSTRUCTIONS MB90560 series B.9 Instruction Maps An F2MC-16L instruction code consists of one or two bytes. Accordingly an instruction map consists of several one-byte or two-byte pages. Tables B.9-2 to B.9-20 show F2MC-16L instruction maps. s Configuration of instruction maps Basic page map : 1st byte Bit operation instructions Character string operation instructions 2-byte instructions ea instructions x 9 : 2nd byte Figure B.9-1 Configuration of instruction maps When the instruction code is a 1-byte instruction (NOP instruction, etc.), the instruction code is described on the basic page map. When the instruction code is a 2-byte instruction (MOVS, etc.), see the basic page map and check the name of the map where the second byte of the instruction code to be referenced next is described. MB90560 series APPENDIX B INSTRUCTIONS 523 Figure B.9-2 shows the relationship between the actual instruction code and instruction maps. May not exist for some instructions Length differs according to the instruction *** [Basic page map] XY Instruction code First byte Second byte operand operand +Z [Extension page map] Note UV +W Note: Extended page maps are provided for bit manipulation instructions, character string manipulation instructions, two-byte instructions, and "ea" instructions; multiple-extended-page maps exist for each type of instruction. Figure B.9-2 Relationship between actual instruction codes and instruction maps Table B.9-1 lists instruction code examples. Table B.9-1 Example instruction codes Instruction NOP AND A,#8 MOV A,ADB @RW2+d8,#8,rel 1st byte (from the basic page map) 00 + 0 = 00 30 + 4 = 34 60 + F = 6F 70 + 0 = 70 2nd byte (from the extended page map) 00 + 0 = 00 F0 + 2 = F2 524 APPENDIX B INSTRUCTIONS MB90560 series MB90560 series 20 ADD MOV MOV BRA A, io rel JMP @A JMP instructions (3) instructions (2) instructions (1) 00 ea MOV A, Ri Ri, A Ri, #8 A, Ri MOV MOV MOVX ea ea ea instructions (4) 10 MOVX A,@RWi+d8 30 40 50 60 70 80 90 A0 B0 C0 D0 MOVN A, #4 E0 CALLV #4 F0 +0 A, dir A, dir MOV MOV dir, A MOV A A, #8 SUBC A SUB A, dir A, #8 NOP CMR ADD +1 INT9 NCC SUB +2 ADDDC SUBDC ADDC A A +3 ea instructions (5) NEG A +4 ea instructions (6) PCB JCTX @A EXT +5 ea instructions (7) DTB ZEXT +6 RET instructions (8) ADB ea ea #vct8 INT addr16 instructions (9) SWAP addr16 JMPP addr24 CALL addr16 CALLP addr24 RETP +7 INT MOVW A, RWi MOVW RWi, A SPB +8 MOVW MOVW RWi, #16 @RWi+dB MOVW @RWi+dB, A Table B.9-2 Basic page map +9 +A +B +C +D ADDSP #8 LINK ADDL imm#8 A, #32 UNLINK SUBL A, #32 MOV MOV RP, #8 ILM, #8 NEGW CMPL A A, #32 LSLW EXTW A ZEXTW +E ASRW SWAPW A +F LSRW APPENDIX B INSTRUCTIONS A ADDSP #16 A, #8 CMP CMP MOVX A, #8 A A, #8 MOV AND AND CCR, #8 A, #8 dir, #8 OR OR MOVX A, #8 CCR, #8 A, dir XOR DIVU MOVW A, #8 A A, SP MOVW MULU NOT A A SP, A ADDW ADDW MOVW A, #16 A A, dir MOVW SUBW SUBW A, #16 A dir, A MOVW CBNE A, CWBNE A, #16, rel #8, rel A, #16 MOVL CMPW CMPW A, #16 A A, #32 PUSHW ANDW ANDW A, #16 A A ORW ORW PUSHW AH A, #16 A PUSHW XORW XORW A, #16 A PS PUSHW NOTW MULUW rlst A A MOVEA RWi, ea MOV INTP Ri, ea addr24 MOVW RETI RWi, ea Bit MOV operation ea, Ri instructions MOVW ea, RWi String XCH operation Ri, ea instructions XCRW Two-byte RWi, ea instructions io, A MOV A, addr16 MOV addr 16, A MOV io, #8 MOVX A, io MOVW io, #16 MOVX A, addr16 MOVW A, io MOVW io, A MOVW A, addr16 MOVW addr16, A POPW A POPW AH POPW PS POPW rlst BZ /BEQ rel BNZ/BNE rel BC /BLO rel BNC/BHS rel BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel 525 526 20 CLRB io:bp io:bp SETB BBC io:bp, rel BBS io:bp, rel WBTS io:bp 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 WBTC io:bp F0 MOVB addr16: bp, A CLRB dir:bp CLRB addr16:bp SETB dir:bp SETB addr16:bp BBC BBC dir:bp,rel ad16:bp, rel BBS dir:bp, rel BBS ad 16:bp, rel SBBS addr16:bp 00 10 +0 MOVB A, io:bp MOVB io:bp, A +1 APPENDIX B INSTRUCTIONS +2 +3 +4 +5 +6 +7 +8 MOVB A, dir:bp MOVB A, addr16:bp MOVB dir: bp,A +9 +A +B +C +D +E Table B.9-3 Bit operation instruction map (1st byte = 6CH) +F MB90560 series MB90560 series 20 MOVSWD SCEQI PCB DTB DTB ADB SPB SPB SPB ADB ADB DTB DTB ADB SPB DTB ADB SPB SCEQD PCB SCWEQI PCB SCWEQD PCB FILSI PCB 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 FILSWI PCB DTB ADB SPB F0 00 10 +0 MOVSI PCB, PCB MOVSD MOVSWI +1 PCB, DTB +2 PCB, ADB +3 PCB, SPB +4 DTB, PCB +5 DTB, DTB +6 DTB, ADB +7 DTB, SPB +8 ADB, PCB +9 ADB, DTB +A ADB, ADB +B ADB, SPB +C SPB, PCB +D SPB, DTB +E SPB, ADB Table B.9-4 Character string operation instruction map (1st byte = 6EH) APPENDIX B INSTRUCTIONS +F SPB, SPB 527 528 20 MOV A, @RL0+d8 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 MOV A, @RL1+d8 MOV A, @RL2+d8 MOVW MOVW @RL0+d8, A A, @RL0+d8 A MULW A MOVW @RL1+d8, A A MOVW A, @RL1+d8 DIVU MUL 00 10 +0 MOVX MOV A, @RL0 +d8 @RL0+d8, A +1 APPENDIX B INSTRUCTIONS MOVW A, @RL2+d8 MOVW A, @RL3+d8 +2 MOVX MOV A, @RL1+d8 @RL1+d8, A +3 +4 MOVX MOV A, @RL2+d8 @RL2+d8, A +5 +6 MOVX MOV MOV A, @RL3+d8 @RL3+d8, A A, @RL3+d8 +7 MOV A, DTB MOV A, ADB MOV A, SSB MOV A, USB MOV A. DPR MOV A. @A MOV A, PCB ROLC A MOV DTB, A MOV ADB, A MOV SSB, A MOV USB, A MOV DPR, A MOV @AL, AH MOVX A, @A RORC A +8 +9 +A +B Table B.9-5 2-byte instruction map (1st byte = 6FH) +C LSLW LSLL LSL +D +E +F A, R0 MOVW A, @A ASRW A, R0 LSRW A, R0 A, R0 MOVW @AL, AH ASRL A, R0 LSRL A, R0 MOVW A, R0 @RL2+d8, A NRML A, R0 ASR MOVW A, R0 @RL3+d8, A LSR A, R0 MB90560 series MB90560 series 20 SUBL CMPL CMPL A, A, RL0 @RW0+d8 ANDL CMPL A, A, RL0 @RW1+d8 ANDL CMPL A, A, RL1 @RW2+d8 ANDL CMPL A, A, RL1 @RW3+d8 ANDL CMPL A, A, RL2 @RW4+d8 ANDL CMPL A, A, RL2 @RW5+d8 ANDL CMPL A, A, RL3 @RW6+d8 ANDL CMPL A, A, RL2 @RW5+d8 ORL ANDL A, A, RL3 @RW6+d8 ORL ANDL A, A, RL3 @RW7+d8 ORL ANDL A, A, RL2 @RW4+d8 ORL ANDL A, A, RL1 @RW3+d8 ORL ANDL A, A, RL1 @RW2+d8 ORL ANDL A, A, RL1 @RW2+d8 XORL ORL A, A, RL1 @RW3+d8 XORL ORL A, A, RL2 @RW4+d8 XORL ORL A, A, RL2 @RW5+d8 XORL ORL A, A, RL3 @RW6+d8 XORL ORL A, A, RL3 @RW7+d8 XORL ORL A, A, RL0 @RW1+d8 ORL ANDL A, A, RL0 @RW1+d8 XORL ORL A, A, RL0 @RW0+d8 ORL ANDL A, A, RL0 @RW0+d8 XORL ORL A, @RW0+d8 XORL A, @RW1+d8 XORL A, @RW2+d8 XORL A, @RW3+d8 XORL A, @RW4+d8 XORL A, @RW5+d8 XORL A, @RW6+d8 XORL A, @RW7+d8 XORL A, A, RL0 CMPL A, RL0 CMPL A, RL1 CMPL A, RL1 CMPL A, RL2 CMPL A, RL2 CMPL A, RL3 CMPL ANDL @RW0+d8 SUBL A, @RW1+d8 SUBL A, @RW2+d8 SUBL A, @RW3+d8 SUBL A, @RW4+d8 SUBL A, @RW5+d8 SUBL A, @RW6+d8 SUBL A, @RW7+d8 SUBL A, A, RL3 CMPL A, RL3 @RW7+d8 CMPL A, ANDL SUBL A, ANDL A, ORL ORL A, XORL A, XORL 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 XORL ORL ORL A, XORL A, CMPL ANDL ANDL A, CMPL A, A, @RW1 @RW1+d16 A, @RW1 @RW1+d16 A, @RW1 @RW1+d16 A, @RW1 @RW1+d16 XORL ORL XORL A, ORL A, CMPL ANDL ANDL A, CMPL A, A, @RW2 @RW2+d16 A, @RW2 @RW2+d16 A, @RW2 @RW2+d16 A, @RW2 @RW2+d16 ORL XORL XORL A, ANDL A, ORL A, CMPL ANDL CMPL A, A, @RW3 @RW3+d16 A, @RW3 @RW3+d16 A, @RW3 @RW3+d16 A, @RW3 @RW3+d16 ORL XORL XORL A, ANDL A, ORL A, CMPL CMPL A, ANDL A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 ORL XORL ANDL A, ORL A, XORL A, CMPL CMPL A, ANDL Prohibit A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 ORL XORL ORL A, XORL A, CMPL CMPL A, ANDL ANDL A, Prohibit @PC+d16 A, @RW2+ @PC+d16 A, @RW2+ @PC+d16 A, @RW2+ @PC+d16 A, @RW2+ XORL ORL ORL A, XORL A, CMPL CMPL A, ANDL ANDL A, Prohibit A, @RW3+ addr16 A, @RW3+ addr16 A, @RW3+ addr16 A, @RW3+ addr16 CWBNE RW0, #16, rel CWBNE RW1, #16, rel CWBNE RW2, #16, rel CWBNE RW3, #16, rel CWBNE RW4, #16, rel CWBNE RW5, #16, rel CWBNE RW6, #16, rel CWBNE RW7, #16, rel CWBNE @ RW0, #16, rel CWBNE @ RW1, #16, rel CWBNE @ RW2, #16, rel CWBNE @ RW3, #16, rel Prohibit CBNE R0, #8, rel CBNE R1, #8, rel CBNE R2, #8, rel CBNE R3, #8, rel CBNE R4, #8, rel CBNE R5, #8, rel CBNE R6, #8, rel CBNE R7, #8, rel CBNE @RW0, #8, rel CBNE @RW1, #8, rel CBNE @RW2, #8, rel CBNE @RW3, #8, rel Prohibit Prohibit Prohibit Prohibit A, @RW3+ addr16 CWBNE @RW0+d8, #16, rel CWBNE @RW1+d8, #16, rel CWBNE @RW2+d8, #16, rel CWBNE @RW3+d8, #16, rel CWBNE @RW4+d8, #16, rel CWBNE @RW5+d8, #16, rel CWBNE @RW6+d8, #16, rel CWBNE @RW7+d8, #16, rel CWBNE @RW0+d16, #16, rel CWBNE @RW1, d16, #16, rel CWBNE @RW2+d16, #16, rel CWBNE @RW3+d16, #16, rel CWBNE @RW0+RW7 ,#16, rel CWBNE @RW1+RW7 ,#16, rel CWBNE @PC+d16, #16, rel CWBNE addr16, #16, rel 00 10 ADDL ADDL A, +0 A, RL0 ADDL @RW0+d8 A, RL0 SUBL ADDL A, +1 A, RL0 ADDL @RW1+d8 A, RL0 SUBL ADDL A, +2 A, RL1 ADDL @RW2+d8 A, RL1 SUBL ADDL A, +3 A, RL1 ADDL @RW3+d8 A, RL1 SUBL ADDL A, +4 A, RL2 ADDL @RW4+d8 A, RL2 SUBL ADDL A, +5 A, RL2 ADDL @RW5+d8 A, RL2 SUBL ADDL A, +6 A, RL3 ADDL @RW6+d8 A,RL3 ADDL A, SUBL +7 A, RL3 ADDL @RW7+d8 A, RL3 SUBL ADDL A, +8 A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 SUBL SUBL A, ADDL A, ADDL +9 A, @RW1 @RW1+d16 A, @RW1 @RW1+d16 SUBL SUBL A, ADDL ADDL A, +A A, @RW2 @RW2+d16 A, @RW2 @RW2+d16 SUBL SUBL A, ADDL ADDL A, Table B.9-6 ea instruction map (1) (1st byte = 70H) +B A, @RW3 @RW3+d16 A, @RW3 @RW3+d16 ADDL ADDL A, SUBL SUBL A, +C A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 ADDL ADDL A, SUBL SUBL A, +D A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 ADDL A, SUBL SUBL A, ADDL +E A, @RW2+ @PC+d16 A, @RW2+ @PC+d16 ADDL A, SUBL SUBL A, ADDL +F APPENDIX B INSTRUCTIONS A, @RW3+ addr16 CBNE @RW0+d8, #8, rel CBNE @RW1+d8, #8, rel CBNE @RW2+d8, #8, rel CBNE @RW3+d8, #8, rel CBNE @RW4+d8, #8, rel CBNE @RW5+d8, #8, rel CBNE @RW6+d8, #8, rel CBNE @RW7+d8, #8, rel CBNE @RW0+d16, #8, rel CBNE @RW1+d16, #8, rel CBNE* @RW2+d16, #8, rel CBNE @RW3+d16, #8, rel CBNE @RW0+RW7 , #8, rel CBNE @RW1+RW7 #8, rel CBNE @PC+d16, #8, rel CBNE addr16, #8, rel 529 530 20 CALLP @@RW0+d8 INCL @RW0+d8 DECL @RW0+d8 MOVL A, @RW0+d8 MOVL @R W0+d8, A MOVL @R W1+d8, A MOVL @R W2+d8, A MOVL @R W3+d8, A MOVL @R W4+d8, A MOVL @R W5+d8, A MOVL @R W6+d8, A MOVL @R W7+d8, A MOV R2, #8 MOV R3, #8 MOV R4, #8 MOV R5, #8 MOV R6, #8 MOV R7, #8 MOV R1, #8 MOVL A, @RW1+d8 MOVL A, @RW2+d8 MOVL A, @RW3+d8 MOVL A, @RW4+d8 MOVL A, @RW5+d8 MOVL A, @RW6+d8 MOVL A, @RW7+d8 MOVL RL3, A MOVL RL3, A MOVL RL2, A MOVL RL2, A MOVL RL1, A MOVL RL1, A MOVL RL0, A DECL @RW1+d8 DECL @RW2+d8 DECL @RW3+d8 DECL @RW4+d8 DECL @RW5+d8 DECL @RW6+d8 DECL @RW7+d8 DECL @RW0+d16 DECL @RW1+d16 DECL @RW2+d16 DECL @RW3+d16 DECL @RW0+RW7 DECL @RW1+RW7 DECL @PC+d16 DECL addr16 MOVL MOVL A, A, @RW1 @RW1+d16 MOVL MOVL A, A, @RW2 @RW2+d16 MOVL MOVL A, A,@ RW3 @RW3+d16 MOVL A, RL3 MOVL A, RL3 MOVL A, RL2 MOVL A, RL2 MOVL A, RL1 MOVL A, RL1 MOVL A, RL0 INCL @RW1+d8 INCL @RW2+d8 INCL @RW3+d8 INCL @RW4+d8 INCL @RW5+d8 INCL @RW6+d8 INCL @RW7+d8 INCL @RW0+d16 INCL @RW1+d16 INCL @RW2+d16 INCL @RW3+d16 INCL @RW0+RW7 INCL @RW1+RW7 INCL @PC+d16 INCL addr16 DECL @RW3+ DECL @RW2+ DECL @RW1+ DECL @RW0+ DECL @RW3 DECL @RW2 DECL @RW1 DECL @RW0 DECL RL3 DECL RL3 DECL RL2 DECL RL2 DECL RL1 DECL RL1 DECL RL0 CALLP @@RW1+d8 CALLP @@RW2+d8 CALLP @@RW3+d8 CALLP @@RW4+d8 CALLP @@RW5+d8 CALLP @@RW6+d8 CALLP @@RW7+d8 INCL @RW0 INCL @RW1 INCL @RW2 INCL @RW3 INCL @RW0+ INCL @RW1+ INCL @RW2+ INCL @RW3+ INCL RL3 INCL RL3 INCL RL2 INCL RL2 INCL RL1 INCL RL1 INCL RL0 INCL RL0 DECL RL0 MOVL A, RL0 MOVL RL0, A MOV R0, #8 30 40 50 60 70 80 90 A0 B0 C0 D0 MOV @R W0+d8, #8 MOV @R W1+d8, #8 MOV @R W2+d8, #8 MOV @R W3+d8, #8 MOV @R W4+d8, #8 MOV @R W5+d8, #8 MOV @R W6+d8, #8 MOV @R W7+d8, #8 MOV MOV @R @RW0, #8 W0+d16, #8 MOVL @RW1, A MOVL @RW2, A MOVL @RW3, A MOVL @R W1+d16, A MOVL @R W2+d16, A MOVL @R W3+d16, A MOV MOV @R @RW1, #8 W1+d16, #8 MOV MOV @R @RW2, #8 W2+d16, #8 MOV MOV @R @RW3, #8 W3+d16, #8 E0 MOVEA A, RW0 MOVEA A, RW1 MOVEA A, RW2 MOVEA A, RW3 MOVEA A, RW4 MOVEA A, RW5 MOVEA A, RW6 MOVEA A, RW7 F0 MOVEA A, @RW0+d8 MOVEA A, @RW1+d8 MOVEA A, @RW2+d8 MOVEA A, @RW3+d8 MOVEA A, @RW4+d8 MOVEA A, @RW5+d8 MOVEA A, @RW6+d8 MOVEA A, @RW7+d8 MOVEA MOVEA A, A, @RW0 @RW0+d16 MOVEA A, @RW1 MOVEA A, @RW2 MOVEA A, @RW3 MOVEA A, @RW1+d16 MOVEA A, @RW2+d16 MOVEA A, @RW3+d16 MOVL MOVL MOVL A, MOVL @R A, @RW0 @RW0+d16 @RW0, A W0+d16, A CALLP @ @RW1+d16 CALLP @ @RW2+d16 CALLP @ @RW3+d16 00 10 +0 JMPP @RL0 JMPP @@RW0+d8 CALLP @RL0 +1 JMPP @RL0 JMPP @@RW1+d8 CALLP @RL0 APPENDIX B INSTRUCTIONS MOVL MOVL A, A, @RW2+ @PC+d16 MOVL MOVL A, A, @RW3+ addr16 MOVL MOV MOVL @P MOV @P @RW2+, A C+d16, A @RW2+, #8 C+d16, #8 MOVL MOVL @RW3+, A addr16, A MOV MOV @RW3+, #8 addr16, #8 +2 JMPP @RL1 JMPP @@RW2+d8 CALLP @RL1 +3 JMPP @RL1 JMPP @@RW3+d8 CALLP @RL1 +4 JMPP @RL2 JMPP @@RW4+d8 CALLP @RL2 +5 JMPP @RL2 JMPP @@RW5+d8 CALLP @RL2 +6 JMPP @RL3 JMPP @@RW6+d8 CALLP @RL3 +7 JMPP @RL3 JMPP @@RW7+d8 CALLP @RL3 +8 JMPP @@RW0 JMPP @ @RW0+d16 CALLP CALLP @ @@RW0 @RW0+d16 +9 JMPP @@RW1 JMPP @ @RW1+d16 CALLP @@RW1 +A JMPP @@RW2 JMPP @ @RW2+d16 CALLP @@RW2 +B JMPP @@RW3 JMPP @ @RW3+d16 CALLP @@RW3 Table B.9-7 ea instruction map (2) (1st byte = 71H) +C JMPP @@RW0+ JMPP @ CALLP CALLP @ @RW0+RW7 @@RW0+ @RW0+RW7 MOVL MOVL MOVEA MOVL A, MOVL @R MOV MOV @R MOVEA A, A, @RW0+ @RW0+RW7 @RW0+, A W0+RW7, A @RW0+, #8 W0+RW7, #8 A, @RW0+ @RW0+RW7 MOVL MOVL MOVEA MOVL A, MOVL @R MOV MOV @R MOVEA A, A, @RW1+ @RW1+RW7 @RW1+, A W1+RW7, A @RW1+, #8 W1+RW7, #8 A, @RW1+ @RW1+RW7 MOVEA MOVEA A, A, @RW2+ @PC+d16 MOVEA MOVEA A, A, @RW3+ addr16 +D JMPP @@RW1+ JMPP @ CALLP CALLP @ @RW1+RW7 @@RW1+ @RW1+RW7 +E JMPP @@RW2+ JMPP @@PC+d16 CALLP CALLP @@RW2+ @@PC+d16 +F JMPP @@RW3+ JMPP @addr16 CALLP CALLP @@RW3+ @addr16 MB90560 series MB90560 series 20 RORC @RW0+d8 INC @RW0+d8 DEC @RW0+d8 MOV A, @RW0+d8 MOV @R W0+d8, A MOV @R W1+d8, A MOV @R W2+d8, A MOV @R W3+d8, A MOV @R W4+d8, A MOV @R W5+d8, A MOV @R W6+d8, A MOV R7, A MOV @R W7+d8, A MOVX A, R1 MOVX A, R2 MOVX A, R3 MOVX A, R4 MOVX A, R5 MOVX A, R6 MOVX A, R7 MOVX A, @RW0 MOV @RW1, A MOV @RW2, A MOV MOV A, A, @RW3 @RW3+d16 MOV @RW3, A MOV @R W1+d16, A MOV @R W2+d16, A MOV @R W3+d16, A MOVX A, @RW1 MOVX A, @RW2 MOVX A, @RW3 MOV A, @RW1+d8 MOV A, @RW2+d8 MOV A, @RW3+d8 MOV A, @RW4+d8 MOV A, @RW5+d8 MOV A, @RW6+d8 MOV A, @RW7+d8 MOV R5, A MOV R6, A MOV R4, A MOV R3, A MOV R2, A MOV R1, A DEC @RW1+d8 DEC @RW2+d8 DEC @RW3+d8 DEC @RW4+d8 DEC @RW5+d8 DEC @RW6+d8 DEC @RW7+d8 DEC @RW0+d16 DEC @RW1+d16 DEC @RW2+d16 DEC @RW3+d16 DEC @RW0+RW7 DEC @RW1+RW7 DEC @PC+d16 DEC addr16 MOV A, R7 MOV A, R6 MOV A, R5 MOV A, R4 MOV A, R3 MOV A, R2 MOV A, R1 INC @RW1+d8 INC @RW2+d8 INC @RW3+d8 INC @RW4+d8 INC @RW5+d8 INC @RW6+d8 INC @RW7+d8 INC @RW0+d16 INC @RW1+d16 INC @RW2+d16 INC @RW3+d16 INC @RW0+RW7 INC @RW1+RW7 INC @PC+d16 INC addr16 DEC @RW2+ DEC @RW3+ DEC @RW1+ DEC @RW0+ DEC @RW3 DEC @RW2 DEC @RW1 DEC @RW0 DEC R7 DEC R6 DEC R5 DEC R4 DEC R3 DEC R2 DEC R1 RORC @RW1+d8 RORC @RW2+d8 RORC @RW3+d8 RORC @RW4+d8 RORC @RW5+d8 RORC @RW6+d8 RORC @RW7+d8 RORC @RW0+d16 RORC @RW1+d16 RORC @RW2+d16 RORC @RW3+d16 RORC @RW0+RW7 RORC @RW1+RW7 RORC @PC+d16 RORC addr16 INC @RW3+ INC @RW2+ INC @RW1+ INC @RW0+ INC @RW3 INC @RW2 INC @RW1 INC @RW0 INC R7 INC R6 INC R5 INC R4 INC R3 INC R2 INC R1 INC R0 DEC R0 MOV A, R0 MOV R0, A MOVX A, R0 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 XCH MOVX A, A, R0 @RW0+d8 XCH MOVX A, A, R1 @RW1+d8 XCH MOVX A, A, R2 @RW2+d8 XCH MOVX A, A, R3 @RW3+d8 XCH MOVX A, A, R4 @RW4+d8 XCH MOVX A, A, R5 @RW5+d8 XCH MOVX A, A, R6 @RW6+d8 XCH MOVX A, A, R7 @RW7+d8 F0 XCH A, @RW0+d8 XCH A, @RW1+d8 XCH A, @RW2+d8 XCH A, @RW3+d8 XCH A, @RW4+d8 XCH A, @RW5+d8 XCH A, @RW6+d8 XCH A, @RW7+d8 XCH MOVX A, XCH A, A, @RW0 @RW0+d16 @RW0+d16 XCH MOVX A, A, @RW1 @RW1+d16 XCH MOVX A, A, @RW2 @RW2+d16 XCH MOVX A, A, @RW3 @RW3+d16 XCH A, @RW1+d16 XCH A, @RW2+d16 XCH A, @RW3+d16 MOV MOV MOVX XCH MOV A, MOV @R MOVX A, XCH A, A, @RW0+ @RW0+RW7 @RW0+, A W0+RW7, A A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 MOV MOV MOVX XCH MOV A, MOV @R MOVX A, XCH A, A, @RW1+ @RW1+RW7 @RW1+, A W1+RW7, A A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 MOV MOV A, A, @RW2+ @PC+d16 MOV MOV A, A, @RW3+ addr16 MOV MOV @P @RW2+, A C+d16, A MOV MOV @RW3+, A addr16, A MOVX A, @RW2+ MOVX A, @RW3+ MOVX A, @PC+d16 MOVX A, addr16 XCH XCH A, A, @RW2+ @PC+d16 XCH XCH A, A, @RW3+ addr16 MOV MOV MOV A, MOV @R A, @RW0 @RW0+d16 @RW0, A W0+d16, A MOV MOV A, A, @RW1 @RW1+d16 MOV MOV A, A, @RW2 @RW2+d16 00 10 +0 ROLC R0 ROLC @RW0+d8 RORC R0 +1 ROLC R1 ROLC @RW1+d8 RORC R1 +2 ROLC R2 ROLC @RW2+d8 RORC R2 +3 ROLC R3 ROLC @RW3+d8 RORC R3 +4 ROLC R4 ROLC @RW4+d8 RORC R4 +5 ROLC R5 ROLC @RW5+d8 RORC R5 +6 ROLC R6 ROLC @RW6+d8 RORC R6 +7 ROLC R7 ROLC @RW7+d8 RORC R7 +8 ROLC @RW0 ROLC @RW0+d16 RORC @RW0 +9 ROLC @RW1 ROLC @RW1+d16 RORC @RW1 +A ROLC @RW2 ROLC @RW2+d16 RORC @RW2 +B ROLC @RW3 ROLC @RW3+d16 RORC @RW3 +C ROLC @RW0+ ROLC RORC @RW0+RW7 @RW0+ Table B.9-8 ea instruction map (3) (1st byte = 72H) +D ROLC @RW1+ ROLC RORC @RW1+RW7 @RW1+ +E ROLC @RW2+ ROLC @PC+d16 RORC @RW2+ APPENDIX B INSTRUCTIONS +F ROLC @RW3+ ROLC addr16 RORC @RW3+ 531 532 20 CALL @@RW0+d8 INCW @RW0+d8 DECW @RW0+d8 DECW @RW1+d8 DECW @RW2+d8 DECW @RW3+d8 DECW @RW4+d8 DECW @RW5+d8 DECW @RW6+d8 DECW @RW7+d8 DECW @RW0+d16 DECW @RW1+d16 DECW @RW2+d16 DECW @RW3+d16 DECW @RW0+RW7 DECW @RW1+RW7 DECW @PC+d16 DECW addr16 MOVW MOVW A, A, @RW1 @RW1+d16 MOVW MOVW A, A, @RW2 @RW2+d16 MOVW MOVW A, A, @RW3 @RW3+d16 MOVW MOVW A, A, RW7 @RW7+d8 MOVW MOVW A, A, RW6 @RW6+d8 MOVW RW6, A MOVW RW7, A MOVW MOVW A, A, RW5 @RW5+d8 MOVW RW5, A MOVW MOVW A, A, RW4 @RW4+d8 MOVW RW4, A MOVW MOVW A, A, RW3 @RW3+d8 MOVW RW3, A MOVW MOVW A, A, RW2 @RW2+d8 MOVW RW2, A MOVW MOVW A, A, RW1 @RW1+d8 MOVW RW1, A INCW @RW1+d8 INCW @RW2+d8 INCW @RW3+d8 INCW @RW4+d8 INCW @RW5+d8 INCW @RW6+d8 INCW @RW7+d8 DECW @RW0 DECW @RW1 DECW @RW2 DECW @RW3 DECW @RW0+ DECW @RW1+ DECW @RW2+ DECW @RW3+ DECW RW7 DECW RW6 DECW RW5 DECW RW4 DECW RW3 DECW RW2 DECW RW1 CALL @@RW1+d8 CALL @@RW2+d8 CALL @@RW3+d8 CALL @@RW4+d8 CALL @@RW5+d8 CALL @@RW6+d8 CALL @@RW7+d8 INCW INCW @RW0 @RW0+d16 INCW INCW @RW1 @RW1+d16 INCW INCW @RW2 @RW2+d16 INCW INCW @RW3 @RW3+d16 INCW INCW @RW0+ @RW0+RW7 INCW INCW @RW1+ @RW1+RW7 INCW INCW @RW2+ @PC+d16 INCW INCW @RW3+ addr16 INCW RW7 INCW RW6 INCW RW5 INCW RW4 INCW RW3 INCW RW2 INCW RW1 INCW RW0 DECW RW0 MOVW MOVW A, A, RW0 @RW0+d8 MOVW RW0, A 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 XCHW A, @RW0+d8 XCHW A, @RW1+d8 XCHW A, @RW2+d8 XCHW A, @RW3+d8 XCHW A, @RW4+d8 XCHW A, @RW5+d8 MOVW @R MOVW MOVW @RW XCHW RW6, #16 6+d8, #16 A, RW6 W6+d8, A MOVW @R MOVW MOVW @RW XCHW RW7, #16 7+d8, #16 A, RW7 W7+d8, A XCHW A, @RW6+d8 XCHW A, @RW7+d8 MOVW @R MOVW MOVW @RW XCHW RW0, #16 0+d8, #16 A, RW0 W0+d8, A MOVW @R MOVW MOVW @RW XCHW RW1, #16 1+d8, #16 A, RW1 W1+d8, A MOVW @R MOVW MOVW @RW XCHW RW2, #16 2+d8, #16 A, RW2 W2+d8, A MOVW @R MOVW MOVW @RW XCHW RW3, #16 3+d8, #16 A, RW3 W3+d8, A MOVW @R MOVW MOVW @RW XCHW RW4, #16 4+d8, #16 A, RW4 W4+d8, A MOVW @R MOVW MOVW @RW XCHW RW5, #16 5+d8, #16 A, RW5 W5+d8, A MOVW MOVW MOVW A, MOVW @R MOVW MOVW@RW0 XCHW XCHW A, A, @RW0 @RW0+d16 @RW0, A W0+d16, A @RW0, #16 +d16, #16 A, @RW0 @RW0+d16 MOVW @RW1. A MOVW @RW2, A MOVW @RW3, A MOVW @R MOVW MOVW@RW1 XCHW @RW1, #16 +d16, #16 A, @RW1 W1+d16, A MOVW @R MOVW MOVW@ RW2 XCHW @RW2, #16 +d16, #16 A, @RW2 W2+d16, A MOVW @R MOVW MOVW @RW3 XCHW @RW3, #16 +d16, #16 A, @RW3 W3+d16, A XCHW A, @RW1+d16 XCHW A, @RW2+d16 XCHW A, @RW3+d16 CALL @@RW1+d16 CALL @@RW2+d16 CALL @@RW3+d16 00 10 +0 JMP @RW0 JMP @@RW0+d8 CALL @RW0 +1 JMP @RW1 JMP @@RW1+d8 CALL @RW1 APPENDIX B INSTRUCTIONS MOVW MOVW A, A, @RW2+ @PC+d16 MOVW MOVW A, A, @RW3+ addr16 MOVW MOVW @RW3+, A addr16, A MOVW @ MOVW ad RW3+, #16 dr16, #16 +2 JMP @RW2 JMP @@RW2+d8 CALL @RW2 +3 JMP @RW3 JMP @@RW3+d8 CALL @RW3 +4 JMP @RW4 JMP @@RW4+d8 CALL @RW4 +5 JMP @RW5 JMP @@RW5+d8 CALL @RW5 +6 JMP @RW6 JMP @@RW6+d8 CALL @RW6 +7 JMP @RW7 JMP @@RW7+d8 CALL @RW7 +8 JMP JMP @@RW0 @@RW0+d16 CALL CALL @@RW0 @@RW0+d16 +9 JMP JMP @@RW1 @@RW1+d16 CALL @@RW1 +A JMP JMP @@RW2 @@RW2+d16 CALL @@RW2 +B JMP JMP @@RW3 @@RW3+d16 CALL @@RW3 Table B.9-9 ea instruction map (4) (1st byte = 73H) +C JMP JMP CALL CALL @ @@RW0+ @@RW0+RW7 @@RW0+ @RW0+RW7 MOVW MOVW MOVW A, MOVW @R MOVW @ MOVW@RW0 XCHW XCHW A, A, @RW0+ @RW0+RW7 @RW0+, A W0+RW7, A RW0+, #16 +RW7, #16 A, @RW0+ @RW0+RW7 MOVW MOVW MOVW A, MOVW @R MOVW @ MOVW @RW1 XCHW XCHW A, A, @RW1+ @RW1+RW7 @RW1+, A W1+RW7, A RW1+, #16 +RW7, #16 A, @RW1+ @RW1+RW7 MOVW MOVW @P MOVW @ MOVW @PC XCHW XCHW A, @RW2+, A C+d16, A RW2+, #16 +d16, #16 A, @RW2+ @PC+d16 XCHW XCHW A, A, @RW3+ addr16 +D JMP JMP CALL CALL @ @@RW1+ @@RW1+RW7 @@RW1+ @RW1+RW7 +E JMP JMP @@RW2+ @@PC+d16 CALL CALL @@RW2+ @@PC+d16 +F JMP JMP @@RW3+ @addr16 CALL CALL @@RW3+ @addr16 MB90560 series MB90560 series 20 SUB A, @RW0+d8 ADDC A, @RW0+d8 CMP A, @RW0+d8 AND A, @RW0+d8 A, R0 OR A, R1 OR A, R2 OR A, R3 OR A, R4 OR A, R5 OR A, R6 OR A, R7 AND A, @RW1+d8 AND A, @RW2+d8 AND A, @RW3+d8 AND A, @RW4+d8 AND A, @RW5+d8 AND A, @RW6+d8 AND A, @RW7+d8 OR A, XOR A, R1 @RW1+d8 OR A, XOR A, R2 @RW2+d8 OR A, XOR A, R3 @RW3+d8 OR A, XOR A, R4 @RW4+d8 OR A, XOR A, R5 @RW5+d8 OR A, XOR A, R6 @RW6+d8 OR A, XOR A, R7 @RW7+d8 CMP A, @RW1+d8 CMP A, @RW2+d8 CMP A, @RW3+d8 CMP A, @RW4+d8 CMP A, @RW5+d8 CMP A, @RW6+d8 CMP A, @RW7+d8 AND A, R7 AND A, R6 AND A, R5 AND A, R4 AND A, R3 AND A, R2 AND A, R1 ADDC A, @RW1+d8 ADDC A, @RW2+d8 ADDC A, @RW3+d8 ADDC A, @RW4+d8 ADDC A, @RW5+d8 ADDC A, @RW6+d8 ADDC A, @RW7+d8 ADDC A, @RW0+d16 ADDC A, @RW1+d16 ADDC A, @RW2+d16 ADDC A, @RW3+d16 CMP CMP A, A, @RW3 @RW3+d16 CMP CMP A, A, @RW0+ @RW0+RW7 CMP CMP A, A, @RW1+ @RW1+RW7 CMP CMP A, A, @RW2+ @PC+d16 CMP CMP A, A, @RW3+ addr16 A, CMP CMP A, A, @RW2 @RW2+d16 CMP CMP A, A, @RW1 @RW1+d16 CMP CMP A, A, @RW0 @RW0+d16 CMP A, R7 CMP A, R6 CMP A, R5 CMP A, R4 CMP A, R3 CMP A, R2 CMP A, R1 SUB A, @RW1+d8 SUB A, @RW2+d8 SUB A, @RW3+d8 SUB A, @RW4+d8 SUB A, @RW5+d8 SUB A, @RW6+d8 SUB A, @RW7+d8 ADDC A, @RW0 ADDC A, @RW1 ADDC A, @RW2 ADDC A, @RW3 ADDC ADDC A, A, @RW0+ @RW0+RW7 ADDC ADDC A, A, @RW1+ @RW1+RW7 ADDC ADDC A, A, @RW2+ @PC+d16 ADDC ADDC A, @RW3+ addr16 ADDC A. R7 ADDC A, R6 ADDC A, R5 ADDC A, R4 ADDC A, R3 ADDC A, R2 ADDC A, R1 ADDC A, R0 CMP A, R0 AND A, R0 OR OR A, XOR A, R0 @RW0+d8 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 XOR A, DBNZ DBNZ @ R0, r RW0+d8, r @RW0+d8 XOR A, DBNZ DBNZ @ R1, r RW1+d8, r @RW1+d8 XOR A, DBNZ DBNZ @ R2, r RW2+d8, r @RW2+d8 XOR A, DBNZ DBNZ @ R3, r RW3+d8, r @RW3+d8 XOR A, DBNZ DBNZ @ R4, r RW4+d8, r @RW4+d8 XOR A, DBNZ DBNZ @ R5, r RW5+d8, r @RW5+d8 XOR A, DBNZ DBNZ @ R6, r RW6+d8, r @RW6+d8 XOR A, DBNZ DBNZ @ R7, r RW7+d8, r @RW7+d8 XOR A, DBNZ @RW0, r @RW0+d16 OR A, @RW1 OR A, @RW2 AND AND A, A, @RW3 @RW3+d16 OR A, @RW3 OR A, XOR A, @RW1 @RW1+d16 OR A, XOR A, @RW2 @RW2+d16 OR A, XOR A, @RW3 @RW3+d16 AND AND A, OR OR A, XOR A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ AND AND A, OR OR A, XOR A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ AND AND A, A, @RW2+ @PC+d16 AND AND A, A, @RW3+ addr16 OR OR A, A, @RW2+ @ PC+d16 OR OR A, A, @RW3+ addr16 XOR A, @RW2+ XOR A, @RW3+ XOR A, DBNZ @RW1, r @RW1+d16 XOR A, DBNZ @RW2, r @RW2+d16 XOR A, DBNZ @RW3, r @RW3+d16 DBNZ RW0+d16, r DBNZ RW1+d16, r DBNZ RW2+d16, r DBNZ RW3+d16, r XOR A, DBNZ DBNZ @RW0+RW7 @RW0+, r RW0+RW7, r XOR A, DBNZ DBNZ @RW1+RW7 @RW1+, r RW1+RW7, r XOR A, @PC+d16 XOR addr16 A, DBNZ DBNZ @RW2+, r @ PC+d16, r DBNZ DBNZ @RW3+, r @ addr16, r AND AND A, OR OR A, XOR A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 AND AND A, A, @RW1 @RW1+d16 AND AND A, A, @RW2 @RW2+d16 00 10 +0 ADD A, R0 ADD A, @RW0+d8 SUB A, R0 +1 ADD A, R1 ADD A, @RW1+d8 SUB A, R1 +2 ADD A, R2 ADD A, @RW2+d8 SUB A, R2 +3 ADD A, R3 ADD A, @RW3+d8 SUB A, R3 +4 ADD A, R4 ADD A, @RW4+d8 SUB A, R4 +5 ADD A, R5 ADD A, @RW5+d8 SUB A, R5 +6 ADD A, R6 ADD A, @RW6+d8 SUB A, R6 +7 ADD A, R7 ADD A, @RW7+d8 SUB A, R7 +8 ADD ADD A, A, @RW0 @RW0+d16 SUB SUB A, A, @RW0 @RW0+d16 +9 ADD A, @RW1 ADD A, @RW1+d16 SUB SUB A, A, @RW1 @RW1+d16 +A ADD A, @RW2 ADD A, @RW2+d16 SUB SUB A, A, @RW2 @RW2+d16 +B ADD A, @RW3 ADD A, @RW3+d16 SUB SUB A, A, @RW3 @RW3+d16 +C ADD ADD A, A, @RW0+ @RW0+RW7 SUB SUB A, A, @RW0+ @RW0+RW7 Table B.9-10 ea instruction map (5) (1st byte = 74H) +D ADD ADD A, A, @RW1+ @RW1+RW7 SUB SUB A, A, @RW1+ @RW1+RW7 +E ADD ADD A, A, @RW2+ @PC+d16 SUB SUB A, A, @RW2+ @PC+d16 APPENDIX B INSTRUCTIONS +F ADD ADD A, A, @RW3+ addr16 SUB SUB A, A, @RW3+ addr16 533 534 20 SUB @R W0+d8, A SUBC A, @RW0+d8 NEG @RW0+d8 OR @RW0+d8, A R0, A XOR R1, A XOR R2, A XOR R3, A XOR R4, A XOR R5, A XOR OR @RW6+d8, A OR @RW7+d8, A R6, A XOR R7, A OR @RW1+d8, A OR @RW2+d8, A OR @RW3+d8, A OR @RW4+d8, A OR @RW5+d8, A NEG @RW1+d8 NEG @RW2+d8 NEG @RW3+d8 NEG @RW4+d8 NEG @RW5+d8 NEG @RW6+d8 NEG @RW7+d8 NEG @RW0+d16 NEG @RW1+d16 NEG @RW2+d16 NEG @RW3+d16 NEG @RW0+RW7 NEG @RW1+RW7 NEG @PC+d16 NEG addr16 AND @RW3, A AND @RW2, A AND @RW1, A AND R7, A AND @R OR R7, A W7+d8, A AND R6, A AND @R OR R6, A W6+d8, A AND R5, A AND @R OR R5, A W5+d8, A AND R4, A AND @R OR R4, A W4+d8, A AND R3, A AND @R OR R3, A W3+d8, A AND R2, A AND @R OR R2, A W2+d8, A AND R1, A AND @R OR R1, A W1+d8, A SUBC A, @RW1+d8 SUBC A, @RW2+d8 SUBC A, @RW3+d8 SUBC A, @RW4+d8 SUBC A, @RW5+d8 SUBC A, @RW6+d8 SUBC A, @RW7+d8 NEG @RW0 NEG @RW1 NEG @RW2 NEG @RW3 NEG @RW0+ NEG @RW1+ NEG @RW2+ NEG @RW3+ NEG R7 NEG R6 NEG R5 NEG R4 NEG R3 NEG R2 NEG R1 SUB @R W1+d8, A SUB @R W2+d8, A SUB @R W3+d8, A SUB @R W4+d8, A SUB @R W5+d8, A SUB @R W6+d8, A SUB @R W7+d8, A SUBC SUBC A, A, @RW0 @RW0+d16 SUBC SUBC A, A, @RW1 @RW1+d16 SUBC SUBC A, A, @RW2 @RW2+d16 SUBC SUBC A, A, @RW3 @RW3+d16 SUBC SUBC A, A, @RW0+ @RW0+RW7 SUBC SUBC A, A, @RW1+ @RW1+RW7 SUBC SUBC A, A, @RW2+ @PC+d16 SUBC SUBC A, @RW3+ addr16 A, SUBC A, R7 SUBC A, R6 SUBC A, R5 SUBC A, R4 SUBC A, R3 SUBC A, R2 SUBC A, R1 SUBC A, R0 NEG R0 AND R0, A AND @R OR R0, A W0+d8, A XOR 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 NOT @RW0+d8 NOT @RW1+d8 XOR @R NOT R2 W2+d8, A XOR @R NOT R3 W3+d8, A XOR @R NOT R4 W4+d8, A XOR @R NOT R5 W5+d8, A XOR @R NOT R6 W6+d8, A XOR @R NOT R7 W7+d8, A XOR @R NOT @RW0 W0+d16, A XOR @R NOT @RW1 W1+d16, A XOR @R NOT @RW2 W2+d16, A XOR AND @R OR OR @RW2, A @RW2+d16, A @RW2, A W2+d16, A XOR AND @R OR OR @RW3, A @RW3+d16, A @RW3, A W3+d16, A XOR @RW0+, A AND AND @R OR OR @R @RW1+, A W1+RW7, A @RW1+, A W1+RW7, A AND AND @P OR OR @RW2+, A @RW2+, A @PC+d16, A C+d16, A AND AND @RW3+, A addr16, A OR OR @RW3+, A addr16, A XOR @RW1+, A XOR @RW2+, A XOR @RW3+, A XOR @R NOT @RW3 W3+d16, A XOR @R NOT W0+RW7, A @RW0+ XOR @R NOT W1+RW7, A @RW1+ XOR @P NOT @RW2+ C+d16, A XOR addr16, A NOT @RW3+ NOT @RW2+d8 NOT @RW3+d8 NOT @RW4+d8 NOT @RW5+d8 NOT @RW6+d8 NOT @RW7+d8 NOT @RW0+d16 NOT @RW1+d16 NOT @RW2+d16 NOT @RW3+d16 NOT @RW0+RW7 NOT @RW1+RW7 NOT @PC+d16 NOT addr16 XOR @R NOT R0 W0+d8, A XOR @R NOT R1 W1+d8, A AND XOR AND @R OR OR @RW0, A W0+d16, A @RW0, A @RW0+d16, A @RW0, A XOR AND @R OR OR @RW1, A @RW1+d16, A @RW1, A W1+d16, A 00 10 +0 ADD R0, A ADD @R SUB W0+d8, A R0, A +1 ADD R1, A ADD @R SUB W1+d8, A R1, A APPENDIX B INSTRUCTIONS AND AND @R OR OR @R @RW0+, A W0+RW7, A @RW0+, A W0+RW7, A +2 ADD R2, A ADD @R SUB W2+d8, A R2, A +3 ADD R3, A ADD @R SUB W3+d8, A R3, A +4 ADD R4, A ADD @R SUB W4+d8, A R4, A +5 ADD R5, A ADD @R SUB W5+d8, A R5, A +6 ADD R6, A ADD @R SUB W6+d8, A R6, A +7 ADD R7, A ADD @R SUB W7+d8, A R7, A +8 ADD @R SUB ADD SUB @R @RW0, A W0+d16, A @RW0, A W0+d16, A +9 ADD @RW1, A ADD @R SUB SUB @R W1+d16, A @RW1, A W1+d16, A +A ADD @RW2, A ADD @R SUB SUB @R RW2+d16, A @RW2, A W2+d16, A +B ADD @RW3, A ADD @R SUB SUB @R RW3+d16, A @RW3, A W3+d16, A Table B.9-11 ea instruction map (6) (1st byte = 75H) +C ADD ADD @R SUB SUB @R @RW0+, A W0+RW7, A @RW0+, A W0+RW7, A +D ADD ADD @R SUB SUB @R @RW1+, A W1+RW7, A @RW1+, A W1+RW7, A +E ADD @P SUB ADD SUB @P @RW2+, A C+d16, A @RW2+, A C+d16, A +F ADD ADD SUB SUB @RW3+, A addr16, A @RW3+, A addr16, A MB90560 series MB90560 series 20 ADDCW ADDCW A, A, RW0 @RW0+d8 CMPW CMPW A, A, RW0 @RW0+d8 ANDW ANDW A, ORW A, RW0 A, RW0 @RW0+d8 ANDW ANDW A, ORW A, RW1 A, RW1 @RW1+d8 ANDW ANDW A, ORW A, RW2 A, RW2 @RW2+d8 ANDW ANDW A, ORW A, RW3 A, RW3 @RW3+d8 ANDW ANDW A, ORW A, RW4 A, RW4 @RW4+d8 ANDW ANDW A, ORW A, RW5 A, RW5 @RW5+d8 ANDW ANDW A, ORW A, RW6 A, RW6 @RW6+d8 ANDW ANDW A, ORW A, RW7 A, RW7 @RW7+d8 CMPW CMPW A, A, RW1 @RW1+d8 CMPW CMPW A, A, RW2 @RW2+d8 CMPW CMPW A, A, RW3 @RW3+d8 CMPW CMPW A, A, RW4 @RW4+d8 CMPW CMPW A, A, RW5 @RW5+d8 CMPW CMPW A, A, RW6 @RW6+d8 CMPW CMPW A, A, RW7 @RW7+d8 CMPW CMPW A, A, @RW0 @RW0+d16 CMPW CMPW A, A, @RW1 @RW1+d16 CMPW CMPW A, A, @RW2 @RW2+d16 CMPW CMPW A, A, @RW3 @RW3+d16 CMPW CMPW A, A, @RW0+ @RW0+RW7 CMPW CMPW A, A, @RW1+ @RW1+RW7 CMPW CMPW A, A, @RW2+ @PC+d16 CMPW CMPW A, @RW3+ addr16 A, A, ADDCW ADDCW A, A, RW1 @RW1+d8 ADDCW ADDCW A, A, RW2 @RW2+d8 ADDCW ADDCW A, A, RW3 @RW3+d8 ADDCW ADDCW A, A, RW4 @RW4+d8 ADDCW ADDCW A, A, RW5 @RW5+d8 ADDCW ADDCW A, A, RW6 @RW6+d8 ADDCW ADDCW A, A, RW7 @RW7+d8 ADDCW ADDCW A, A, @RW0 @RW0+d16 ADDCW ADDCW A, A, @RW1 @RW1+d16 ADDCW ADDCW A, A, @RW2 @RW2+d16 ADDCW ADDCW A, A, @RW3 @RW3+d16 ADDCW ADDCW A, A, @RW0+ @RW0+RW7 ADDCW ADDCW A, A, @RW1+ @RW1+RW7 ADDCW ADDCW A, A, @RW2+ @PC+d16 ADDCW ADDCW A, @RW3+ addr16 ORW A, XORW A, RW0 @RW0+d8 ORW A, XORW A, RW1 @RW1+d8 ORW A, XORW A, RW2 @RW2+d8 ORW A, XORW A, RW3 @RW3+d8 ORW A, XORW A, RW4 @RW4+d8 ORW A, XORW A, RW5 @RW5+d8 ORW A, XORW A, RW6 @RW6+d8 ORW A, XORW A, RW7 @RW7+d8 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 XORW A, DWBNZ DWBNZ @ RW0, r RW0+d8, r @RW0+d8 XORW A, DWBNZ DWBNZ @ RW1, r RW1+d8, r @RW1+d8 XORW A, DWBNZ DWBNZ @ RW2, r RW2+d8, r @RW2+d8 XORW A, DWBNZ DWBNZ @ RW3, r RW3+d8, r @RW3+d8 XORW A, DWBNZ DWBNZ @ RW4, r RW4+d8, r @RW4+d8 XORW A, DWBNZ DWBNZ @ RW5, r RW5+d8, r @RW5+d8 XORW A, DWBNZ DWBNZ @ RW6, r RW6+d8, r @RW6+d8 XORW A, DWBNZ DWBNZ @ RW7, r RW7+d8, r @RW7+d8 XORW A, DWBNZ @RW0, r @RW0+d16 XORW A, DWBNZ @RW1, r @RW1+d16 XORW A, DWBNZ @RW2, r @RW2+d16 ANDW ANDW A, ORW ORW A, XORW A, @RW3 @RW3+d16 A, @RW3 A, @RW3 @RW3+d16 ANDW ANDW A, ORW ORW A, XORW A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ ANDW ANDW A, ORW ORW A, XORW A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ ANDW ANDW A, ORW ORW A, XORW A, @RW2+ @PC+d16 A, @RW2+ @ PC+d16 A, @RW2+ ANDW ANDW A, ORW ORW A, @RW3+ addr16 A, @RW3+ addr16 A, XORW A, @RW3+ XORW A, DWBNZ @RW3, r @RW3+d16 DWBNZ @R W0+d16, r DWBNZ @R W1+d16, r DWBNZ @R W2+d16, r DWBNZ @R W3+d16, r XORW A, DWBNZ DWBNZ @R @RW0+, r W0+RW7, r @RW0+RW7 XORW A, DWBNZ DWBNZ @R @RW1+, r W1+RW7, r @RW1+RW7 XORW A, DWBNZ DWBNZ @ @RW2+, r PC+d16, r @PC+d16 XORW addr16 A, DWBNZ DWBNZ @RW3+, r addr16, r ANDW ANDW A, ORW ORW A, XORW A, @RW0 @RW0+d16 A, @RW0 A, @RW0 @RW0+d16 ANDW ANDW A, ORW ORW A, XORW A, @RW1 @RW1+d16 A, @RW1 A, @RW1 @RW1+d16 ANDW ANDW A, ORW ORW A, XORW A, @RW2 @RW2+d16 A, @RW2 A, @RW2 @RW2+d16 00 10 +0 ADDW A, RW0 ADDW A, @RW0+d8 SUBW SUBW A, A, RW0 @RW0+d8 +1 ADDW A, RW1 ADDW A, @RW1+d8 SUBW SUBW A, A, RW1 @RW1+d8 +2 ADDW A, RW2 ADDW A, @RW2+d8 SUBW SUBW A, A, RW2 @RW2+d8 +3 ADDW A, RW3 ADDW A, @RW3+d8 SUBW SUBW A, A, RW3 @RW3+d8 +4 ADDW A, RW4 ADDW A, @RW4+d8 SUBW SUBW A, A, RW4 @RW4+d8 +5 ADDW A, RW5 ADDW A, @RW5+d8 SUBW SUBW A, A, RW5 @RW5+d8 +6 ADDW A, RW6 ADDW A, @RW6+d8 SUBW SUBW A, A, RW6 @RW6+d8 +7 ADDW A, RW7 ADDW A, @RW7+d8 SUBW SUBW A, A, RW7 @RW7+d8 +8 ADDW ADDW A, SUBW SUBW A, A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 +9 ADDW A, @RW1 ADDW A, @RW1+d16 SUBW SUBW A, A, @RW1 @RW1+d16 +A ADDW A, @RW2 ADDW A, @RW2+d16 SUBW SUBW A, A, @RW2 @RW2+d16 +B ADDW A, @RW3 ADDW A, @RW3+d16 SUBW SUBW A, A, @RW3 @RW3+d16 +C ADDW ADDW A, A, @RW0+ @RW0+RW7 SUBW SUBW A, A, @RW0+ @RW0+RW7 Table B.9-12 ea instruction map (7) (1st byte = 76H) +D ADDW ADDW A, A, @RW1+ @RW1+RW7 SUBW SUBW A, A, @RW1+ @RW1+RW7 +E ADDW ADDW A, A, @RW2+ @PC+d16 SUBW SUBW A, A, @RW2+ @PC+d16 APPENDIX B INSTRUCTIONS +F ADDW ADDW A, A, @RW3+ addr16 SUBW SUBW A, A, @RW3+ addr16 535 536 20 SUBCW SUBCW A, A, RW0 @RW0+d8 SUBCW SUBCW A, A, RW1 @RW1+d8 SUBCW SUBCW A, A, RW2 @RW2+d8 SUBCW SUBCW A, A, RW3 @RW3+d8 SUBCW SUBCW A, A, RW4 @RW4+d8 SUBCW SUBCW A, A, RW5 @RW5+d8 SUBCW SUBCW A, A, RW6 @RW6+d8 SUBCW A,RW7 SUBCW SUBCW A, A, @RW0 @RW0+d16 SUBCW SUBCW A, A, @RW1 @RW1+d16 SUBCW SUBCW A, A, @RW2 @RW2+d16 SUBCW SUBCW A, A, @RW3 @RW3+d16 SUBCW SUBCW A, A, @RW0+ @RW0+RW7 SUBCW SUBCW A, A, @RW1+ @RW1+RW7 SUBCW SUBCW A, A, @RW2+ @PC+d16 SUBCW SUBCW A, @RW3+ addr16 A, NEGW NEGW @RW2+ @PC+d16 NEGW NEGW @RW3+ addr16 NEGW NEGW @RW1+ @RW1+RW7 NEGW NEGW @RW0+ @RW0+RW7 NEGW NEGW @RW3 @RW3+d16 NEGW NEGW @RW2 @RW2+d16 NEGW NEGW @RW1 @RW1+d16 ANDW ANDW @R @RW1, A W1+d16, A ANDW ANDW @R @RW2, A W2+d16, A ANDW ANDW @R @RW3, A W3+d16, A NEGW NEGW @RW0 @RW0+d16 ANDW ANDW @R @RW0, A W0+d16, A SUBCW A, @RW7+d8 NEGW NEGW RW7 @RW7+d8 ANDW ANDW @R RW7, A W7+d8, A ORW RW7, A NEGW NEGW RW6 @RW6+d8 ANDW ANDW @R RW6, A W6+d8, A ORW RW6, A NEGW NEGW RW5 @RW5+d8 ANDW ANDW @R RW5, A W5+d8, A ORW RW5, A NEGW NEGW RW4 @RW4+d8 ANDW ANDW @R RW4, A W4+d8, A ORW RW4, A NEGW NEGW RW3 @RW3+d8 ANDW ANDW @R RW3, A W3+d8, A ORW RW3, A NEGW NEGW RW2 @RW2+d8 ANDW ANDW @R RW2, A W2+d8, A OWR RW2, A ORW @R XORW W2+d8, A RW2, A ORW @R XORW W3+d8, A RW3, A ORW @R XORW W4+d8, A RW4, A ORW @R XORW W5+d8, A RW5, A ORW @R XORW W6+d8, A RW6, A ORW @R XORW W7+d8, A RW7, A NEGW NEGW RW1 @RW1+d8 ANDW ANDW @R RW1, A W1+d8, A ORW RW1, A ORW @R XORW W1+d8, A RW1, A NEGW NEGW RW0 @RW0+d8 ANDW ANDW @R RW0, A W0+d8, A ORW RW0, A ORW @R XORW W0+d8, A RW0, A 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 NOTW @RW0+d8 NOTW @RW1+d8 XORW @R NOTW RW2 W2+d8, A XORW @R NOTW RW3 W3+d8, A XORW @R NOTW RW4 W4+d8, A XORW @R NOTW RW5 W5+d8, A XORW @R NOTW RW6 W6+d8, A XORW @R NOTW W7+d8, A RW7 XORW @R NOTW @RW0 W0+d16, A ORW @RW1, A ORW @RW2, A ORW @RW3, A ORW @R XORW W1+d16, A @RW1, A ORW @R XORW W2+d16, A @RW2, A ORW @R XORW W3+d16, A @RW3, A ORW @R XORW W0+RW7, A @RW0+, A ANDW ANDW @R ORW ORW @R XORW @RW1+, A W1+RW7, A @RW1+, A W1+RW7, A @RW1+, A ANDW ANDW @P ORW @RW2+, A C+d16, A @RW2+, A ANDW ANDW @RW3+, A addr16, A ORW @P XORW @RW2+, A C+d16, A ORW ORW @RW3+, A addr16, A XORW @RW3+, A XORW @R NOTW @RW1 W1+d16, A XORW @R NOTW W2+d16, A @RW2 XORW @R NOTW @RW3 W3+d16, A XORW @R NOTW @RW0+ W0+RW7, A XORW @R NOTW @RW1+ W1+RW7, A XORW @P NOTW @RW2+ C+d16, A XORW addr16, A NOTW @RW3+ NOTW @RW2+d8 NOTW @RW3+d8 NOTW @RW4+d8 NOTW @RW5+d8 NOTW @RW6+d8 NOTW @RW7+d8 NOTW @RW0+d16 NOTW @RW1+d16 NOTW @RW2+d16 NOTW @RW3+d16 NOTW @RW0+RW7 NOTW @RW1+RW7 NOTW @PC+d16 NOTW addr16 XORW @R NOTW RW0 W0+d8, A XORW @R NOTW RW1 W1+d8, A SUBW @R W0+d16, A SUBW @R W1+d16, A SUBW @R W2+d16, A ORW ORW @R XORW @RW0, A W0+d16, A @RW0, A ANDW ANDW @R ORW @RW0+, A W0+RW7, A @RW0+, A 00 10 +0 ADDW RW0, A ADDW @R W0+d8, A SUBW SUBW @R RW0, A W0+d8, A +1 ADDW RW1, A ADDW @R W1+d8, A SUBW SUBW @R RW1, A W1+d8, A APPENDIX B INSTRUCTIONS +2 ADDW RW2, A ADDW @R W2+d8, A SUBW SUBW @R RW2, A W2+d8, A +3 ADDW RW3, A ADDW @R W3+d8, A SUBW SUBW @R RW3, A W3+d8, A +4 ADDW RW4, A ADDW @R W4+d8, A SUBW SUBW @R RW4, A W4+d8, A +5 ADDW RW5, A ADDW @R W5+d8, A SUBW SUBW @R RW5, A W5+d8, A +6 ADDW RW6, A ADDW @R W6+d8, A SUBW SUBW @R RW6, A W6+d8, A +7 ADDW RW7, A ADDW @R W7+d8, A SUBW SUBW @R RW7, A W7+d8, A +8 ADDW @RW0, A ADDW @R W0+d16, A SUBW @RW0, A +9 ADDW @RW1, A ADDW @R W1+d16, A SUBW @RW1, A +A ADDW @RW2, A ADDW @R W2+d16, A SUBW @RW2, A +B ADDW @RW3, A ADDW @R W3+d16, A SUBW SUBW @R @RW3, A W3+d16, A +C ADDW @RW0+, A ADDW @R W0+RW7 SUBW SUBW @R @RW0+, A W0+RW7, A Table B.9-13 ea instruction map (8) (1st byte = 77H) +D ADDW @RW1+, A ADDW @R W1+RW7 SUBW SUBW @R @RW1+, A W1+RW7, A +E ADDW @RW2+, A ADDW @P C+d16, A SUBW SUBW @RW2+, A @PC+d16, A +F ADDW @RW3+, A ADDW addr16, A SUBW SUBW @RW3+, A addr16, A MB90560 series MB90560 series 20 MUL A, @RW0+d8 MUL A, @RW1+d8 MUL A, @RW2+d8 MUL A, @RW3+d8 MUL A, @RW4+d8 MUL A, @RW5+d8 MUL A, @RW6+d8 MUL A, @RW7+d8 MULW MULW A, A, @RW0 @RW0+d16 MULW MULW A, A, @RW1 @RW1+d16 MULW MULW A, A, @RW2 @RW2+d16 MULW MULW A, A, @RW3 @RW3+d16 MULW MULW A, A, @RW0+ @RW0+RW7 MULW MULW A, A, @RW1+ @RW1+RW7 MULW MULW A, A, @RW2+ @PC+d16 MULW MULW A, A, @RW3+ addr16 MULW MULW A, A, RW7 @RW7+d8 DIVU A, R7 DIVU A, @RW7+d8 MULW MULW A, A, RW6 @RW6+d8 DIVU A, R6 DIVU A, @RW6+d8 MULW MULW A, A, RW5 @RW5+d8 DIVU A, R5 DIVU A, @RW5+d8 DIVUW A, RW5 DIVUW A, RW6 DIVUW A, RW7 MULW MULW A, A, RW4 @RW4+d8 DIVU A, R4 DIVU A, @RW4+d8 DIVUW A, RW4 MULW MULW A, A, RW3 @RW3+d8 DIVU A, R3 DIVU A, @RW3+d8 DIVUW A, RW3 MULW MULW A, A, RW2 @RW2+d8 DIVU A, R2 DIVU A, @RW2+d8 DIVUW A, RW2 MULW MULW A, A, RW1 @RW1+d8 DIVU A, R1 DIVU A, @RW1+d8 DIVUW A, RW1 DIVUW A, DIV @RW1+d8 A, R1 DIVUW A, DIV @RW2+d8 A, R2 DIVUW A, DIV @RW3+d8 A, R3 DIVUW A, DIV @RW4+d8 A, R4 DIVUW A, DIV @RW5+d8 A, R5 DIVUW A, DIV @RW6+d8 A, R6 DIVUW A, DIV @RW7+d8 A, R7 MULW MULW A, A, RW0 @RW0+d8 DIVU A, R0 DIVU A, @RW0+d8 DIVUW A, DIV @RW0+d8 A, R0 DIVUW A, RW0 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 DIV A, DIVW @RW0+d8 A, RW0 DIV A, DIVW @RW1+d8 A, RW1 DIV A, DIVW @RW2+d8 A, RW2 DIV A, DIVW @RW3+d8 A, RW3 DIV A, DIVW @RW4+d8 A, RW4 DIV A, DIVW @RW5+d8 A, RW5 DIV A, DIVW @RW6+d8 A, RW6 DIV A, DIVW @RW7+d8 A, RW7 F0 DIVW A, @RW0+d8 DIVW A, @RW1+d8 DIVW A, @RW2+d8 DIVW A, @RW3+d8 DIVW A, @RW4+d8 DIVW A, @RW5+d8 DIVW A, @RW6+d8 DIVW A, @RW7+d8 DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 DIVU DIVU A, A, @RW1 @RW1+d16 DIVU DIVU A, A, @RW2 @RW2+d16 DIVU DIVU A, A, @RW3 @RW3+d16 DIVUW A, @RW1 DIVUW A, @RW2 DIVUW A, @RW3 DIVUW A, DIV DIV A, DIVW @RW1+d16 A, @RW1 @RW1+d16 A, @RW1 DIVUW A, DIV DIV A, DIVW @RW2+d16 A, @RW2 @RW2+d16 A, @RW2 DIVUW A, DIV DIV A, DIVW @RW3+d16 A, @RW3 @RW3+d16 A, @RW3 DIVW A, @RW1+d16 DIVW A, @RW2+d16 DIVW A, @RW3+d16 DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 DIVU DIVU A, A, @RW2+ @PC+d16 DIVU DIVU A, A, @RW3+ addr16 DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, @RW2+ @ PC+d16 A, @RW2+ @PC+d16 A, @RW2+ @ PC+d16 DIVUW DIVUW A, @RW3+ addr16 A, DIV DIV A, A, @RW3+ addr16 DIVW DIVW A, A, @RW3+ addr16 MUL A, @RW1+d16 MUL A, @RW2+d16 MUL A, @RW3+d16 00 10 +0 MULU A, R0 MULU A, @RW0+d8 MULUW MULUW A, MUL A, RW0 @RW0+d8 A, R0 +1 MULU A, R1 MULU A, @RW1+d8 MULUW MULUW A, MUL A, RW1 @RW1+d8 A, R1 +2 MULU A, R2 MULU A, @RW2+d8 MULUW MULUW A, MUL A, RW2 @RW2+d8 A, R2 +3 MULU A, R3 MULU A, @RW3+d8 MULUW MULUW A, MUL A, RW3 @RW3+d8 A, R3 +4 MULU A, R4 MULU A, @RW4+d8 MULUW MULUW A, MUL A, RW4 @RW4+d8 A, R4 +5 MULU A, R5 MULU A, @RW5+d8 MULUW MULUW A, MUL A, RW5 @RW5+d8 A, R5 +6 MULU A, R6 MULU A, @RW6+d8 MULUW MULUW A, MUL A, RW6 @RW6+d8 A, R6 +7 MULU A, R7 MULU A, @RW7+d8 MULUW MULUW A, MUL A, RW7 @RW7+d8 A, R7 +8 MULU MULU A, A, @RW0 @RW0+d16 MULUW MULUW A, MUL MUL A, A, @RW0 @RW0+d16 A, @RW0 @RW0+d16 +9 MULU A, @RW1 MULU A, @RW1+d16 MULUW MULUW A, MUL A, @RW1 @RW1+d16 A, @RW1 +A MULU A, @RW2 MULU A, @RW2+d16 MULUW MULUW A, MUL A, @RW2 @RW2+d16 A, @RW2 +B MULU A, @RW3 MULU A, @RW3+d16 MULUW MULUW A, MUL A, @RW3 @RW3+d16 A, @RW3 +C MULU MULU A, A, @RW0+ @RW0+RW7 MULUW MULUW A, MUL MUL A, A, @RW0+ @RW0+RW7 A, @RW0+ @RW0+RW7 Table B.9-14 ea instruction map (9) (1st byte = 78H) +D MULU MULU A, A, @RW1+ @RW1+RW7 MULUW MULUW A, MUL MUL A, A, @RW1+ @RW1+RW7 A, @RW1+ @RW1+RW7 +E MULU MULU A, A, @RW2+ @PC+d16 MULUW MULUW A, MUL MUL A, A, @RW2+ @PC+d16 A, @RW2+ @PC+d16 APPENDIX B INSTRUCTIONS +F MULU MULU A, A, @RW3+ addr16 MULUW MULUW A, MUL MUL A, A, @RW3+ addr16 A, @RW3+ addr16 537 538 20 MOVEA RW3, MOVEA @RW0+d8 RW4, RW0 MOVEA RW3, MOVEA @RW1+d8 RW4, RW1 MOVEA RW3, MOVEA @RW2+d8 RW4, RW2 MOVEA RW3, MOVEA @RW3+d8 RW4, RW3 MOVEA RW3, MOVEA @RW4+d8 RW4, RW4 MOVEA RW3, MOVEA @RW5+d8 RW4, RW5 MOVEA RW3, MOVEA @RW6+d8 RW4, RW6 MOVEA RW3, MOVEA @RW7+d8 RW4, RW7 MOVEA RW4, MOVEA @RW6+d8 RW5, RW6 MOVEA RW4, MOVEA @RW7+d8 RW5, RW7 MOVEA RW4, MOVEA @RW5+d8 RW5, RW5 MOVEA RW4, MOVEA @RW4+d8 RW5, RW4 MOVEA RW4, MOVEA @RW3+d8 RW5, RW3 MOVEA RW4, MOVEA @RW2+d8 RW5, RW2 MOVEA RW4, MOVEA @RW1+d8 RW5, RW1 MOVEA RW4, MOVEA @RW0+d8 RW5, RW0 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW0+d8 RW6, RW0 ,@RW0+d8 RW7, RW0 @RW0+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW1+d8 RW6, RW1 ,@RW1+d8 RW7, RW1 @RW1+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW2+d8 RW6, RW2 ,@RW2+d8 RW7, RW2 @RW2+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW3+d8 RW6, RW3 ,@RW3+d8 RW7, RW3 @RW3+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW4+d8 RW6, RW4 ,@RW4+d8 RW7, RW4 @RW4+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW5+d8 RW6, RW5 ,@RW5+d8 RW7, RW5 @RW5+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW6+d8 RW6, RW6 ,@RW6+d8 RW7, RW6 @RW6+d8 MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, @RW7+d8 RW6, RW7 ,@RW7+d8 RW7, RW7 @RW7+d8 00 10 +0 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA RW0, RW0 @RW0+d8 RW1, RW0 @RW0+d8 RW2, RW0 @RW0+d8 RW3, RW0 +1 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA RW0, RW1 @RW1+d8 RW1, RW1 @RW1+d8 RW2, RW1 @RW1+d8 RW3, RW1 APPENDIX B INSTRUCTIONS +2 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA RW0, RW2 @RW2+d8 RW1, RW2 @RW2+d8 RW2, RW2 @RW2+d8 RW3, RW2 +3 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA RW0, RW3 @RW3+d8 RW1, RW3 @RW3+d8 RW2, RW3 @RW3+d8 RW3, RW3 +4 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA RW0, RW4 @RW4+d8 RW1, RW4 @RW4+d8 RW2, RW4 @RW4+d8 RW3, RW4 +5 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA RW0, RW5 @RW5+d8 RW1, RW5 @RW5+d8 RW2, RW5 @RW5+d8 RW3, RW5 +6 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA RW0, RW6 @RW6+d8 RW1, RW6 @RW6+d8 RW2, RW6 @RW6+d8 RW3, RW6 +7 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA RW0, RW7 @RW7+d8 RW1, RW7 @RW7+d8 RW2, RW7 @RW7+d8 RW3, RW7 +8 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA RW3, MOVEA MOVEA RW4, MOVEA MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, RW0, @RW0 @RW0+d16 RW1, @RW0 @RW0+d16 RW2, @RW0 @RW0+d16 RW3, @RW0 @RW0+d16 RW4, @RW0 @RW0+d16 RW5, @RW0 @RW0+d16 RW6, @RW0 ,@RW0+d16 RW7, @RW0 @RW0+d16 +9 MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA RW3, MOVEA MOVEA RW4, MOVEA MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, RW0, @RW1 @RW1+d16 RW1, @RW1 @RW1+d16 RW2, @RW1 @RW1+d16 RW3, @RW1 @RW1+d16 RW4, @RW1 @RW1+d16 RW5, @RW1 @RW1+d16 RW6, @RW1 ,@RW1+d16 RW7, @RW1 @RW1+d16 +A MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA RW3, MOVEA MOVEA RW4, MOVEA MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, RW0, @RW2 @RW2+d16 RW1, @RW2 @RW2+d16 RW2, @RW2 @RW2+d16 RW3, @RW2 @RW2+d16 RW4, @RW2 @RW2+d16 RW5, @RW2 @RW2+d16 RW6, @RW2 ,@RW2+d16 RW7, @RW2 @RW2+d16 +B MOVEA MOVEA RW0, MOVEA MOVEA RW1, MOVEA MOVEA RW2, MOVEA MOVEA RW3, MOVEA MOVEA RW4, MOVEA MOVEA RW5, MOVEA MOVEA RW6 MOVEA MOVEA RW7, RW0, @RW3 @RW3+d16 RW1, @RW3 @RW3+d16 RW2, @RW3 @RW3+d16 RW3, @RW3 @RW3+d16 RW4, @RW3 @RW3+d16 RW5, @RW3 @RW3+d16 RW6, @RW3 ,@RW3+d16 RW7, @RW3 @RW3+d16 +C MOVEA R MOVEA RW0, MOVEA R MOVEA RW1, MOVEA R MOVEA RW2, MOVEA R MOVEA RW3, MOVEA R MOVEA RW4, MOVEA R MOVEA RW5, MOVEA R MOVEA RW6 MOVEA R MOVEA RW7, W0, @RW0+ @RW0+RW7 W1, @RW0+ @RW0+RW7 W2, @RW0+ @RW0+RW7 W3, @RW0+ @RW0+RW7 W4, @RW0+ @RW0+RW7 W5, @RW0+ @RW0+RW7 W6, @RW0+ ,@RW0+RW7 W7, @RW0+ @RW0+RW7 +D MOVEA R MOVEA RW0, MOVEA R MOVEA RW1, MOVEA R MOVEA RW2, MOVEA R MOVEA RW3, MOVEA R MOVEA RW4, MOVEA R MOVEA RW5, MOVEA R MOVEA RW6 MOVEA R MOVEA RW7, W0, @RW1+ @RW1+RW7 W1, @RW1+ @RW1+RW7 W2, @RW1+ @RW1+RW7 W3, @RW1+ @RW1+RW7 W4, @RW1+ @RW1+RW7 W5, @RW1+ @RW1+RW7 W6, @RW1+ ,@RW1+RW7 W7, @RW1+ @RW1+RW7 +E MOVEA R MOVEA RW0, MOVEA R MOVEA RW1, MOVEA R MOVEA RW2, MOVEA R MOVEA RW3, MOVEA R MOVEA RW4, MOVEA R MOVEA RW5, MOVEA R MOVEA RW6 MOVEA R MOVEA RW7, W0, @RW2+ @PC+d16 W1, @RW2+ @PC+d16 W2, @RW2+ @PC+d16 W3, @RW2+ @PC+d16 W4, @RW2+ @PC+d16 W5, @RW2+ @PC+d16 W6, @RW2+ ,@PC+d16 W7, @RW2+ @PC+d16 Table B.9-15 MOVEA RWi,ea instruction map (1st byte = 79H) +F MOVEA R MOVEA RW0, MOVEA R MOVEA RW1, MOVEA R MOVEA RW2, MOVEA R MOVEA RW3, MOVEA R MOVEA RW4, MOVEA R MOVEA RW5, MOVEA MOVEA RW6 MOVEA R MOVEA RW7, W0, @RW3+ addr16 W1, @RW3+ addr16 W2, @RW3+ addr16 W3, @RW3+ addr16 W4, @RW3+ addr16 W5, @RW3+ addr16 W6, @RW3+ ,addr16 W7, @RW3+ addr16 MB90560 series MB90560 series 20 MOV R1, @RW0+d8 MOV R5, @RW0+d8 MOV R5, @RW1+d8 MOV R5, @RW2+d8 MOV R5, @RW3+d8 MOV R5, @RW4+d8 MOV R5, @RW5+d8 MOV R5, @RW6+d8 MOV R5, @RW7+d8 MOV R5, @RW0+d16 MOV R4, MOV @RW1+d16 R5, @RW1 MOV R4, MOV @RW2+d16 R5, @RW2 MOV R4, MOV @RW3+d16 R5, @RW3 MOV R5, @RW1+d16 MOV R5, @RW2+d16 MOV R5, @RW3+d16 MOV R6, R1 MOV R6, R2 MOV R6, R3 MOV R6, R4 MOV R6, R5 MOV R6, R6 MOV R6, R7 MOV R6, @RW0 MOV R6, @RW1 MOV R6, @RW2 MOV R6, @RW3 MOV R1, @RW1+d8 MOV R1, @RW2+d8 MOV R1, @RW3+d8 MOV R1, @RW4+d8 MOV R1, @RW5+d8 MOV R1, @RW6+d8 MOV R1, @RW7+d8 MOV R2, MOV @RW0+d16 R3, @RW0 MOV R2, MOV @RW1+d16 R3, @RW1 MOV R3, MOV @RW1+d16 R4, @RW1 MOV R3, MOV @RW2+d16 R4, @RW2 MOV R3, MOV @RW3+d16 R4, @RW3 MOV R3, MOV @RW0+d16 R4, @RW0 MOV R2, R7 MOV R2, MOV R3, R7 @RW7+d8 MOV R3, MOV R4, R7 @RW7+d8 MOV R2, R6 MOV R2, MOV R3, R6 @RW6+d8 MOV R3, MOV R4, R6 @RW6+d8 MOV R2, R5 MOV R3, MOV R4, R5 @RW5+d8 MOV R2, MOV R3, R5 @RW5+d8 MOV R4, MOV R5, R5 @RW5+d8 MOV R4, MOV R5, R6 @RW6+d8 MOV R4, MOV R5, R7 @RW7+d8 MOV R4, MOV @RW0+d16 R5, @RW0 MOV R2, R4 MOV R3, MOV R4, R4 @RW4+d8 MOV R4, MOV R5, R4 @RW4+d8 MOV R2, MOV R3, R4 @RW4+d8 MOV R2, R3 MOV R2, MOV R3, R3 @RW3+d8 MOV R3, MOV R4, R3 @RW3+d8 MOV R4, MOV R5, R3 @RW3+d8 MOV R2, R2 MOV R2, MOV R3, R2 @RW2+d8 MOV R3, MOV R4, R2 @RW2+d8 MOV R4, MOV R5, R2 @RW2+d8 MOV R2, R1 MOV R2, MOV R3, R1 @RW1+d8 MOV R3, MOV R4, R1 @RW1+d8 MOV R4, MOV R5, R1 @RW1+d8 MOV R2, R0 MOV R2, MOV R3, R0 @RW0+d8 MOV R3, MOV R4, R0 @RW0+d8 MOV R4, MOV R5, R0 @RW0+d8 MOV R6, R0 30 40 50 60 70 80 90 A0 B0 C0 D0 MOV R6, @RW0+d8 MOV R6, @RW1+d8 MOV R6, @RW2+d8 MOV R6, @RW3+d8 MOV R6, @RW4+d8 MOV R6, @RW5+d8 MOV R6, @RW6+d8 MOV R6, @RW7+d8 E0 MOV R7, R0 MOV R7, R1 MOV R7, R2 MOV R7, R3 MOV R7, R4 MOV R7, R5 MOV R7, R6 MOV R7, R7 F0 MOV R7, @RW0+d8 MOV R7, @RW1+d8 MOV R7, @RW2+d8 MOV R7, @RW3+d8 MOV R7, @RW4+d8 MOV R7, @RW5+d8 MOV R7, @RW6+d8 MOV R7, @RW7+d8 MOV MOV R6, MOV R7, @RW0+d16 R7, @RW0 @RW0+d16 MOV R6, @RW1+d16 MOV R6, @RW2+d16 MOV R6, @RW3+d16 MOV R7, @RW1 MOV R7, @RW2 MOV R7, @RW3 MOV R7, @RW0+ MOV R7, @RW1+ MOV MOV R4, MOV MOV R5, R4, @RW2+ @PC+d16 R5, @RW2+ @PC+d16 MOV MOV R4, R4, @RW3+ addr16 MOV MOV R5, R5, @RW3+ addr16 MOV R6, @RW2+ MOV R6, @RW3+ MOV R6, @PC+d16 MOV R6, addr16 MOV R7, @RW2+ MOV R7, @RW3+ MOV R7, @RW1+d16 MOV R7, @RW2+d16 MOV R7, @RW3+d16 MOV R7, @RW0+RW7 MOV R7, @RW1+RW7 MOV R7, @PC+d16 MOV R7, addr16 MOV R2, @RW1 MOV MOV R2, MOV R2, @RW2 @RW2+d16 R3, @RW2 MOV MOV R2, MOV R2, @RW3 @RW3+d16 R3, @RW3 MOV MOV R2, R2, @RW2+ @PC+d16 MOV MOV R2, R2, @RW3+ addr16 MOV MOV R3, R3, @RW2+ @PC+d16 MOV MOV R3, R3, @RW3+ addr16 00 10 +0 MOV R0, R0 MOV R0, @RW0+d8 MOV R1, R0 +1 MOV R0, R1 MOV R0, MOV @RW1+d8 R1, R1 +2 MOV R0, R2 MOV R0, MOV @RW2+d8 R1, R2 +3 MOV R0, R3 MOV R0, MOV @RW3+d8 R1, R3 +4 MOV R0, R4 MOV R0, MOV @RW4+d8 R1, R4 +5 MOV R0, R5 MOV R0, MOV @RW5+d8 R1, R5 +6 MOV R0, R6 MOV R0, MOV @RW6+d8 R1, R6 +7 MOV R0, R7 MOV R0, MOV @RW7+d8 R1, R7 +8 MOV MOV R0, MOV MOV R1, MOV R0, @RW0 @RW0+d16 R1, @RW0 @RW0+d16 R2, @RW0 +9 MOV MOV R0, MOV MOV R1, R0, @RW1 @RW1+d16 R1, @RW1 @RW1+d16 +A MOV MOV R0, MOV MOV R1, R0, @RW2 @RW2+d16 R1, @RW2 @RW2+d16 +B MOV MOV R0, MOV MOV R1, R0, @RW3 @RW3+d16 R1, @RW3 @RW3+d16 +C MOV MOV R0, MOV R1, MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV R6, MOV R6, R0, @RW0+ @RW0+RW7 R1, @RW0+ @RW0+RW7 R2, @RW0+ @RW0+RW7 R3, @RW0+ @RW0+RW7 R4, @RW0+ @RW0+RW7 R5, @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 +D MOV MOV R0, MOV R1, MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV R6, MOV R6, R0, @RW1+ @RW1+RW7 R1, @RW1+ @RW1+RW7 R2, @RW1+ @RW1+RW7 R3, @RW1+ @RW1+RW7 R4, @RW1+ @RW1+RW7 R5, @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 +E MOV MOV R0, R0, @RW2+ @PC+d16 MOV R1, MOV R1, R1, @RW2+ @PC+d16 Table B.9-16 MOV Ri,ea instruction map (1st byte = 7AH) APPENDIX B INSTRUCTIONS +F MOV MOV R0, R0, @RW3+ @addr16 MOV R1, MOV R1, R1, @RW3+ addr16 539 540 20 MOVW RW2, MOVW @RW0+d8 RW3, RW0 MOVW RW2, MOVW @RW1+d8 RW3, RW1 MOVW RW2, MOVW @RW2+d8 RW3, RW2 MOVW RW2, MOVW @RW3+d8 RW3, RW3 MOVW RW2, MOVW @RW4+d8 RW3, RW4 MOVW RW2, MOVW @RW5+d8 RW3, RW5 MOVW RW2, MOVW @RW6+d8 RW3, RW6 MOVW RW2, MOVW @RW7+d8 RW3, RW7 MOVW RW3, MOVW @RW7+d8 RW4, RW7 MOVW RW4, MOVW @RW7+d8 RW5, RW7 MOVW RW3, MOVW @RW6+d8 RW4, RW6 MOVW RW4, MOVW @RW6+d8 RW5, RW6 MOVW RW3, MOVW @RW5+d8 RW4, RW5 MOVW RW4, MOVW @RW5+d8 RW5, RW5 MOVW RW3, MOVW @RW4+d8 RW4, RW4 MOVW RW4, MOVW @RW4+d8 RW5, RW4 MOVW RW3, MOVW @RW3+d8 RW4, RW3 MOVW RW4, MOVW @RW3+d8 RW5, RW3 MOVW RW3, MOVW @RW2+d8 RW4, RW2 MOVW RW4, MOVW @RW2+d8 RW5, RW2 MOVW RW3, MOVW @RW1+d8 RW4, RW1 MOVW RW4, MOVW @RW1+d8 RW5, RW1 MOVW RW3, MOVW @RW0+d8 RW4, RW0 MOVW RW4, MOVW @RW0+d8 RW5, RW0 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 MOVW RW7, @RW0+d8 MOVW RW7, @RW1+d8 MOVW RW7, @RW2+d8 MOVW RW7, @RW3+d8 MOVW RW7, @RW4+d8 MOVW RW7, @RW5+d8 MOVW RW7, @RW6+d8 MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, @RW7+d8 RW6, RW7 @RW7+d8 RW7, RW7 @RW7+d8 MOVW RW5, MOVW MOVW RW6, MOVW @RW0+d8 RW6, RW0 @RW0+d8 RW7, RW0 MOVW RW5, MOVW MOVW RW6, MOVW @RW1+d8 RW6, RW1 @RW1+d8 RW7, RW1 MOVW RW5, MOVW MOVW RW6, MOVW @RW2+d8 RW6, RW2 @RW2+d8 RW7, RW2 MOVW RW5, MOVW MOVW RW6, MOVW @RW3+d8 RW6, RW3 @RW3+d8 RW7, RW3 MOVW RW5, MOVW MOVW RW6, MOVW @RW4+d8 RW6, RW4 @RW4+d8 RW7, RW4 MOVW RW5, MOVW MOVW RW6, MOVW @RW5+d8 RW6, RW5 @RW5+d8 RW7, RW5 MOVW RW5, MOVW MOVW RW6, MOVW @RW6+d8 RW6, RW6 @RW6+d8 RW7, RW6 00 10 +0 MOVW MOVW RW0, MOVW MOVW RW1, MOVW RW0, RW0 @RW0+d8 RW1, RW0 @RW0+d8 RW2, RW0 +1 MOVW MOVW RW0, MOVW MOVW RW1, MOVW RW0, RW1 @RW1+d8 RW1, RW1 @RW1+d8 RW2, RW1 APPENDIX B INSTRUCTIONS +2 MOVW MOVW RW0, MOVW MOVW RW1, MOVW RW0, RW2 @RW2+d8 RW1, RW2 @RW2+d8 RW2, RW2 +3 MOVW MOVW RW0, MOVW MOVW RW1, MOVW RW0, RW3 @RW3+d8 RW1, RW3 @RW3+d8 RW2, RW3 +4 MOVW MOVW RW0, MOVW MOVW RW1, MOVW RW0, RW4 @RW4+d8 RW1, RW4 @RW4+d8 RW2, RW4 +5 MOVW MOVW RW0, MOVW MOVW RW1, MOVW RW0, RW5 @RW5+d8 RW1, RW5 @RW5+d8 RW2, RW5 +6 MOVW MOVW RW0, MOVW MOVW RW1, MOVW RW0, RW6 @RW6+d8 RW1, RW6 @RW6+d8 RW2, RW6 +7 MOVW MOVW RW0, MOVW MOVW RW1, MOVW RW0, RW7 @RW7+d8 RW1, RW7 @RW7+d8 RW2, RW7 +8 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0, @RW0 @RW0+d16 RW1, @RW0 @RW0+d16 RW2, @RW0 @RW0+d16 RW3, @RW0 @RW0+d16 RW4, @RW0 @RW0+d16 RW5, @RW0 @RW0+d16 RW6, @RW0 @RW0+d16 RW7, @RW0 @RW0+d16 +9 MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0, @RW1 @RW1+d16 RW1, @RW1 @RW1+d16 RW2, @RW1 @RW1+d16 RW3, @RW1 @RW1+d16 RW4, @RW1 @RW1+d16 RW5, @RW1 @RW1+d16 RW6, @RW1 @RW1+d16 RW7, @RW1 @RW1+d16 +A MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0, @RW2 @RW2+d16 RW1, @RW2 @RW2+d16 RW2, @RW2 @RW2+d16 RW3, @RW2 @RW2+d16 RW4, @RW2 @RW2+d16 RW5, @RW2 @RW2+d16 RW6, @RW2 @RW2+d16 RW7, @RW2 @RW2+d16 +B MOVW MOVW RW0, MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0, @RW3 @RW3+d16 RW1, @RW3 @RW3+d16 RW2, @RW3 @RW3+d16 RW3, @RW3 @RW3+d16 RW4, @RW3 @RW3+d16 RW5, @RW3 @RW3+d16 RW6, @RW3 @RW3+d16 RW7, @RW3 @RW3+d16 +C MOVW R MOVW RW0, MOVW R MOVW RW1, MOVW R MOVW RW2, MOVW R MOVW RW3, MOVW R MOVW RW4, MOVW R MOVW RW5, MOVW R MOVW RW6, MOVW R MOVW RW7, W0, @RW0+ @RW0+RW7 W1, @RW0+ @RW0+RW7 W2, @RW0+ @RW0+RW7 W3, @RW0+ @RW0+RW7 W4, @RW0+ @RW0+RW7 W5, @RW0+ @RW0+RW7 W6, @RW0+ @RW0+RW7 W7, @RW0+ @RW0+RW7 +D MOVW R MOVW RW0, MOVW R MOVW RW1, MOVW R MOVW RW2, MOVW R MOVW RW3, MOVW R MOVW RW4, MOVW R MOVW RW5, MOVW R MOVW RW6, MOVW R MOVW RW7, W0, @RW1+ @RW1+RW7 W1, @RW1+ @RW1+RW7 W2, @RW1+ @RW1+RW7 W3, @RW1+ @RW1+RW7 W4, @RW1+ @RW1+RW7 W5, @RW1+ @RW1+RW7 W6, @RW1+ @RW1+RW7 W7, @RW1+ @RW1+RW7 +E MOVW R MOVW RW0, MOVW R MOVW RW1, MOVW R MOVW RW2, MOVW R MOVW RW3, MOVW R MOVW RW4, MOVW R MOVW RW5, MOVW R MOVW RW6, MOVW R MOVW RW7, W0, @RW2+ @PC+d16 W1, @RW2+ @PC+d16 W2, @RW2+ @PC+d16 W3, @RW2+ @PC+d16 W4, @RW2+ @PC+d16 W5, @RW2+ @PC+d16 W6, @RW2+ @PC+d16 W7, @RW2+ @PC+d16 Table B.9-17 MOVW RWi,ea instruction map (1st byte = 7BH) +F MOVW R MOVW RW0, MOVW R MOVW RW1, MOVW R MOVW RW2, MOVW R MOVW RW3, MOVW R MOVW RW4, MOVW R MOVW RW5, MOVW R MOVW RW6, MOVW R MOVW RW7, W0, @RW3+ addr16 W1, @RW3+ addr16 W2, @RW3+ addr16 W3, @RW3+ addr16 W4, @RW3+ addr16 W5, @RW3+ addr16 W6, @RW3+ addr16 W7, @RW3+ addr16 MB90560 series MB90560 series 20 MOV @R MOV W0+d8, R1 R0, R2 MOV @R, MOV R0, R3 W0+d8, R2 MOV @R MOV R0, R4 W0+d8, R3 MOV @R W0+d8, R4 MOV @R W0+d8, R5 MOV @R W1+d8, R5 MOV @R W2+d8, R5 MOV @R W3+d8, R5 MOV @R W4+d8, R5 MOV @R W5+d8, R5 MOV @R W6+d8, R5 MOV R7, R5 MOV @R W7+d8, R5 MOV R1, R6 MOV R2, R6 MOV R3, R6 MOV R4, R6 MOV R5, R6 MOV R6, R6 MOV R7, R6 MOV @R W1+d8, R4 MOV @R, W2+d8, R4 MOV @R, W3+d8, R4 MOV @R W4+d8, R4 MOV @R W5+d8, R4 MOV @R W6+d8, R4 MOV @R W7+d8, R4 MOV R5, R5 MOV R6, R5 MOV R4, R5 MOV R3, R5 MOV R2, R5 MOV R1, R5 MOV R0, R5 MOV R0, R6 MOV @R MOV R1, R4 W1+d8, R3 MOV @R W2+d8, R3 MOV @R MOV R3, R4 W3+d8, R3 MOV @R MOV R4, R4 W4+d8, R3 MOV @R MOV R5, R4 W5+d8, R3 MOV @R MOV R6, R4 W6+d8, R3 MOV @R MOV R7, R4 W7+d8, R3 MOV R2, R4 MOV @R MOV R1, R3 W1+d8, R2 MOV @R MOV R2, R3 W2+d8, R2 MOV @R MOV R3, R3 W3+d8, R2 MOV @R MOV R4, R3 W4+d8, R2 MOV @R MOV R5, R3 W5+d8, R2 MOV @R MOV R6, R3 W6+d8, R2 MOV @R MOV R7, R3 W7+d8, R2 MOV @RW MOV MOV @RW MOV @RW0, R3 @RW0, R4 0+d16, R2 0+d16, R3 MOV @RW MOV MOV @RW MOV @RW1, R3 1+d16, R3 @RW1, R4 1+d16, R2 MOV @RW MOV MOV @RW MOV @RW2, R3 2+d16, R3 @RW2, R4 2+d16, R2 MOV @RW MOV MOV @RW MOV @RW3, R3 3+d16, R3 @RW3, R4 3+d16, R2 MOV @R MOV W1+d8, R1 R1, R2 MOV @R MOV W2+d8, R1 R2, R2 MOV @R MOV W3+d8, R1 R3, R2 MOV @R MOV W4+d8, R1 R4, R2 MOV @R MOV W5+d8, R1 R5, R2 MOV @R MOV W6+d8, R1 R6, R2 MOV @R MOV W7+d8, R1 R7, R2 MOV @RW MOV 0+d16, R1 @RW0, R2 MOV @RW MOV 1+d16, R1 @RW1, R2 MOV @RW MOV 2+d16, R1 @RW2, R2 MOV @RW MOV 3+d16, R1 @RW3, R2 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 MOV @R MOV R0, R7 W0+d8, R6 MOV @R MOV R1, R7 W1+d8, R6 MOV @R MOV R2, R7 W2+d8, R6 MOV @R MOV R3, R7 W3+d8, R6 MOV @R MOV R4, R7 W4+d8, R6 MOV @R MOV R5, R7 W5+d8, R6 MOV @R MOV R6, R7 W6+d8, R6 MOV @R MOV R7, R7 W7+d8, R6 F0 MOV @R W0+d8, R7 MOV @R W1+d8, R7 MOV @R W2+d8, R7 MOV @R W3+d8, R7 MOV @R W4+d8, R7 MOV @R W5+d8, R7 MOV @R W6+d8, R7 MOV @R W7+d8, R7 MOV @RW MOV MOV @RW @RW0, R7 0+d16, R6 0+d16, R7 MOV @RW MOV @RW1, R5 1+d16, R4 MOV @RW MOV @RW2, R5 2+d16, R4 MOV @RW MOV @RW3, R5 3+d16, R4 MOV @RW MOV @RW1, R6 1+d16, R5 MOV @RW MOV @RW2, R6 2+d16, R5 MOV @RW MOV @RW3, R6 3+d16, R5 MOV @RW MOV @RW1, R7 1+d16, R6 MOV @RW MOV @RW2, R7 2+d16, R6 MOV @RW MOV @RW3, R7 3+d16, R6 MOV @RW 1+d16, R7 MOV @RW 2+d16, R7 MOV @RW 3+d16, R7 MOV @RW MOV MOV @RW MOV @RW0, R5 0+d16, R5 @RW0, R6 0+d16, R4 MOV MOV @RW2+, R2 PC+d16, R2 MOV MOV @RW2+, R3 PC+d16, R3 MOV MOV @RW3+, R3 addr16, R3 MOV MOV @RW2+, R4 PC+d16, R4 MOV MOV @RW2+, R5 PC+d16, R5 MOV MOV MOV MOV @RW3+, R4 addr16, R4 @RW3+, R5 addr16, R5 MOV MOV @RW2+, R6 PC+d16, R6 MOV MOV @RW3+, R6 addr16, R6 MOV MOV @RW2+, R7 PC+d16, R7 MOV MOV @RW3+, R7 addr16, R7 00 10 +0 MOV R0, R0 MOV @R W0+d8, R0 MOV R0, R1 +1 MOV R1, R0 MOV @R W1+d8, R0 MOV R1, R1 +2 MOV R2, R0 MOV @R W2+d8, R0 MOV R2, R1 +3 MOV R3, R0 MOV @R W3+d8, R0 MOV R3, R1 +4 MOV R4, R0 MOV @R W4+d8, R0 MOV R4, R1 +5 MOV R5, R0 MOV @R W5+d8, R0 MOV R5, R1 +6 MOV R6, R0 MOV @R W6+d8, R0 MOV R6, R1 +7 MOV R7, R0 MOV @R W7+d8, R0 MOV R7, R1 +8 MOV MOV @RW MOV @RW0, R0 W0+d16, R0 @RW0, R1 +9 MOV MOV @RW MOV @RW1, R0 W1+d16, R0 @RW1, R1 +A MOV MOV @RW MOV @RW2, R0 W2+d16, R0 @RW2, R1 +B MOV MOV @RW MOV @RW3, R0 W3+d16, R0 @RW3, R1 +C MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW @RW0+, R0 W0+RW7, R0 @RW0+, R1 @RW0+, R3 0+RW7, R3 @RW0+, R4 0+RW7, R4 @RW0+, R5 0+RW7, R5 @RW0+, R6 0+RW7, R6 @RW0+, R7 0+RW7, R7 0+RW7, R1 @RW0+, R2 0+RW7, R2 +D MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW MOV MOV @RW @RW1+, R0 W1+RW7, R0 @RW1+, R1 @RW1+, R3 1+RW7, R3 @RW1+, R4 1+RW7, R4 @RW1+, R5 1+RW7, R5 @RW1+, R6 1+RW7,R6 @RW1+, R7 1+RW7, R7 1+RW7, R1 @RW1+, R2 1+RW7, R2 +E MOV MOV @RW2+, R0 PC+d16, R0 MOV MOV @RW2+, R1 PC+d16, R1 Table B.9-18 MOV ea,Ri instruction map (1st byte = 7CH) APPENDIX B INSTRUCTIONS +F MOV MOV MOV MOV MOV MOV @RW3+, R0 addr16, R0 @RW3+, R1 addr16, R1 @RW3+, R2 addr16, R2 541 542 20 MOVW @RW MOVW RW0, RW2 0+d8, RW1 MOVW @R 1+d8, RW1 MOVW @RW MOVW RW2, RW2 2+d8, RW1 MOVW @RW MOVW RW3, RW2 3+d8, RW1 MOVW @RW MOVW RW4, RW2 4+d8, RW1 MOVW @RW MOVW RW5, RW2 5+d8, RW1 MOVW @RW MOVW RW6, RW2 6+d8, RW1 MOVW @RW MOVW RW7, RW2 7+d8, RW1 MOVW @RW MOVW RW7, RW3 7+d8, RW2 MOVW @RW MOVW RW7, RW4 7+d8, RW3 MOVW @RW MOVW RW6, RW3 6+d8, RW2 MOVW @RW MOVW RW6, RW4 6+d8, RW3 MOVW @RW MOVW RW6, RW5 6+d8, RW4 MOVW @RW MOVW RW7, RW5 7+d8, RW4 MOVW @RW MOVW RW5, RW3 5+d8, RW2 MOVW @RW MOVW RW5, RW4 5+d8, RW3 MOVW @RW MOVW RW5, RW5 5+d8, RW4 MOVW @RW MOVW RW4, RW3 4+d8, RW2 MOVW @RW MOVW RW4, RW4 4+d8, RW3 MOVW @RW MOVW RW4, RW5 4+d8, RW4 MOVW @RW MOVW RW3, RW3 3+d8, RW2 MOVW @RW MOVW RW3, RW4 3+d8, RW3 MOVW @RW MOVW RW3, RW5 3+d8, RW4 MOVW @RW MOVW RW2, RW3 2+d8, RW2 MOVW @RW MOVW RW2, RW4 2+d8, RW3 MOVW @RW MOVW RW2, RW5 2+d8, RW4 MOVW @RW MOVW RW2, RW6 2+d8, RW5 MOVW @RW MOVW RW3, RW6 3+d8, RW5 MOVW @RW MOVW RW4, RW6 4+d8, RW5 MOVW @RW MOVW RW5, RW6 5+d8, RW5 MOVW @RW MOVW RW6, RW6 6+d8, RW5 MOVW @RW MOVW RW7, RW6 7+d8, RW5 MOVW RW1, RW2 MOVW @R 1+d8, RW2 MOVW RW1, RW3 MOVW @RW MOVW RW1, RW4 1+d8, RW3 MOVW @RW MOVW RW1, RW5 1+d8, RW4 MOVW @RW MOVW RW1, RW6 1+d8, RW5 MOVW @RW MOVW RW0, RW3 0+d8, RW2 MOVW @RW MOVW RW0, RW4 0+d8, RW3 MOVW @RW MOVW RW0, RW5 0+d8, RW4 MOVW @RW MOVW RW0, RW6 0+d8, RW5 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 MOVW @RW 0+d8, RW7 MOVW @RW 1+d8, RW7 MOVW @RW MOVW RW1, RW7 1+d8, RW6 MOVW @RW MOVW RW2, RW7 2+d8, RW6 MOVW @RW MOVW RW3, RW7 3+d8, RW6 MOVW @RW MOVW RW4, RW7 4+d8, RW6 MOVW @RW MOVW RW5, RW7 5+d8, RW6 MOVW @RW MOVW RW6, RW7 6+d8, RW6 MOVW @RW MOVW RW7, RW7 7+d8, RW6 MOVW @RW 2+d8, RW7 MOVW @RW 3+d8, RW7 MOVW @RW 4+d8, RW7 MOVW @RW 5+d8, RW7 MOVW @RW 6+d8, RW7 MOVW @RW 7+d8, RW7 MOVW@RW0 MOVW @RW0, RW7 +d16, RW7 MOVW@RW1 MOVW @RW1, RW7 +d16, RW7 MOVW@RW2 MOVW @RW2, RW7 +d16, RW7 MOVW@RW3 MOVW @RW3, RW7 +d16, RW7 MOVW @ MOVW@RW0 +RW7, RW7 RW0+, RW7 MOVW @ MOVW@RW1 +RW7, RW7 RW1+, RW7 MOVW @RW MOVW RW0, RW7 0+d8, RW6 00 10 +0 MOVW RW0, RW0 MOVW @RW MOVW RW0, RW1 0+d8, RW0 +1 MOVW RW1, RW0 MOVW @RW MOVW RW1, RW1 1+d8, RW0 APPENDIX B INSTRUCTIONS +2 MOVW RW2, RW0 MOVW @RW MOVW RW2, RW1 2+d8, RW0 +3 MOVW RW3, RW0 MOVW @RW MOVW RW3, RW1 3+d8, RW0 +4 MOVW RW4, RW0 MOVW @RW MOVW RW4, RW1 4+d8, RW0 +5 MOVW RW5, RW0 MOVW @RW MOVW RW5, RW1 5+d8, RW0 +6 MOVW RW6, RW0 MOVW @RW MOVW RW6, RW1 6+d8, RW0 +7 MOVW RW7, RW0 MOVW @RW MOVW RW7, RW1 7+d8, RW0 +8 MOVW@RW0 MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW @RW0, RW6 +d16, RW6 @RW0, RW5 +d16, RW5 @RW0, RW4 +d16, RW4 @RW0, RW3 +d16, RW3 @RW0, RW2 +d16, RW2 @RW0, RW1 +d16, RW1 @RW0, RW0 +d16, RW0 +9 MOVW@RW1 MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW @RW1, RW6 +d16, RW6 @RW1, RW5 +d16, RW5 @RW1, RW4 +d16, RW4 @RW1, RW3 +d16, RW3 @RW1, RW2 +d16, RW2 @RW1, RW1 +d16, RW1 @RW1, RW0 +d16, RW0 +A MOVW@RW2 MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW@RW2 MOVW MOVW @RW2, RW6 +d16, RW6 @RW2, RW5 +d16, RW5 @RW2, RW4 +d16, RW4 @RW2, RW3 +d16, RW3 @RW2, RW2 +d16, RW2 @RW2, RW1 +d16, RW1 @RW2, RW0 +d16, RW0 +B MOVW@RW3 MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW@RW3 MOVW MOVW @RW3, RW6 +d16, RW6 @RW3, RW5 +d16, RW5 @RW3, RW4 +d16, RW4 @RW3, RW3 +d16, RW3 @RW3, RW2 +d16, RW2 @RW3, RW1 +d16, RW1 @RW3, RW0 +d16, RW0 +C @ MOVW@RW0 @ MOVW@RW0 MOVW @ MOVW@RW0 MOVW @ MOVW@RW0 MOVW @ MOVW@RW0 MOVW @ MOVW@RW0 MOVW MOVW@RW0 MOVW MOVW +RW7, RW6 RW0+, RW6 +RW7, RW5 RW0+, RW5 +RW7, RW4 RW0+, RW4 +RW7, RW3 RW0+, RW3 +RW7, RW2 RW0+, RW2 +RW7, RW0 RW0+, RW1 +RW7, RW1 @RW0+, RW0 +D @ MOVW@RW1 @ MOVW@RW1 MOVW @ MOVW@RW1 MOVW @ MOVW@RW1 MOVW @ MOVW@RW1 MOVW @ MOVW@RW1 MOVW MOVW@RW1 MOVW MOVW +RW7, RW6 RW1+, RW6 +RW7, RW5 RW1+, RW5 +RW7, RW4 RW1+, RW4 +RW7, RW3 RW1+, RW3 +RW7, RW2 RW1+, RW2 RW1+, RW1 +RW7, RW1 @RW1+, RW0 +RW7, RW0 +E @ MOVW @PC+ @ MOVW @PC+ MOVW @ MOVW @PC+ MOVW @ MOVW @PC+ MOVW @ MOVW @PC+ MOVW @ MOVW @PC+ MOVW @ MOVW @PC+ MOVW MOVW @PC+ MOVW MOVW d16, RW7 d16, RW6 RW2+, RW7 d16, RW5 RW2+, RW6 d16, RW4 RW2+, RW5 d16, RW3 RW2+, RW4 d16, RW2 RW2+, RW3 d16, RW1 RW2+, RW2 RW2+, RW1 d16, RW0 @RW2+, RW0 Table B.9-19 MOVW ea,Rwi instruction map (1st byte = 7DH) +F MOVW @ MOVW addr MOVW @ MOVW addr MOVW @ MOVW addr MOVW @ MOVW addr MOVW @ MOVW addr MOVW @ MOVW addr MOVW @ MOVW addr MOVW addr MOVW 16, RW7 16, RW6 RW3+, RW7 16, RW5 RW3+, RW6 16, RW4 RW3+, RW5 16, RW3 RW3+, RW4 16, RW2 RW3+, RW3 16, RW1 RW3+, RW2 16, RW0 RW3+, RW1 @RW3+, RW0 MB90560 series MB90560 series 20 XCH XCH R2, R1 XCH R2, R2 XCH R2, R3 XCH R2, R4 XCH R2, R5 XCH R2, R6 XCH R2, R7 R1, R0 XCH R1, @RW0+d8 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R2, R0 R3, R0 R4, R0 R5, R0 @RW0+d8 R6, R0 @RW0+d8 R7, R0 @RW0+d8 @RW0+d8 @RW0+d8 @RW0+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH NOTW R7, R3, R1 R4, R1 R5, R1 @RW1+d8 R6, R1 @RW1+d8 R7, R1 @RW1+d8 @RW1+d8 @RW1+d8 @RW1+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, R2 R4, R2 R5, R2 @RW2+d8 R6, R2 @RW2+d8 R7, R2 @RW2+d8 @RW2+d8 @RW2+d8 @RW2+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH NOTW R7, R3, R3 R4, R3 R5, R3 @RW3+d8 R6, R3 @RW3+d8 R7, R3 @RW3+d8 @RW3+d8 @RW3+d8 @RW3+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH NOTW R7, R3, R4 R4, R4 R5, R4 @RW4+d8 R6, R4 @RW4+d8 R7, R4 @RW4+d8 @RW4+d8 @RW4+d8 @RW4+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, R5 R4, R5 R5, R5 @RW5+d8 R6, R5 @RW5+d8 R7, R5 @RW5+d8 @RW5+d8 @RW5+d8 @RW5+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, R6 R4, R6 R5, R6 @RW6+d8 R6, R6 @RW6+d8 R7, R6 @RW6+d8 @RW6+d8 @RW6+d8 @RW6+d8 XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, R7 R4, R7 R5, R7 @RW7+d8 R6, R7 @RW7+d8 R7, R7 @RW7+d8 @RW7+d8 @RW7+d8 @RW7+d8 XCH R5, XCH XCH R6, XCH XCH R7, R6, @RW0 @RW0+d16 R7, @RW0 @RW0+d16 @RW0+d16 XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R2, @RW1 @RW1+d16 R3, @RW1 @RW1+d16 R4, @RW1 @RW1+d16 R5, @RW1 @RW1+d16 R6, @RW1 @RW1+d16 R7, @RW1 @RW1+d16 XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R2, @RW2 @RW2+d16 R3, @RW2 @RW2+d16 R4, @RW2 @RW2+d16 R5, @RW2 @RW2+d16 R6, @RW2 @RW2+d16 R7, @RW2 @RW2+d16 XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R2, @RW3 @RW3+d16 R3, @RW3 @RW3+d16 R4, @RW3 @RW3+d16 R5, @RW3 @RW3+d16 R6, @RW3 @RW3+d16 R7, @RW3 @RW3+d16 00 10 +0 XCH XCH R0, R0 XCH R0, @RW0+d8 +1 XCH XCH R0, XCH XCH R1, R0, R1 @RW1+d8 R1, R1 @RW1+d8 +2 XCH R0, R2 XCH R0, XCH XCH R1, @RW2+d8 R1, R2 @RW2+d8 +3 XCH R0, R3 XCH R0, XCH XCH R1, @RW3+d8 R1, R3 @RW3+d8 +4 XCH R0, R4 XCH R0, XCH XCH R1, @RW4+d8 R1, R4 @RW4+d8 +5 XCH R0, R5 XCH R0, XCH XCH R1, @RW5+d8 R1, R5 @RW5+d8 +6 XCH R0, R6 XCH R0, XCH XCH R1, @RW6+d8 R1, R6 @RW6+d8 +7 XCH R0, R7 XCH R0, XCH XCH R1, @RW7+d8 R1, R7 @RW7+d8 +8 XCH R0, @RW0 XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH @RW0+d16 R1, @RW0 @RW0+d16 R2, @RW0 @RW0+d16 R3, @RW0 @RW0+d16 R4, @RW0 @RW0+d16 R5, @RW0 +9 XCH R0, @RW1 XCH R0, XCH XCH R1, @RW1+d16 R1, @RW1 @RW1+d16 +A XCH R0, @RW2 XCH R0, XCH XCH R1, @RW2+d16 R1, @RW2 @RW2+d16 +B XCH R0, @RW3 XCH R0, XCH XCH R1, @RW3+d16 R1, @RW3 @RW3+d16 +C XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, @RW0+ @RW0+RW7 R1, @RW0+ @RW0+RW7 R2, @RW0+ @RW0+RW7 R3, @RW0+ @RW0+RW7 R4, @RW0+ @RW0+RW7 R5, @RW0+ @RW0+RW7 R6, @RW0+ @RW0+RW7 R7, @RW0+ @RW0+RW7 +D XCH XCH R2, R2, @RW2+ @PC+d16 XCH XCH R2, R2, @RW3+ addr16 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, @RW1+ @RW1+RW7 R1, @RW1+ @RW1+RW7 R2, @RW1+ @RW1+RW7 R3, @RW1+ @RW1+RW7 R4, @RW1+ @RW1+RW7 R5, @RW1+ @RW1+RW7 R6, @RW1+ @RW1+RW7 R7, @RW1+ @RW1+RW7 XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, @RW2+ @PC+d16 R4, @RW2+ R6, @RW2+ @PC+d16 R7, @RW2+ @PC+d16 @PC+d16 R5, @RW2+ @PC+d16 XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R3, @RW3+ addr16 R4, @RW3+ R5, @RW3+ addr16 R6, @RW3+ addr16 R7, @RW3+ addr16 addr16 Table B.9-20 XCH Ri,ea instruction map (1st byte = 7EH) +E XCH XCH R0, R0, @RW2+ @PC+d16 XCH XCH R1, R1, @RW2+ @PC+d16 APPENDIX B INSTRUCTIONS +F XCH XCH R0, R0, @RW3+ addr16 XCH XCH R1, R1, @RW3+ addr16 543 544 20 XCHW RW2, XCHW @RW0+d8 RW3, RW0 XCHW RW3, XCHW @RW0+d8 RW4, RW0 XCHW RW4, XCHW RW5, RW0 @RW0+d8 XCHW RW4, XCHW RW5, RW1 @RW1+d8 XCHW RW4, XCHW RW5, RW2 @RW2+d8 XCHW RW4, XCHW RW5, RW3 @RW3+d8 XCHW RW4, XCHW RW5, RW4 @RW4+d8 XCHW RW4, XCHW RW5, RW5 @RW5+d8 XCHW RW4, XCHW RW5, RW6 @RW6+d8 XCHW RW4, XCHW RW5, RW7 @RW7+d8 XCHW RW3, XCHW @RW1+d8 RW4, RW1 XCHW RW3, XCHW @RW2+d8 RW4, RW2 XCHW RW3, XCHW @RW3+d8 RW4, RW3 XCHW RW3, XCHW @RW4+d8 RW4, RW4 XCHW RW3, XCHW @RW5+d8 RW4, RW5 XCHW RW3, XCHW @RW6+d8 RW4, RW6 XCHW RW3, XCHW @RW7+d8 RW4, RW7 XCHW RW2, XCHW @RW1+d8 RW3, RW1 XCHW RW2, XCHW @RW2+d8 RW3, RW2 XCHW RW2, XCHW @RW3+d8 RW3, RW3 XCHW RW2, XCHW @RW4+d8 RW3, RW4 XCHW RW2, XCHW @RW5+d8 RW3, RW5 XCHW RW2, XCHW @RW6+d8 RW3, RW6 XCHW RW2, XCHW @RW7+d8 RW3, RW7 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW6, RW0 @RW0+d8 RW7, RW0 @RW0+d8 @RW0+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW6, RW1 RW7, RW1 @RW1+d8 @RW1+d8 @RW1+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW6, RW2 RW7, RW2 @RW2+d8 @RW2+d8 @RW2+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW6, RW3 RW7, RW3 @RW3+d8 @RW3+d8 @RW3+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW6, RW4 RW7, RW4 @RW4+d8 @RW4+d8 @RW4+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW6, RW5 RW7, RW5 @RW5+d8 @RW5+d8 @RW5+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW6, RW6 RW7, RW6 @RW6+d8 @RW6+d8 @RW6+d8 XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW6, RW7 RW7, RW7 @RW7+d8 @RW7+d8 @RW7+d8 00 10 +0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW0 @RW0+d8 RW1, RW0 @RW0+d8 RW2, RW0 +1 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW1 @RW1+d8 RW1, RW1 @RW1+d8 RW2, RW1 APPENDIX B INSTRUCTIONS +2 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW2 @RW2+d8 RW1, RW2 @RW2+d8 RW2, RW2 +3 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW3 @RW3+d8 RW1, RW3 @RW3+d8 RW2, RW3 +4 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW4 @RW4+d8 RW1, RW4 @RW4+d8 RW2, RW4 +5 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW5 @RW5+d8 RW1, RW5 @RW5+d8 RW2, RW5 +6 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW6 @RW6+d8 RW1, RW6 @RW6+d8 RW2, RW6 +7 XCHW XCHW RW0, XCHW XCHW RW1, XCHW RW0, RW7 @RW7+d8 RW1, RW7 @RW7+d8 RW2, RW7 +8 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, @RW0 @RW0+d16 RW1, @RW0 @RW0+d16 RW2, @RW0 @RW0+d16 RW3, @RW0 @RW0+d16 RW4, @RW0 @RW0+d16 RW5, @RW0 @RW0+d16 RW6, @RW0 @RW0+d16 RW7, @RW0 @RW0+d16 +9 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, @RW1 @RW1+d16 RW1, @RW1 @RW1+d16 RW2, @RW1 @RW1+d16 RW3, @RW1 @RW1+d16 RW4, @RW1 @RW1+d16 RW5, @RW1 @RW1+d16 RW6, @RW1 @RW1+d16 RW7, @RW1 @RW1+d16 +A XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, @RW2 @RW2+d16 RW1, @RW2 @RW2+d16 RW2, @RW2 @RW2+d16 RW3, @RW2 @RW2+d16 RW4, @RW2 @RW2+d16 RW5, @RW2 @RW2+d16 RW6, @RW2 @RW2+d16 RW7, @RW2 @RW2+d16 +B XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, @RW3 @RW3+d16 RW1, @RW3 @RW3+d16 RW2, @RW3 @RW3+d16 RW3, @RW3 @RW3+d16 RW4, @RW3 @RW3+d16 RW5, @RW3 @RW3+d16 RW6, @RW3 @RW3+d16 RW7, @RW3 @RW3+d16 +C XCHW R XCHW RW0, XCHW R XCHW RW1, XCHW R XCHW RW2, XCHW R XCHW RW3, XCHW R XCHW RW4, XCHW R XCHW RW5, XCHW R XCHW RW6, XCHW R XCHW RW7, W0, @RW0+ @RW0+RW7 W1, @RW0+ @RW0+RW7 W2, @RW0+ @RW0+RW7 W3, @RW0+ @RW0+RW7 W4, @RW0+ @RW0+RW7 W5, @RW0+ @RW0+RW7 W6, @RW0+ @RW0+RW7 W7, @RW0+ @RW0+RW7 +D XCHW R XCHW RW0, XCHW R XCHW RW1, XCHW R XCHW RW2, XCHW R XCHW RW3, XCHW R XCHW RW4, XCHW R XCHW RW5, XCHW R XCHW RW6, XCHW R XCHW RW7, W0, @RW1+ @RW1+RW7 W1, @RW1+ @RW1+RW7 W2, @RW1+ @RW1+RW7 W3, @RW1+ @RW1+RW7 W4, @RW1+ @RW1+RW7 W5, @RW1+ @RW1+RW7 W6, @RW1+ @RW1+RW7 W7, @RW1+ @RW1+RW7 +E XCHW R XCHW RW0, XCHW R XCHW RW1, XCHW R XCHW RW2, XCHW R XCHW RW3, XCHW R XCHW RW4, XCHW R XCHW RW5, XCHW R XCHW RW6, XCHW R XCHW RW7, W0, @RW2+ @PC +d16 W1, @RW2+ @PC+d16 W2, @RW2+ @PC+d16 W3, @RW2+ @PC+d16 W4, @RW2+ W6, @RW2+ @PC+d16 W7, @RW2+ @PC+d16 @PC+d16 W5, @RW2+ @PC+d16 Table B.9-21 XCHW RWi,ea instruction map (1st byte = 7FH) +F XCHW R XCHW RW0, XCHW R XCHW RW1, XCHW R XCHW RW2, XCHW R XCHW RW3, XCHW R XCHW RW4, XCHW R XCHW RW5, XCHW R XCHW RW6, XCHW R XCHW RW7, W0, @RW3+ addr16 W1, @RW3+ W2, @RW3+ W3, @RW3+ W4, @RW3+ W5, @RW3+ W6, @RW3+ W7, @RW3+ addr16 addr16 addr16 addr16 addr16 addr16 addr16 MB90560 series APPENDIX C 512K-BIT FLASH MEMORY The 512K-bit flash memory features the following: * Sector configuration of 64K words x 8 bits/32K words x 16 bits (16K + 512 x 2 + 7K + 8K + 32K) * Automatic programming algorithm (Embedded Algorithm: Same as MBM29F400TA) * Erase fault/erase restart function * Detecting the completion of write/erase by data polling or using toggle bits * Detecting the completion of write/erase using the RY and BY pins * Detecting the completion of write/erase using a CPU interrupt * Compatible with JEDEC standard commands * Erasable in units of sectors (free combination of sectors) * A minimum of 100 write/erase operations Embedded Algorithm is a trademark of Advanced Micro Device Corporation. s Sector Configuration Figure C-1 shows the sector configuration of the 512K-bit flash memory. When the memory is accessed from the CPU, SA0 to SA5 are seen in the FF bank. Writer address 7FFFF h CPU address FFFFFFh FFBFFFh FFBDFFh FFBBFFh FF9FFFh FF7FFFh FF0000h SA5 (16K bytes) 7BFFF h SA4 (512 bytes) SA3 (512 bytes) SA2 (7K bytes) SA1 (8K bytes) SA0 (32K bytes) 7BDFF h 7BBFF h 79FFF h 77FFF h 70000 h Figure C-1 Sector configuration of 512K-bit flash memory s Flash Memory Mode When the mode pins are set to "111" for resetting, the CPU is shut down. When this occurs, the function of the flash memory interface circuit connects the signals from ports 0, 1, 2, 3, and 4 directly to the control signals of flash memory and enables flash memory to be directly controlled from external pins. This mode gives an image where flash memory appears as a single unit on the external pins. The mode is mainly used when data is written or erased using the flash memory writer. In this mode, every operation of the automatic algorithm for the 512K-bit flash memory can be used. s Normal Mode Normal mode is specified when the mode pins are set for other than flash memory mode. The settings for use prohibition are excluded, though. The 1M-bit flash memory is allocated in the FE and FF banks on the CPU memory map, so the function of the flash memory interface circuit enables read access or program access from the CPU in the same way as with normal mask ROM. In this mode, the 512K-bit flash memory can also be written or erased by an instruction from the CPU via the flash memory interface circuit. This function enables rewriting in the installed state under control of the internal CPU. In this mode, normal writing and erasing can be performed but selector operation such as for enable sector protection cannot be performed. s Control Signals of 512K-Bit Flash Memory Table C.1 lists the flash memory control signals used in normal mode and flash memory mode. q Flash memory mode In this mode, external data bus width is limited to 8 bits and therefore only byte access is enabled. D15 to D08 are not used. Be sure to set the BYTEX pin to "0". q Normal mode Signals other than the reset signal are under control of the flash memory interface circuit. The data bus of flash memory is connected to the internal bus via the flash memory interface circuit. Selecting between byte and word access makes no sense. Therefore, the BYTEX signal of flash memory is internally fixed to 1 in this mode. Table C-1 Correspondence between external control pins and flash memory control signals External control pin RSTX P36 P34 P33 P32 P31 P30 P63, P46~ P40 P27~ P20 P07~ P00 MD2 ~MD0 Flash memory mode pin RSTX BYTEX Vacant for IM (AQ17) WEX OEX CEX AQ16 AQ15 ~ AQ8 AQ7 ~ AQ0 DQ7 ~ DQ0 VID pin (5V5%) Internal and interface control signals Internal and interface control signals Internal and interface control signals Internal address bus (A16) Internal address bus (A15 to A8) Internal address bus (A7 to A0) Internal data bus (D7 to D0) MD2 ~MD0 Normal mode RSTX Internally fixed to H 546 APPENDIX C 512K-BIT FLASH MEMORY MB90560 series s Control Status Register (FMCS) The control status register (FMCS) is situated in the flash memory interface circuit and used for writing or erasing flash memory when the CPU runs in normal mode. It cannot be used in flash memory mode. q Register structure: Control status register (FMCS) 7 Address:00000AEh Read/Write Initial value INTE (R/W) (0) 6 RDYI (R/W) (0) 5 WE (R/W) (0) 4 RDY (R/W) (0) 3 Reserved ( -) (0) 2 ( -) ( -) 1 ( -) ( -) 0 LPM (R/W) (0) q Bit description [Bit 7]: Interrupt Enable (INTE) This bit is used to cause an interrupt to the CPU when the writing or erasing of flash memory is finished. A CPU interrupt is caused when the INTE and DYINT bits are both 1. It is not caused when the INTE bit is "0". [Bit 6]: Ready Interrupt (RDYINT) This bit is set to "1" after the writing or erasing of flash memory is finished. The writing or erasing of flash memory is disabled while this bit is 0 even after the writing or erasing of flash memory is finished. Flash memory can be written or erased only after the bit is set to "1". Writing "0" in the bit clears the bit to "0", but writing "1" in the bit is ignored. The bit is set to "1" at the leading edge of the RY/BYX signal from flash memory. Read Modify Write (RMW) always reads "1" from this bit. [Bit 5]: Write Enable (WE) This bit is used to enable writing to the flash memory area. When the bit is "1", a write to the FF or FE bank becomes a write to the flash memory area. The bit is used to activate a flash memory write or erase command. A write signal is generated when the bit is "1" and MD2 to MD0 are all "1". No write signal is generated when the bit is "0" or MD2 to MD0 are not all "1". [Bit 4] : Ready (RDY) RDY is a flash memory write/erase enable bit. While the bit is "0", flash memory cannot be written or erased. Even in this situation, a read or reset command or a suspend command such as to temporarily stop a sector deletion can be accepted. Refer to the MB29F400TA specifications for more information. [Bit 3]: Reserved bit This bit is reserved for testing. Keep it as "0" for normal operation. [Bits 2 and 1]: Unused bit Leave it as "0" for normal operation. MB90560 series APPENDIX C 512K-BIT FLASH MEMORY 547 [Bit 0]: Low Power Mode (LPM) When this bit is set to "1", the "L" period of the CEX signal supplied to flash memory during access to flash memory is minimized to suppress the power consumption of flash memory. However, the access time is greatly increased compared with that when LPM is "0", and memory access is disabled when the CPU runs in high-speed mode. When LPM mode is used, therefore, run the CPU at frequencies of 4 MHz or less. RDY input RDYINT bit RDY bit 1 machine cycle s Read/Write Access Method While flash memory mode requires external-pin control for read or write access to the 1M-bit flash memory, normal mode does not require it because access timing is controlled by the flash memory interface circuit. The write access explained below is a write access to the command register to activate the automatic algorithm and means a write to flash memory. s Read/Write Access in Flash Memory Mode Table C-2 lists the pin settings for read, write, and other operations in flash memory mode. Control of these pin settings is not a problem when connecting to the flash memory writer but must satisfy the timing specifications of the individual pins in other cases. See the separate section for the timing specifications. Since data bus width is limited to eight bits in flash memory mode, fix the BYTEX pin to "0". Table C-2 Pin settings for read/write access in flash memory mode Operation Read Write Output disable Standby Hardware reset L L L H ! CEX L H H ! ! OEX H L H ! ! WEX AQ0~16 Read address Write address ! ! ! DQ0~7 DOUT DIN High-Z High-Z High-Z H H H H L RSTX 548 APPENDIX C 512K-BIT FLASH MEMORY MB90560 series q Read/write access in normal mode For a read/write access to flash memory in normal mode, the timing of the internal bus access from the CPU is converted, in the flash memory interface circuit, into flash memory access timing. In this mode, one read/write cycle completes in two internal machine clock cycles. For data access with LPM set to "0" in this mode, CEX goes "L" for every cycle. However, for data access with LPM set to "1", CEX goes "L" after the data decision of the data bus (D15 to D00). Thus, the access timing is different. (When LPM is set to 1, the access time increases and the CPU speed must be decelerated.) Internal address bits 15 to 0 corresponds to AQ15 to 0 in flash memory mode on a one-toone basis, and internal data bits 15 to 0 correspond to DQ15 to 0 on a one-to-one basis. To perform a write access to flash memory, the WE bit of the control status register must be set to "1" in advance. The WE bit prevents the automatic algorithm from malfunctioning because of an invalid write to flash memory caused by noise. Therefore, when no write access is anticipated, the WE bit should be reset to "0". When LPM is "0", no restrictions apply to read/write access to flash memory, the same as for access to other types of memory, as long as the access time is within the range of the CPU operation guarantee frequencies. When LPM is "1", the CEX timing controls read/write access and restricts the CPU operation frequencies. Therefore, to perform a read or write access with LPM set to "1", set the CPU operation frequency to 4 MHz or less. s Ready or Busy Signal The 1M-bit flash memory uses the aforementioned hardware sequence flags, i.e., data polling flag and toggle bit flag, to indicate whether the internal automatic algorithm is being executed or is finished. In addition, this memory also has hardware signals, i.e., Ready and Busy signals, available for the same purpose. The Ready and Busy signals operate differently, depending on whether the CPU runs in flash memory mode or normal mode. q Flash memory mode For a Ready or Busy signal, the RY or BYX signal from flash memory is asynchronously supplied to the RY or BYX pin for the open drain output to the outside of the chip. When a pull-up resistor is connected to VCC, several RY or BYX pins can be connected in parallel. When the output of the RY or BYX pin is "0", flash memory is busy writing or erasing. In this state, no write or erase command can be accepted. When the RY or BYX pin is set to "1" by the connection of an external pull-up resistor, flash memory is ready to accept a read, write, or erase command. In erase temporary stop mode, the RY or BYX output is set to "1" by the connection of an external pull-up resistor. q Normal mode A Ready or Busy signal is supplied as an interrupt request signal to the CPU via the flash memory interface circuit. An interrupt request is sent to the CPU when the state of flash memory changes from busy to ready while the INTE bit of the control status register (FMCS) is "1". No interrupt request is sent to the CPU even if the state of flash memory changes as above if the INTE bit of the FMCS register is "0". Clearing the RDYINT bit of the FMCS register to "0" after an interrupt request is issued to the CPU cancels the interrupt request to the CPU. This action also resets the INTE bit of the FMCS register to "0". MB90560 series APPENDIX C 512K-BIT FLASH MEMORY 549 APPENDIX D EXAMPLE OF FMC-16LX MB90F562 CONNECTION FOR SERIAL WRITING This MB90F562 supports serial on-board writing (Fujitsu standard) to flash ROM. appendix describes the specifications for serial on-board writing. s Basic Configuration The AF200 flash microcomputer programmer of Yokogawa Digital Computer Co., Ltd. is used for Fujitsu standard serial on-board writing. Host interface cable (AZ201) General-purpose common cable (AZ210) RS232C AF200 flash microcomputer programmer + memory card Clock synchronous serial MB90F553A user system Operable in stand-alone mode Figure D-1 Standard configuration for Fujitsu standard serial on-board writing s Pins used for Fujitsu standard serial on-board writing Pin MD2,MD1, MD0 P00 RSTX SIN SOT SCK Function Mode pin Write program start pin Reset pin Serial data input pin Serial data output pin Serial clock input pin If write voltage (5V10%) is supplied from the user system, this pin need not be connected to the flash microcomputer programmer. If the pin is connected to the flash microcomputer programmer, do not connect it to the power of the user system. Used also as the ground pin for the flash microcomputer programmer. UART is used in clock synchronous mode. Description Used to enable write mode for the flash microcomputer programmer. - - VCC Power supply pin VSS Ground pin Note: When the P00, SIN0, SOT0, and SCK0 pins are also used by the user system, the control circuit shown below is required. (The /TICS signal of the flash microcomputer programmer can separate the user circuit during serial writing. See the connection example shown later.) AF200 write control pin 10K AF200 /TICS pin User MB90F562 write control pin 552 APPENDIX D MB90560 series s Connection example for serial writing Figure D-2 is a connection example for serial writing. AF200 flash microcomputer programmer TAUX3 User system Connector DX10-28S or DX20-28S (19) 10k 10k MD1 10k MB90F562 MD2 TMODE TAUX (12) (23) 10K MD0 P00 /TICS (10) User /TRES 10k (5) RSTX User TTXD TRXD TCK TVPP1 (13) (27) (6) (16) (7,8, 14,15, 21,22, 1,28) SIN SOT SCK *2 Vcc User power supply Pin 1 t Vss GND Pin 14 DX10-28S DX20-28S Pins 3, 4, 9, 11, 17, 18, 20, 24, 25, and 26 are open. Pin 15 Pin 28 Pin assignments are viewed from the engagement side. Cable connector (made by Hirose Denki) DX10-28S: Right-angle type DX20-28S: Straight type Mode pin: MD2, MD1, MD0 = 011 Figure D.2 Connection example for MB90F562 serial writing MB90560 series APPENDIX D 553 Note:1. When the SIN, SOT, and SCK pins are also used by the user system, the control circuit shown on the right is required, which is the same as for P00. (The /TICS signal of the flash microcomputer programmer can separate the user circuit during serial writing.) AF200 write control pin 10K AF200 / TICS pin User MB90F562 write control pin Note:2. If the power for writing is supplied by the AF200, do not connect the power pin to the power supply of the user system. Note:3. Turn off the user system power before connecting to the AF200. s System configuration of AF200 flash microcomputer programmer (Yokogawa Digital Computer Co., Ltd.) Type AF200 AD200/ ACP AZ201 AZ210 FF001 FF001/P2 EF001/P4 Function Advanced on-board flash microcomputer programmer AC adapter (center +) (Option) Host interface cable (PCAT) General-purpose common probe (Type A) Fujitsu FMC-16LX control module for flash microcomputer 2MB PC Card (Option) 4MB PC Card (Option) For more information, contact the Sales Dept., Equipment Business Center, Yokogawa Digital Computer Co., Ltd. (Telephone: 0423-33-6224) 554 APPENDIX D MB90560 series Corrections of MB90560 Hardware Manual (CM44-10107-1E) 1. A/D CONVERTER The total error for the 3V version (MB90560L series) is max. +/-8LSB. The total error for the 5V version (MB90560 series) is max. +/-5LSB ADCS1 Register STS1-0 bits = 0,0 --> Activation by Software. STS1-0 bits = 0,1 --> Activation by Software, and Zero detection of Free Running Timer STS1-0 bits = 1,0 --> Activation by Software, and Reload Timer STS1-0 bits = 1,1 --> Activation by Software, Zero detection of Free Running Timer, and Reload Timer. 1. PPG Chapter 12.3.4.3 PPG clock control Register (PCS01/23/45) The operating clock settings fc/32 and fc/64 are not possible. If these settings are used the PPG output will stay on low level. When PPG is set to 16 bit mode with "GATE" function, the output can't produce desired waveform. Input capture register Chapter 12.3.3 (page 304 in HW-Manual) capture control register (upper) ICS23 The address for upper register 0x69 is incorrect, correct address is 0x6A. Timer Control Status Register Chapter 12.3.1.3 ( page 294 in HW-Manuel) Upper Timer control status register TCCS (bit 15-8). Description of bit8 ICRE Compare interrupt request enable bit is not correct. Enable interrupt set '1', disable interrupt set '0'. UART - synchronous mode Chapter 13.6.1 Baud Rates: synchronous Transfer Division Ratios. Page 379 in HW-Manual Table 13.6-2 Division ratio for CLK synchronization: values in Table are incorrect correct baud rates (div=4): CS2,CS1,CS0,baudrates 0, 0, 0, 4M 0, 0, 1, 2M 0, 1, 0, 1M 0, 1, 1, 500K 1, 0, 0, 250K 1, 0, 1, 125K Max. synchronous baud rate with div=1: 8Mbaud Appendix C, 512K-Bit Flash memory The Sector configuration of the Flash memory is 32K/8K/8K/16K Low Power Mode, Chapter 5.3 Bit 3 of the LPMCR is used to enter the Timer Mode. Write 0 to this bit to enter the Timer mode. Clearing this bit will enter the timer mode, regardless from the current mode of the CPU. Time Base Timer Mode, chapter 5.5.2 Time Base Timer Mode is entered by clearing Bit3 of the LPMCR register. Clearing this bit will enter the timer mode, regardless from the current mode of the CPU. last updated : 16 September'99 (tka) |
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